GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
ChangeLog:
PR ld/32372
* pdb.c (add_stream): Return NULL.
(cherry picked from commit bf447eec6d)
GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
ChangeLog:
PR ld/32372
* prdbg.c (visibility_name): Return NULL.
(cherry picked from commit eeff15bc88)
static_assert is declared in C23 so we can't reuse that identifier:
* Define our own static_assert conditionally;
* Rename "static assert" hacks to _N as we do already in some places
to avoid a conflict.
ChangeLog:
PR ld/32372
* i386-gen.c (static_assert): Define conditionally.
* mips-formats.h (MAPPED_INT): Rename identifier.
(MAPPED_REG): Rename identifier.
(OPTIONAL_MAPPED_REG): Rename identifier.
* s390-opc.c (static_assert): Define conditionally.
(cherry picked from commit 8ebe62f3f0)
GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
ChangeLog:
PR ld/32372
* elf32-ppc.c (ppc_elf_tls_setup): Return NULL.
* elf32-xtensa.c (translate_reloc_bfd_fix): Ditto.
(translate_reloc): Ditto.
* elf64-ppc.c (update_local_sym_info): Ditto.
* mach-o.c (bfd_mach_o_lookup_uuid_command): Ditto.
* xsym.c (bfd_sym_read_name_table): Ditto.
(cherry picked from commit 931e4f9b09)
This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.
Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.
This aligns GNU Assembler to LLVM Assembler.
opcodes/
* s390-opc.c (U6_18, U5_27, U6_26): Remove.
(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
as INSTR_RIE_RRUUU while retaining insn fmt mask.
(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
Z/T-bit of I3/I4 operand as significant.
gas/testsuite/
* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
Reported-by: Dominik Steenken <dost@de.ibm.com>
Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit b8b60e2d0c)
Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.
The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.
This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx
include/
* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
S390_OPERAND_OR8): Remove.
opcodes/
* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
respective insn fmt mask.
(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
mask.
* s390-dis.c (s390_print_insn_with_opcode): Mask constant
operand bits set in insn template of non-length unsigned
integer operands.
gas/
* config/tc-s390.c (s390_insert_operand): Do not OR constant
operand value bits.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a3f1e7c56a)
Document the s390-specific assembler syntax introduced by commit
aacf780bca ("s390: Allow to explicitly omit base register operand in
assembly") to omit the base register operand B in D(X,B) and D(L,B) by
coding D(X,) and D(L,).
While at it document the alternative syntax to omit the index register
operand X in D(X,B) by coding D(,B) instead of D(B).
gas/
* doc/c-s390.texi (s390 Operands): Document syntax to omit base
register operand.
Fixes: aacf780bca ("s390: Allow to explicitly omit base register operand in assembly")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit e75cfa9f0f)
