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6336 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
H.J. Lu
|
2234eee61c |
x86: CET v2.0: Update incssp and setssbsy
Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated. |
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H.J. Lu
|
c2f7640243 |
x86: CET v2.0: Rename savessp to saveprevssp
Replace savessp with saveprevssp for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace savessp with saveprevssp. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated. |
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H.J. Lu
|
9fef80d683 |
x86: CET v2.0: Update NOTRACK prefix
Update NOTRACK prefix handling to support memory indirect branch for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (md_assemble): Update NOTRACK prefix check. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with memory indirect branch. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove memory indirect branch with NOTRACK prefix. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. opcodes/ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" and "jmp{&|}". (NOTRACK_Fixup): Support memory indirect branch with NOTRACK prefix. |
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Thomas Preud'homme
|
3d030cdb4a |
[ARM] Allow Thumb division as an extension for ARMv7
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to allow ARMv7 to be selected in automatic architecture selection in presence of Thumb division instructions. === Motivation === any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect autodetection code to select ARMv7 in presence of Thumb integer division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do not contain these instructions and the idiv extension is only available for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic detection code proposed in the subsequent patch of the series ARMv7 is refused if a Thumb division instruction is present. === Patch description === This patch adds a new "idiv" extension after the existing one that is available to all ARMv7 targets. This new entry is ignored by all current code parsing arm_extensions such that it would be unavailable on the command-line and remain a purely internal hack, easily removed in favor of a better solution later. This is considered though by the subsequent patch reworking automatic detection of build attributes such that ARMv7 is allowed to match in present of Thumb division instructions. For good measure, comments are added in all instances of code browsing arm_extensions to mention the expected behavior in case of duplicate entries as well as a new testcase. 2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable Thumb division for ARMv7 architecture. (arm_parse_extension): Document expected behavior for duplicate entries. (s_arm_arch_extension): Likewise. * testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test. * testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for above test. |
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Thomas Preud'homme
|
54bab2816d |
[ARM] Rework selection of feature bits to base build attributes on
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to set the feature bits on which to decide what the build attributes should be according to the mode (autodetection, user specified architecture or CPU, or -march/-mcpu=all). === Motivation === Currently, the flags variable which is used to determine the build attribute is constructed from the instruction used (arm_arch_used and thumb_arch_used) as well as the user specified architecture or CPU (selected_cpu). This means when several .arch are specified the resulting feature bits can be such that no architecture provide them all and can thus result in incorrect Tag_CPU_arch. See for instance what having both .arch armv8-a and .arch armv8-m.base would result in. This is not caught by the testsuite because of further bugs in the Tag_CPU_arch build attribute value selection logic (see next patch in the series). === Patch description === As one would expect, this patch solves the problem by setting flags from feature bits used if in autodetection mode [1] and from selected_cpu otherwise. The logic to set arm_ext_v1, arm_ext_v4t and arm_ext_os feature bits is also moved to only run in autodetection mode since otherwise the architecture or CPU would have a consistent set of feature bits already. [1] No architecture or CPU was specified by the user 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Populate flags from feature bits used or selected_cpu depending on whether a CPU was selected by the user. |
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Thomas Preud'homme
|
6c290d5387 |
[ARM] Simplify Tag_DSP_extension selection logic
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to simplify the logic to decide whether to set Tag_DSP_extension. === Motivation === To decide whether to set Tag_DSP_extension, the current code was checking whether the flags had DSP instruction but the architecture selected for Tag_CPU_arch did not have any. This was necessary because extension feature bit were not available separately. This is no longer necessary and can be simplified. === Patch description === The patch change the logic to set Tag_DSP_extension to check whether any DSP feature bit is set in the extension feature bit, as per the definition of that build attribute. The patch also removes all definitions of arm_arch which is now unneeded. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to decide whether to set Tag_DSP_extension build attribute value. Remove now useless arm_arch variable. |
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Thomas Preud'homme
|
c168ce07e5 |
[ARM] Keep separation between extensions and architecture bits throughout execution
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to keep the distinction between architecture feature bits and extension ones after parsing has occured. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. The previous patch in the patch series makes the distinction possible when parsing -mcpu and .cpu directives but the distinction gets lost after. Similarly feature bits contributed by extensions in -march or .arch_extensions directive are mixed together with architecture extensions. === Patch description === The patch adds new feature bit pointer for extension feature bits. Information from the parsing regarding extensions can then be kept separate in those. This requires adapting arm_parse_extension to deal with two feature bits, allowing the architecture bits to be marked as const. It also requires extra care when setting cpu_variant and selected_cpu because the extension bits are optional since there might not be any extension in use. Note that contrary to cpu feature bits, the extension feature bits are made read/write and are always dynamically allocated. This allows to unconditionally free them in arm_md_post_relax added for this occasion, thereby fixing a longstanding memory leak when arm_parse_extension was invoked (XNEW of ext_fset without corresponding XDELETE). Introduction of arm_md_post_relax is necessary to only free the extension feature bits after aeabi_set_attribute_string has been called for the last time. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (dyn_mcpu_ext_opt): New static variable. (dyn_march_ext_opt): Likewise. (md_begin): Copy extension feature bits alongside architecture ones. Merge extensions feature bits in selected_cpu and cpu_variant if there is some. (arm_parse_extension): Pass architecture and extension feature bits in separate parameters, with architecture bits being read only. Update **opt_p directly rather than *ext_set and initialize it if needed. (arm_parse_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Adapt to change in parameters of arm_parse_extension. (arm_parse_arch): Adapt to change in parameters of arm_parse_extension. (aeabi_set_attribute_string): Make function static. (arm_md_post_relax): New function. (s_arm_cpu): Stop merging architecture and extension feature bits and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them respectively. Merge extension feature bits in cpu_variant if there is any. (s_arm_arch): Reset extension feature bit. Set selected_cpu from *mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for consistency with s_arm_cpu. (s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than selected_cpu, allocating it before hand if needed. Set selected_cpu from it and then cpu_variant. (s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant. * config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax. (aeabi_set_public_attributes): Delete external declaration. (arm_md_post_relax): Declare externally. |
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Thomas Preud'homme
|
996b5569bf |
[ARM] Separate extensions from architectures in arm_cpus
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to distinguish for a CPU the feature bits coming from its architecture from the feature bits coming from extension(s) available in this CPU. === Motivation === This distinction is necessary to allow the Tag_CPU_arch build attribute value to be exactly as per the architecture of the selected CPU. With mixed architecture and extension feature bit, it is impossible to find an architecture with an exact match of feature bit and the build attribute value logic must then select the closest match which might not be the right architecture. === Patch description === The patch creates a new field in the arm_cpus table to hold the feature set for the extensions available in each CPU. The existing architecture feature set is then updated to remove those feature bit. The patch also takes advantage of all the lines being changed to reindent the whole table. Note: This patch *adds* a memory leak due to mcpu_cpu_opt sometimes pointing to dynamically allocated feature bits which is never freeed. The subsequent patch in the series solves this issue as well as a preexisting identical issue in arm_parse_extension. The patches are kept separate for ease of review since they are both big enough already. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_cpu_option_table): New ext field. (ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical name field just after the name field. (arm_cpus): Move extension feature bit from value field to ext field, reorder parameter according to changes in ARM_CPU_OPT and reindent. (arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and ext field from the selected arm_cpus entry. (s_arm_cpu): Likewise. |
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James Greenhalgh
|
1e29262747 |
Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 architecture.
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75. * doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75. |
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H.J. Lu
|
8cac017d35 |
i386-dis: Add 2 tests with invalid bnd register
PR binutils/21594 * testsuite/gas/i386/mpx.s: Add 2 tests with invalid bnd register. * testsuite/gas/i386/x86-64-mpx.s: Likewise. * testsuite/gas/i386/mpx.d: Updated. * testsuite/gas/i386/x86-64-mpx.d: Likewise. |
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Max Filippov
|
f7e16c2a9c |
xtensa: don't expect XCHAL_* macros to be constant
Get rid of the assumption that XCHAL_* macros are preprocessor constants: don't use them in preprocessor conditionals or in static variable initializers. 2017-06-14 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (elf_xtensa_be_plt_entry, elf_xtensa_le_plt_entry): Add dimension for the ABI to arrays, keep both windowed and call0 ABI PLT definitions. (elf_xtensa_create_plt_entry): Use selected ABI to choose upper elf_xtensa_*_plt_entry endex. (ELF_MAXPAGESIZE): Fix at minimal supported MMU page size. gas/ * config/tc-xtensa.c (density_supported, xtensa_fetch_width, absolute_literals_supported): Leave definitions uninitialized. (directive_state): Leave entries for directive_density and directive_absolute_literals initialized to false. (xg_init_global_config, xtensa_init): New functions. * config/tc-xtensa.h (TARGET_BYTES_BIG_ENDIAN): Define as 0. (HOST_SPECIAL_INIT): New definition. (xtensa_init): New declaration. |
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Michael Collison
|
62e20ed45e |
Add support for AArch64 system register names IP0, IP1, FP and LR.
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0, IP1, FP, and LR as register aliases of register 16, 17, 29 and 30 respectively. * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic prohibiting register 'lr' which is now an alias. * testsuite/gas/aarch64/diagnostic.s: Remove instruction utilizing register 'lr' which is now an alias. |
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Jiong Wang
|
5c8ed6a4a1 |
[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-A
For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in
Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through
the "reject_bad_reg" macro and several scattered checks.
This patch only rejects REG_SP in "reject_bad_reg" and several related places
for legacy architectures before ARMv8-A. I have checked those affected instructions
, all of them qualify such relaxations.
Testcases adjusted accordingly.
* ld-sp-warn.d was written without .arch and without -march options passed.
By default it assumes all architectures, so I deleted the REG_SP warning
on ldrsb as it's supported on ARMv8-A. There are actually quite a few
seperate tests on other architectures, for example ld-sp-warn-v7.l etc.,
so there the test for ldrsb on legacy architectures are still covered.
* sp-pc-validations-bad-t has been extended to armv8-a.
* strex-bad-t.d restricted on armv7-a.
* Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*.
gas/
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
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Jim Wilson
|
61756f84ee |
Drop arm support for falkor/qdf24xx targets, not present in released hardware.
gas/ * config/tc-arm.c (arm_cpus): Delete falkor and qdf24xx entries. * doc/c-arm.texi (-mcpu): Likewise. |
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Anton Kolesov
|
940171d086 |
[ARC] Add arc-cpu.def with processor definitions
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types) into a separate file arc-cpu.def. This will allow reuse of CPU type definition in multiple places where it might be needed, for example in disassembler. This will help ensure that gas and disassembker use same option values for CPUs. arc-cpu.def file relies on preprocessor macroses which are defined somewhere else. This for example multiple C files to include arc-cpu.def, but define different macroses, therefore creating different structures. include/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * elf/arc-cpu.def: New file. gas/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * config/tc-arc.c (cpu_types): Include arc-cpu.def Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com> |
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H.J. Lu
|
6e92fed594 |
x86: Update notrackbad tests for non-ELF targets
* gas/testsuite/gas/i386/notrackbad.l: Updated for non-ELF targets. * gas/testsuite/gas/i386/x86-64-notrackbad.l: Likewise. |
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claziss
|
6e3f3473e2 |
[ARC] Reformat error messages.
gas/ 2017-05-23 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_apply_fix): Use as_bad_where. (assemble_insn): Use as_bad. |
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H.J. Lu
|
04ef582ace |
x86: Add NOTRACK prefix support
For register indirect branches, NOTRACK prefix (0x3e), which is also the DS segment register prefix, can be used to ignore the CET indirect branch track. gas/ * config/tc-i386.c (REX_PREFIX): Changed to 7. (NOTRACK_PREFIX): New. (MAX_PREFIXES): Changed to 8. (_i386_insn): Add notrack_prefix. (PREFIX_GROUP): Add PREFIX_DS. (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE. (md_assemble): Check if NOTRACK prefix is supported. (parse_insn): Set notrack_prefix and issue an error for other prefixes after NOTRACK prefix. * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix. * testsuite/gas/i386/notrack-intel.d: New file. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrack.s: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/notrackbad.s: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. include/ * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New. opcodes/ * i386-dis.c (NOTRACK_Fixup): New. (NOTRACK): Likewise. (NOTRACK_PREFIX): Likewise. (last_active_prefix): Likewise. (reg_table): Use NOTRACK on indirect call and jmp. (ckprefix): Set last_active_prefix. (prefix_name): Return "notrack" for NOTRACK_PREFIX. * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. * i386-opc.h (NoTrackPrefixOk): New. (i386_opcode_modifier): Add notrackprefixok. * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. Add notrack. * i386-tbl.h: Regenerated. |
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Jiong Wang
|
3c0367d0e2 |
[AArch64, gas] Support ILP32 triplet aarch64*-linux-gnu_ilp32
This patch allows AArch64 GAS defaulting to ILP32 if it is configured with
aarch64*-linux-gnu_ilp32.
"md_after_parse_args" is implemented to update ABI into ILP32 if DEFAULT_ARCH is
"aarch64:32".
gas/
* configure.tgt: Set "arch" to "aarch64" if ${cpu} equals "aarch64".
Recognize the new triplet name aarch64*-linux-gnu_ilp32.
* configure.ac: Output DEFAULT_ARCH macro for AArch64.
* configure: Regenerate.
* config/tc-aarch64.h (aarch64_after_parse_args): New declaration.
(md_after_parse_args): New define.
* config/tc-aarch64.c (aarch64_abi_type): New enumeration
AARCH64_ABI_NONE.
(DEFAULT_ARCH): New define.
(aarch64_abi): Set default value to AARCH64_ABI_NONE.
(aarch64_after_parse_args): New function.
|
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Jose E. Marchesi
|
6451799480 |
binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
|
||
|
Jose E. Marchesi
|
ae0264a647 |
gas: fix tests call-relax and asi-bump-warn in 32-bit SPARC ELF targets
Tested in targets: sparc-aout sparc-linux sparc-vxworks sparc64-linux 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/call-relax.d: Support 32-bit targets. * testsuite/gas/sparc/sparc.exp (gas_64_check): Use -64 to run asi-bump-warn. |
||
eorg-Johann Lay
|
f4203b2b88 |
Update avrxmega3 linker emulation to support avrxmega2 devices with flash memory visible in the SRAM address range.
PR ld/21472
ld * emulparams/avrxmega3.sh (RODATA_PM_OFFSET): Set to 0x8000.
* scripttempl/avr.sc
(__RODATA_PM_OFFSET__) [RODATA_PM_OFFSET]: Use RODATA_PM_OFFSET
as default if not already defined.
(.data) [!RODATA_PM_OFFSET]: Don't include .rodata and friends.
(.rodata) [RODATA_PM_OFFSET]: Put at an offset of
__RODATA_PM_OFFSET__.
gas * config/tc-avr.c (mcu_types): Add entries for: attiny416,
attiny417, attiny816, attiny817.
|
||
Alan Modra
|
535b785fb0 |
Don't compare boolean values against TRUE or FALSE
bfd/ * arc-got.h: Don't compare boolean values against TRUE or FALSE. * elf-m10300.c: Likewise. * elf.c: Likewise. * elf32-arc.c: Likewise. * elf32-bfin.c: Likewise. * elf32-m68k.c: Likewise. * elf32-nds32.c: Likewise. * elf32-tilepro.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-tilegx.c: Likewise. * mach-o.c: Likewise. * peXXigen.c: Likewise. * vms-alpha.c: Likewise. * vms-lib.c: Likewise. opcodes/ * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. binutils/ * strings.c: Don't compare boolean values against TRUE or FALSE. gas/ * config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE. * config/tc-hppa.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-score7.c: Likewise. ld/ * emultempl/elf32.em: Don't compare boolean values against TRUE or FALSE. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. |
||
|
Alan Modra
|
91cb9803fc |
Allow target files access to default TC_FORCE_RELOCATION defines
* write.c (GENERIC_FORCE_RELOCATION_LOCAL): Define. (TC_FORCE_RELOCATION_LOCAL): Use it. (GENERIC_FORCE_RELOCATION_SUB_SAME): Define. (TC_FORCE_RELOCATION_SUB_SAME): Use it. * config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL, TC_FORCE_RELOCATION_SUB_SAME): Use GENERIC defines. * config/tc-aarch64.h: Similarly. * config/tc-avr.h: Similarly. * config/tc-cris.h: Similarly. * config/tc-i386.h: Similarly. * config/tc-i960.h: Similarly. * config/tc-ia64.h: Similarly. * config/tc-microblaze.h: Similarly. * config/tc-mips.h: Similarly. * config/tc-msp430.h: Similarly. * config/tc-nds32.h: Similarly. * config/tc-pru.h: Similarly. * config/tc-riscv.h: Similarly. * config/tc-rl78.h: Similarly. * config/tc-s390.h: Similarly. * config/tc-sh.h: Similarly. * config/tc-sh64.h: Similarly. * config/tc-sparc.h: Similarly. * config/tc-xtensa.h: Similarly. * config/tc-mn10300.h: Similarly. (GENERIC_FORCE_RELOCATION_LOCAL): Define. * config/tc-msp430.c (msp430_force_relocation_local): Modify to be addition to rather than replacement of standard TC_FORCE_RELOCATION_LOCAL. |
||
Nick Clifton
|
52a86f843b |
Fix use of ARM ADR and ADRl pseudo-instructions with thumb function symbols.
PR gas/21458 * config/tc-arm.c (do_adr): If the ADR involves a thumb function symbol, ensure that the T bit will be set. (do_adrl): Likewise. (do_t_adr): Likewise. * testsuite/gas/arm/pr21458.s: New test. * testsuite/gas/arm/pr21458.d: New test driver. |
||
Maciej W. Rozycki
|
b32465c97c |
MIPS16e2: Add new MIPS16e2 relaxation GAS and LD tests
Verify MIPS16 PC-relative instruction relaxation using the MIPS16e2 LUI instruction rather than an LI/SLL instruction pair. gas/ * testsuite/gas/mips/mips16-pcrel-1.d: Remove `-mips3' from `as' flags. * testsuite/gas/mips/mips16-pcrel-pic-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-5.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-5.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: Likewise. * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-2.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-3.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-7.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d: Likewise. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-8.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-9.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-1.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-2.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-3.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-5.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-7.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-6.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-1.l: Adjust line numbers. * testsuite/gas/mips/mips16-pcrel-1.s: Adjust for alignment preservation between MIPS16 and MIPS16e2 code. * testsuite/gas/mips/mips.exp: Run MIPS16 relaxation tests over all MIPS16 architectures. ld/ * testsuite/ld-mips-elf/mips16e2-pcrel-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-1.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-2.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-addend-6.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n32-1.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-0.d: New test. * testsuite/ld-mips-elf/mips16e2-pcrel-n64-sym32-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. |
||
|
Maciej W. Rozycki
|
3f3467ffc4 |
MIPS16e2: Add new MIPS16e2 ASE binutils and GAS tests
Verify MIPS16e2 ASE instruction assembly, disassembly and object file flags. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Add `-mips3' to `as' flags. * testsuite/binutils-all/mips/mips16e2-undecoded.d: New test. * testsuite/binutils-all/mips/mips16e2-extend-insn.d: New test. * testsuite/binutils-all/mips/mips16-undecoded.s: Remove `.module mips3'. * testsuite/binutils-all/mips/mips.exp: Run the new tests. gas/ * testsuite/gas/mips/mips16e2.d: New test. * testsuite/gas/mips/mips16e2-mt.d: New test. * testsuite/gas/mips/mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test. * testsuite/gas/mips/mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test. * testsuite/gas/mips/mips16e2-hilo.d: New test. * testsuite/gas/mips/mips16e2-hilo-n32.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.d: New test. * testsuite/gas/mips/mips16e2-imm-error.d: New test. * testsuite/gas/mips/elf_ase_mips16e2.d: New test. * testsuite/gas/mips/elf_ase_mips16e2-2.d: New test. * testsuite/gas/mips/elf-rel9-mips16e2.d: New test. * testsuite/gas/mips/mips16e2-lui.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test. * testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test. * testsuite/gas/mips/mips16e2@lui-2.d: New test. * testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output. * testsuite/gas/mips/mips16e2-imm-error.l: New stderr output. * testsuite/gas/mips/mips16e2@lui-2.l: New stderr output. * testsuite/gas/mips/mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-mt.s: New test source. * testsuite/gas/mips/mips16e2-sub.s: New test source. * testsuite/gas/mips/mips16e2-mt-sub.s: New test source. * testsuite/gas/mips/mips16e2-hilo.s: New test source. * testsuite/gas/mips/mips16e2-reloc-error.s: New test source. * testsuite/gas/mips/mips16e2-imm-error.s: New test source. * testsuite/gas/mips/elf-rel9-mips16e2.s: New test source. * testsuite/gas/mips/mips16e2-lui.s: New test source. * testsuite/gas/mips/mips.exp: Expand `mips32r2-sync', `mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2 architectures. Run the new tests. |
||
|
Maciej W. Rozycki
|
70ab592fba |
MIPS16e2: Add MIPS16e2 ASE GAS test infrastructure
Define a new 32-bit and 64-bit MIPS16e2 test architecture and adjust existing tests now run against these architectures accordingly. gas/ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add `mips16e2@' prefix. (run_list_test_arch): Likewise. (mips16e2-32, mips16e2-64): New architectures. * testsuite/gas/mips/mips16e2-32@mips16-macro.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-macro-t.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-macro-e.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-insn-t.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-insn-e.d: New test. * testsuite/gas/mips/mips16e2-32@mips16e-64.d: New test. * testsuite/gas/mips/mips16e2-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e2-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e2@relax-swap3.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: Remove `source' tag. Add `-I$srcdir/$subdir' to `as' flags. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: Likewise. * testsuite/gas/mips/mips16e2-32@mips16-macro.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-macro-t.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-macro-e.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-insn-t.l: New stderr output. * testsuite/gas/mips/mips16e2-32@mips16-insn-e.l: New stderr output. * testsuite/gas/mips/mips16-sub.s: Add `.set nomips16e2'. * testsuite/gas/mips/mips16e-sub.s: Likewise. * testsuite/gas/mips/mips16e-64-sub.s: Likewise. * testsuite/gas/mips/mips16-asmacro.s: Remove `.set mips32'. * testsuite/gas/mips/mips16-32@mips16-asmacro.s: New test source. * testsuite/gas/mips/mips16-64@mips16-asmacro.s: New test source. |
||
|
Maciej W. Rozycki
|
25499ac7ee |
MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
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Maciej W. Rozycki
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20c59b843a |
MIPS16/GAS: Improve [32768,65535] out-of-range operand error diagnostics
Improve out-of-range operand error diagnostics for invalid values in the [32768,65535] range used for a signed 16-bit immediate, making the message consistent with that used for other invalid values, e.g.: foo.s:1: Error: operand 2 must be an immediate expression `addiu $2,$gp,32768' foo.s:2: Error: invalid operands `lw $2,32768($gp)' vs: foo.s:3: Error: operand 3 out of range `addiu $2,$gp,-32769' foo.s:4: Error: operand 2 out of range `lw $2,-32769($gp)' This case does not currently trigger however, for two reasons. First, for regular MIPS and microMIPS assembly in the case of no match caused by `match_int_operand' here, the function is always called again from `mips_ip' via `match_insns', `match_insn' and then `match_operand' for the same opcode table's entry with `lax_match' set to TRUE, in which case the attempt to match succeeds and no error is issued. Second, in the case of MIPS16 assembly no call to `match_int_operand' is made at all for signed 16-bit immediates, because such immediates are currently only matched with extensible instructions, and these are handled in `match_mips16_insn' via `match_expression' directly rather than via `match_operand'. This will change for MIPS16 code with MIPS16e2 support introduced, where non-extensible instructions accepting signed 16-bit immediates will be added, so make the case work well right from the start: foo.s:1: Error: operand 3 out of range `addiu $2,$gp,32768' foo.s:2: Error: operand 2 out of range `lw $2,32768($gp)' gas/ * config/tc-mips.c (match_int_operand): Call `match_out_of_range' before returning failure for 0x8000-0xffff values conditionally allowed. |
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Maciej W. Rozycki
|
602b88e3ab |
MIPS16/GAS: Improve non-constant operand error diagnostics
Improve operand error diagnostics for non-constant expressions used for a 16-bit immediate, making the message more descriptive and indicating the offending operand, e.g.: foo.s:1: Error: invalid operands `lui $2,foo-bar' will show as: foo.s:1: Error: operand 2 must be constant `lui $2,foo-bar' This case does not currently trigger however, for two reasons. First, for regular MIPS and microMIPS assembly in the case of no match caused by `match_int_operand' here, the function is always called again from `mips_ip' via `match_insns', `match_insn' and then `match_operand' for the same opcode table's entry with `lax_match' set to TRUE, in which case the attempt to match succeeds and no error is issued. Second, in the case of MIPS16 assembly no call to `match_int_operand' is made at all for 16-bit immediates, because such immediates are currently only matched with extensible instructions, and these are handled in `match_mips16_insn' via `match_expression' directly rather than via `match_operand'. This will change for MIPS16 code with MIPS16e2 support introduced, where non-extensible instructions accepting 16-bit immediates will be added, so make the case work well right from the start. gas/ * config/tc-mips.c (match_int_operand): Call `match_not_constant' before returning failure for a non-constant 16-bit immediate conditionally allowed. |
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Maciej W. Rozycki
|
c96425c560 |
MIPS/GAS: Improve bignum operand error diagnostics
Improve bignum operand error diagnostics for cases where a constant would be accepted and report them as range errors, also indicating the offending operand and instruction, e.g.: $ cat bignum.s addiu $2, 0x10000000000000000 break 0x10000000000000000 $ as -o bignum.o bignum.s bignum.s:1: Error: bignum invalid bignum.s:2: Error: operand 1 must be constant `break 0x10000000000000000' $ now show as: $ as -o bignum.o bignum.s bignum.s:1: Error: operand 2 out of range `addiu $2,0x10000000000000000' bignum.s:2: Error: operand 1 out of range `break 0x10000000000000000' $ gas/ * config/tc-mips.c (match_const_int): Call `match_out_of_range' rather than `match_not_constant' for unrelocated operands retrieved as an `O_big' expression. (match_int_operand): Call `match_out_of_range' for relocatable operands retrieved as an `O_big' expression. (match_mips16_insn): Call `match_out_of_range' for relaxable operands retrieved as an `O_big' expression. * testsuite/gas/mips/addiu-error.d: New test. * testsuite/gas/mips/mips16@addiu-error.d: New test. * testsuite/gas/mips/micromips@addiu-error.d: New test. * testsuite/gas/mips/break-error.d: New test. * testsuite/gas/mips/lui-1.l: Adjust error message. * testsuite/gas/mips/addiu-error.l: New stderr output. * testsuite/gas/mips/mips16@addiu-error.l: New stderr output. * testsuite/gas/mips/micromips@addiu-error.l: New stderr output. * testsuite/gas/mips/break-error.l: New stderr output. * testsuite/gas/mips/addiu-error.s: New test source. * testsuite/gas/mips/break-error.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. |
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Maciej W. Rozycki
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1a7bf198b6 |
MIPS16/GAS: Improve non-immediate operand error diagnostics
Improve non-immediate operand error diagnostics for extensible MIPS16
instructions and make it match corresponding regular MIPS and microMIPS
handling, e.g:
$ cat addiu.s
addiu $4, $3, $2
$ as -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2'
$ as -mips16 -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: invalid operands `addiu $4,$3,$2'
$
To do so observe that for extensible MIPS16 instructions and a non-PC
relative operand this case is handled by an explicit OT_INTEGER check in
`match_mips16_insn' returning a failure right away and consequently
preventing a call to `match_expression' from being made. As from commit
|
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Maciej W. Rozycki
|
e295202f60 |
MIPS16/GAS: Improve disallowed relocation operand error diagnostics
Improve disallowed relocation operand error diagnostics for MIPS16 code and make it match corresponding regular MIPS and microMIPS handling, e.g: $ cat sltu.s sltu $2, %lo(foo) $ as -o sltu.o sltu.s sltu.s: Assembler messages: sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)' $ as -mips16 -o sltu.o sltu.s sltu.s: Assembler messages: sltu.s:1: Error: invalid operands `sltu $2,%lo(foo)' $ To do so call `match_not_constant' from `match_mips16_insn' whenever a disallowed relocation operation has been noticed, like `match_const_int' does, making reporting consistent: $ as -mips16 -o sltu.o sltu.s sltu.s: Assembler messages: sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)' $ gas/ * config/tc-mips.c (match_mips16_insn): Call `match_not_constant' for a disallowed relocation operation. * testsuite/gas/mips/mips16-reloc-error.d: New test. * testsuite/gas/mips/mips16-reloc-error.l: New stderr output. * testsuite/gas/mips/mips16-reloc-error.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. |
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Maciej W. Rozycki
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c76081bc87 |
MIPS/GAS/testsuite: Convert LUI list tests to dump tests
gas/ * testsuite/gas/mips/lui-1.d: New test. * testsuite/gas/mips/lui-2.d: New test. * gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests into the new tests. |
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Maciej W. Rozycki
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a54d5f8bb3 |
MIPS/GAS: Update `match_const_int' description
Remove a stale reference to FALLBACK parameter from the description of
`match_const_int', matching commit
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Maciej W. Rozycki
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32035f5151 |
MIPS/GAS/doc: Refer to .module' rather than .set'
Complement commit
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Maciej W. Rozycki
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be3f100674 |
MIPS/GAS: Unify GP-relative percent-ops
For a reason that is unclear commit
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Maciej W. Rozycki
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a4f8991513 |
MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand in the hexadecimal rather than decimal numeral system and add respective operandless variants with an implicit 0 operand, making our handling of these instructions consistent with how we have processed their regular MIPS and microMIPS counterparts since forever. opcodes/ * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand type to hexadecimal. (mips16_opcodes): Add operandless "break" and "sdbbp" entries. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK and SDBBP disassembly. gas/ * testsuite/gas/mips/mips16.d: Adjust BREAK disassembly. * testsuite/gas/mips/mips16-64@mips16.d: Likewise. * testsuite/gas/mips/mips16-64.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-64.d: Likewise. * testsuite/gas/mips/mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise. * testsuite/gas/mips/mips16-sub.d: Likewise. * testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise. |
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Maciej W. Rozycki
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99e2d67a0e |
MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.
References:
[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 305
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 481
opcodes/
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
"sync_rmb" and "sync_wmb" as aliases.
* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
gas/
* testsuite/gas/mips/mips32r2-sync-1.d: New test.
* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
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Maciej W. Rozycki
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7f401e8417 |
MIPS/GAS/testsuite: Convert ISA override list tests to dump tests
And remove the zillion duplicate sources. Also `mips1@isa-override-2.l' is the same as `r3000@isa-override-2.l', so remove the latter too, now that `r3000@isa-override-2.d' can name a file to match stderr output against. gas/ * testsuite/gas/mips/isa-override-2.d: New test. * testsuite/gas/mips/mips1@isa-override-2.d: New test. * testsuite/gas/mips/r3000@isa-override-2.d: New test. * testsuite/gas/mips/r3900@isa-override-2.d: New test. * testsuite/gas/mips/mips2@isa-override-2.d: New test. * testsuite/gas/mips/mips32@isa-override-2.d: New test. * testsuite/gas/mips/mips32r2@isa-override-2.d: New test. * testsuite/gas/mips/mips32r3@isa-override-2.d: New test. * testsuite/gas/mips/mips32r5@isa-override-2.d: New test. * testsuite/gas/mips/mips32r6@isa-override-2.d: New test. * testsuite/gas/mips/octeon3@isa-override-2.d: New test. * testsuite/gas/mips/r3000@isa-override-2.l: Remove list test. * testsuite/gas/mips/mips1@isa-override-2.s: Remove test source. * testsuite/gas/mips/r3000@isa-override-2.s: Remove test source. * testsuite/gas/mips/r3900@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips2@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: Remove test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: Remove test source. * testsuite/gas/mips/octeon3@isa-override-2.s: Remove test source. * gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests into the new tests. |
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Maciej W. Rozycki
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9fc1813479 |
MIPS/GAS/testsuite: Correct swapped MIPS16e subset test names
Correct the test names swapped between common and 64-bit MIPS16e subset tests. gas/ * testsuite/gas/mips/mips16e-sub.d: Correct test name. * testsuite/gas/mips/mips16-32@mips16e-sub.d: Likewise. * testsuite/gas/mips/mips16-64@mips16e-sub.d: Likewise. * testsuite/gas/mips/mips16e-64-sub.d: Likewise. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: Likewise. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: Likewise. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: Likewise. |
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Maciej W. Rozycki
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f78c0b9158 |
MIPS/GAS/testsuite: Remove stale `mips16-macro' list test output
Complement commit
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Maciej W. Rozycki
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58667758b1 |
MIPS/GAS/testsuite: Remove last remnants of ECOFF support
Complement commit |
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Claudiu Zissulescu
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53a346d823 |
[ARC] Object attributes.
gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
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Maciej W. Rozycki
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8507b6e797 |
MIPS16/GAS: Relax 32-bit non-PIC PC-relative synthetic instructions
Implement the relaxation of MIPS16 PC-relative synthetic LA, DLA, LW and LD instructions to an equivalent sequence of instructions produced where the address operand requested is out of range, absolute or requires linker relocation, for ABIs that use 32-bit addressing and non-PIC code. The sequence generated uses the register specified for the destination operand as a temporary and begins with LI to load the high 16-bit part of the address, then continues with SLL by 16 bits to move that part into place and finally completes with a suitable operation corresponding to the synthetic instruction used, one of: 2-argument ADDIU, 2-argument DADDIU, absolute LW, and absolute LD respectively, providing the low 16-bit part of the address. All instructions use the extended encoding. As a special exception accept absolute addresses for relaxation even in PIC code. For example: la $2, 0x12345678 produces code as: li $2, 0x1234 sll $2, $2, 16 addiu $2, 0x5678 would. Where linker relocation is required emit an R_MIPS16_HI16 relocation on the initial LI instruction and an R_MIPS16_LO16 relocation on the final operation. For example (where `foo' is not local): lw $3, foo produces code as: li $3, %hi(foo) sll $3, $3, 16 lw $3, %lo(foo)($3) would. Emit assembly warnings as appropriate where this new relaxation triggers in the `nomacro' mode or for an instruction manually placed in a branch delay slot in the `noreorder' mode. Refrain from relaxation where an explicit instruction size suffix has been used and in the `noautoextend' mode. gas/ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and `nomacro' flags. (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO): New macros. (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT) (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT) (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED) (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED) (RELAX_MIPS16_MARK_ALWAYS_EXTENDED) (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits. (RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO) (RELAX_MIPS16_CLEAR_MACRO): New macros. (append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and `mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE. (mips16_macro_frag): New function. (md_estimate_size_before_relax): Handle HI16/LO16 relaxation. (mips_relax_frag): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/mips16@relax-swap3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16e@relax-swap3.d: New test subarchitecture. * testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing NOP padding. * testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16@relax-swap3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file. * testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file. * testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file. * testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file. * testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file. * testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file. * testsuite/gas/mips/relax-swap3.s: Adjust trailing padding. * testsuite/gas/mips/mips16-pcrel-0.d: New test. * testsuite/gas/mips/mips16-pcrel-1.d: New test. * testsuite/gas/mips/mips16-pcrel-2.d: New test. * testsuite/gas/mips/mips16-pcrel-3.d: New test. * testsuite/gas/mips/mips16-pcrel-4.d: New test. * testsuite/gas/mips/mips16-pcrel-5.d: New test. * testsuite/gas/mips/mips16-pcrel-pic-0.d: New test. * testsuite/gas/mips/mips16-pcrel-pic-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n32-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n32-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-0.d: New test. * testsuite/gas/mips/mips16-pcrel-n64-1.d: New test. * testsuite/gas/mips/mips16-pcrel-delay-0.d: New test. * testsuite/gas/mips/mips16-pcrel-delay-1.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-4.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-5.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-6.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-7.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test. * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d: New test. * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d: New test. * testsuite/gas/mips/mips16-pcrel-0.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-2.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-3.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-4.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-5.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr output. * testsuite/gas/mips/mips16-pcrel-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-2.s: New test source. * testsuite/gas/mips/mips16-pcrel-3.s: New test source. * testsuite/gas/mips/mips16-pcrel-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source. * testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source. * testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source. * testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test. * testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-pcrel-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-1.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: New test. * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. |
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Nick Clifton
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e78bb25cb6 |
Prevent a seg-fault in the assembler when provided with a bogus input source file.
PR gas/20941 * symbols.c (snapshot_symbol): Handle the case where resolve_expression returns a local symbol. |
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Maciej W. Rozycki
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82d808edbc |
MIPS16/GAS: Fix absolute references with PC-relative synthetic instructions
Complement commit
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Maciej W. Rozycki
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14f72d45a2 |
MIPS16/GAS: Factor out duplicate symbol value conversion code
Factor out and consolidate duplicate section-relative to PC-relative symbol value conversion in `mips16_extended_frag' and `md_convert_frag' used for MIPS16 relaxation, observing that the final calculation in the latter function implies `stretch == 0'. Sanitize the formatting of code moved. gas/ * config/tc-mips.c (mips16_pcrel_val): New function, factored out from... (mips16_extended_frag): ... here. (md_convert_frag): Use `mips16_pcrel_val' rather than repeated code in MIPS16 relaxation, with `stretch' hardcoded to 0. |
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Maciej W. Rozycki
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1425c41dcd |
MIPS16/GAS: Rename the LONG_BRANCH relaxation flag
Following commit |