Commit Graph

18009 Commits

Author SHA1 Message Date
Nick Clifton
6ef35c04df Fix verilog output when the width is > 1.
PR 25202
bfd	* bfd.c (VerilogDataEndianness): New variable.
	(verilog_write_record): Use VerilogDataEndianness, if set, to
	choose the endianness of the output.
	(verilog_write_section): Adjust the address by the data width.

binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
	endianness of the input file.
	(copy_main): Verifiy the value set by the --verilog-data-width
	option.
	* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
	* testsuite/binutils-all/verilog-I4.hex: New file.
2022-12-01 13:09:26 +00:00
GDB Administrator
8a1c55cdfb Automatic date update in version.in 2022-12-01 00:00:40 +00:00
Alan Modra
a7cca0b24c regen SRC-POTFILES.in 2022-11-30 18:41:40 +10:30
GDB Administrator
eb362ca1a6 Automatic date update in version.in 2022-11-30 00:00:42 +00:00
Max Filippov
d0a2cfbd31 xtensa: allow dynamic configuration
Import include/xtensa-dynconfig.h that defines XCHAL_* macros as fields
of a structure returned from the xtensa_get_config_v<x> function call.
Define that structure and fill it with default parameter values
specified in the include/xtensa-config.h.
Define reusable function xtensa_load_config that tries to load
configuration and return an address of an exported object from it.
Define functions xtensa_get_config_v{1,2} that use xtensa_load_config
to get structures xtensa_config_v{1,2}, either dynamically configured
or the default.

bfd/
	* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Append
	xtensa-dynconfig.c.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* configure.ac (xtensa_elf32_be_vec, xtensa_elf32_le_vec): Add
	xtensa-dynconfig.lo to the tb.
	* elf32-xtensa.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XSHAL_ABI, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove
	definitions.
	* xtensa-dynconfig.c: New file.
	* xtensa-isa.c (xtensa-dynconfig.h): New #include.
	(xtensa_get_modules): New function.
	(xtensa_isa_init): Call xtensa_get_modules instead of taking
	address of global xtensa_modules.

gas/
	* config/tc-xtensa.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0, XTENSA_MARCH_EARLIEST):
	Remove definitions.
	* config/tc-xtensa.h (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	* config/xtensa-relax.c (xtensa-config.h): Replace #include with
	xtensa-dynconfig.h.
	(XCHAL_HAVE_WIDE_BRANCHES): Remove definition.

include/
	* xtensa-dynconfig.h: New file.

ld/
	* emultempl/xtensaelf.em (xtensa-config.h): Replace #include
	with xtensa-dynconfig.h.
	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): Remove definitions.
2022-11-28 18:16:12 -08:00
GDB Administrator
cb44f89ce9 Automatic date update in version.in 2022-11-29 00:00:28 +00:00
Alan Modra
970a38be46 asan: pef: buffer overflow
* pef.c (bfd_pef_parse_traceback_table): Correct size moved when
	stripping leading dot.
2022-11-28 17:29:11 +10:30
Tsukasa OI
c341f4676a RISC-V: Allow merging 'H' extension
Because riscv_merge_std_ext function did not merge the 'H' extension, linked
executables lacked 'H' extension when multiple objects are merged.

This issue is found while building OpenSBI with 'H' extension (resulting
ELF files did not contain "h1p0" in "Tag_RISCV_arch" even if *all* linked
object files contained it).

This commit adds 'h' to standard_exts variable to merge 'H' extension.

bfd/ChangeLog:

	* elfnn-riscv.c (riscv_merge_std_ext): Add 'H' extension merging.
2022-11-28 02:35:43 +00:00
GDB Administrator
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GDB Administrator
5c95bab813 Automatic date update in version.in 2022-11-27 00:00:30 +00:00
GDB Administrator
66e7b0f4d9 Automatic date update in version.in 2022-11-26 00:00:32 +00:00
Christoph Müllner
ac8df5a192 riscv: Add AIA extension support (Smaia, Ssaia)
This commit adds the AIA extensions (Smaia and Ssaia) CSRs.

bfd/ChangeLog:

	* elfxx-riscv.c: Add 'smaia' and 'ssaia' to the list
	of known standard extensions.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class):
	(riscv_csr_address): Add CSR classes for Smaia/Ssaia.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add new CSRs.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (CSR_MISELECT): New CSR macro.
	(CSR_MIREG): Likewise.
	(CSR_MTOPEI): Likewise.
	(CSR_MTOPI): Likewise.
	(CSR_MVIEN): Likewise.
	(CSR_MVIP): Likewise.
	(CSR_MIDELEGH): Likewise.
	(CSR_MIEH): Likewise.
	(CSR_MVIENH): Likewise.
	(CSR_MVIPH): Likewise.
	(CSR_MIPH): Likewise.
	(CSR_SISELECT): Likewise.
	(CSR_SIREG): Likewise.
	(CSR_STOPEI): Likewise.
	(CSR_STOPI): Likewise.
	(CSR_SIEH): Likewise.
	(CSR_SIPH): Likewise.
	(CSR_HVIEN): Likewise.
	(CSR_HVICTL): Likewise.
	(CSR_HVIPRIO1): Likewise.
	(CSR_HVIPRIO2): Likewise.
	(CSR_VSISELECT): Likewise.
	(CSR_VSIREG): Likewise.
	(CSR_VSTOPEI): Likewise.
	(CSR_VSTOPI): Likewise.
	(CSR_HIDELEGH): Likewise.
	(CSR_HVIENH): Likewise.
	(CSR_HVIPH): Likewise.
	(CSR_HVIPRIO1H): Likewise.
	(CSR_HVIPRIO2H): Likewise.
	(CSR_VSIEH): Likewise.
	(CSR_VSIPH): Likewise.
	(DECLARE_CSR): Add CSRs for Smaia and Ssaia.

Changes for v3:
- Imply ssaia for smaia
- Imply zicsr for ssaia (and transitively smaia)
- Move hypervisor CSRs to Ssaia+H
- Rebase on upstream/master

Changes for v2:
- Add hypervisor and VS CSRs
- Fix whitespace issue

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-25 10:00:06 +08:00
GDB Administrator
18a119b83d Automatic date update in version.in 2022-11-25 00:00:35 +00:00
GDB Administrator
26314ac7ad Automatic date update in version.in 2022-11-24 00:00:46 +00:00
Alan Modra
e6b6fad2fe PR22509 - Null pointer dereference on coff_slurp_reloc_table
This extends the commit 4581a1c7d3 fix to more targets, which
hardens BFD a little.  I think the real underlying problem was the
bfd_canonicalize_reloc call in load_specific_debug_section which
passed a NULL for "symbols".  Fix that too.

	PR 22509
bfd/
	* aoutx.h (swap_ext_reloc_out): Gracefully handle NULL symbols.
	* i386lynx.c (swap_ext_reloc_out): Likewise.
	* pdp11.c (pdp11_aout_swap_reloc_out): Likewise.
	* coff-tic30.c (reloc_processing): Likewise.
	* coff-tic4x.c (tic4x_reloc_processing): Likewise.
	* coff-tic54x.c (tic54x_reloc_processing): Likewise.
	* coff-z80.c (reloc_processing): Likewise.
	* coff-z8k.c (reloc_processing): Likewise.
	* ecoff.c (ecoff_slurp_reloc_table): Likewise.
	* som.c (som_set_reloc_info): Likewise.
binutils/
	* objdump.c (load_specific_debug_section): Pass syms to
	bfd_canonicalize_reloc.
2022-11-23 22:38:48 +10:30
Alan Modra
d499fb8944 asan: NULL deref in filter_symbols
If tdata->symbols is NULL, make tdata->symcount zero too.  This makes
wasm_get_symtab_upper_bound return the proper result and stops
cascading errors.

	* wasm-module.c (wasm_scan_name_function_section): Clear
	tdata->symcount on error.
2022-11-23 22:38:48 +10:30
Xiao Zeng
06f0a892a5 RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant
bits are valid, but since binutils implementation, we usually get 8 bits
field for it.  That means, the high 2 bits could be other field and have
different purpose.  Therefore, we should filter the 8 bits to 6 bits before
calculate, and then only encode the valid 6 bits back.  By the way, we also
need the out-of-range check for R_RISCV_SUB6, and the overflow checks for
all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches.

Passing riscv-gnu-toolchain regressions.

bfd/ChangeLog:

        * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
	lower 6 bits as the significant bit.
        * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
2022-11-23 10:46:16 +08:00
GDB Administrator
c392c0e0ae Automatic date update in version.in 2022-11-23 00:00:43 +00:00
H.J. Lu
04ad71937f x86: Don't define _TLS_MODULE_BASE_ for ld -r
bfd/

	PR ld/29820
	* elfxx-x86.c (_bfd_x86_elf_always_size_sections): Don't define
	 _TLS_MODULE_BASE_ for ld -r.

ld/

	PR ld/29820
	* testsuite/ld-x86-64/pr29820.d: New file.
	* testsuite/ld-x86-64/pr29820.s: Likewise.
	* testsuite/ld-x86-64/x86-64.ex: Run pr29820.
2022-11-22 14:03:16 -08:00
GDB Administrator
31c1130f35 Automatic date update in version.in 2022-11-22 00:00:39 +00:00
Alan Modra
38c917d808 PR29807, SIGSEGV when linking fuzzed PE object
PR 29807
	* cofflink.c (_bfd_coff_generic_relocate_section): Skip relocs
	against symbols with a NULL section.
2022-11-22 08:18:49 +10:30
Alan Modra
e9a20a419b Re: ld: Always output local symbol for relocatable link
Remove this code dating back to commit 98790d3a95 entirely, what it
was trying to do is done elsewhere.

	PR ld/29761
	* elflink.c (elf_link_output_symstrtab): Don't handle symbols
	in SEC_EXCLUDE sections here.
2022-11-22 07:49:23 +10:30
Nick Clifton
1a7e622b82 Fix ARM and AArch64 assembler tests to work in a multi-arch environment.
PR 29764
gas	* testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m
	option passed to objdump.
	* testsuite/gas/arm/cpu-cortex-a77.d: Likewise.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to
	the -m option passed to objdump.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise.

bfd	* cpu-arm.c (scan): Accept machine names prefixed with "arm:".
	* cpu-aarch64.c (scan): Accept machine names prefixed with "aarch64:".

bin	* doc/binutils.texi (objdump): Note that the -m option supports
	the <architecture>:<machine> syntax.
2022-11-21 16:44:02 +00:00
GDB Administrator
01919ca385 Automatic date update in version.in 2022-11-21 00:00:30 +00:00
GDB Administrator
abad6c11d0 Automatic date update in version.in 2022-11-20 00:02:01 +00:00
Tsukasa OI
15253318be RISC-V: Add 'Ssstateen' extension and its CSRs
This commit adds 'Ssstateen' extension, which is a supervisor-visible view
of the 'Smstateen' extension.  It means, this extension implements sstateen*
and hstateen* CSRs of the 'Smstateen' extension.

Note that 'Smstateen' extension itself is unchanged but due to
implementation simplicity, it is implemented so that 'Smstateen' implies
'Ssstateen' (just like 'M' implies 'Zmmul').

This is based on the latest version of RISC-V Profiles
(version 0.9-draft, Frozen):
<226b7f6430>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Update implication rules.
	(riscv_supported_std_s_ext) Add 'Ssstateen' extension.

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Rename
	CSR_CLASS_SMSTATEEN_AND_H{,_32} to CSR_CLASS_SSSTATEEN_...
	Add CSR_CLASS_SSSTATEEN.
	(riscv_csr_address): Support new/renamed CSR classes.
	* testsuite/gas/riscv/csr.s: Add 'Ssstateen' extension to comment.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Reflect changes to
	error messages.
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/ssstateen-csr.s: Test for 'Ssstateen' CSRs.
	* testsuite/gas/riscv/ssstateen-csr.d: Likewise.
	* testsuite/gas/riscv/smstateen-csr-s.d: Test to make sure that
	supervisor/hypervisor part of 'Smstateen' CSRs are accessible from
	'RV32IH_Smstateen', not just from 'RV32IH_Ssstateen' that is tested
	in ssstateen-csr.d.

include/ChangeLog:

	* opcode/riscv-opc.h: Update DECLARE_CSR declarations with
	new CSR classes.
2022-11-19 02:57:05 +00:00
GDB Administrator
84bcca538d Automatic date update in version.in 2022-11-19 00:00:38 +00:00
Alan Modra
7828dfa93b go32 sanity check
* coff-stgo32 (go32exe_check_format): Sanity check stubsize against
	filesize before malloc.
2022-11-18 11:31:17 +10:30
Alan Modra
31f221d0bc Regen potfiles for sframe 2022-11-18 11:31:17 +10:30
GDB Administrator
9c93bc90d5 Automatic date update in version.in 2022-11-18 00:00:43 +00:00
H.J. Lu
25d17459e3 ld: Always call elf_backend_output_arch_local_syms
Always call elf_backend_output_arch_local_syms since only the backend
knows if elf_backend_output_arch_local_syms is needed when all symbols
are striped.  elf_backend_output_arch_local_syms is defined only for
x86, ARM and AARCH64.  On x86, elf_backend_output_arch_local_syms must
be called to handle local IFUNC symbols even if all symbols are striped.
Update ARM and AARCH64 to skip elf_backend_output_arch_local_syms when
symbols aren't needed.

bfd/

	PR ld/29797
	* elf32-arm.c (elf32_arm_output_arch_local_syms): Skip if symbols
	aren't needed.
	* elfnn-aarch64.c (elfNN_aarch64_output_arch_local_syms):
	Likewise.
	* elflink.c (bfd_elf_final_link): Always call
	elf_backend_output_arch_local_syms if available.

ld/

	PR ld/29797
	* testsuite/ld-elf/linux-x86.exp: Run PR ld/29797 test.
	* testsuite/ld-elf/pr29797.c: New file.
2022-11-17 08:13:37 -08:00
Christoph Müllner
01804a098d RISC-V: Add T-Head Int vendor extension
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-17 16:43:55 +08:00
Christoph Müllner
4a3bc79bf4 RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-11-17 16:43:49 +08:00
GDB Administrator
d5b9201744 Automatic date update in version.in 2022-11-17 00:00:37 +00:00
GDB Administrator
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Indu Bhagat
cf0e0a0ba9 bfd: linker: merge .sframe sections
The linker merges all the input .sframe sections.  When merging, the
linker verifies that all the input .sframe sections have the same
abi/arch.

The linker uses libsframe library to perform key actions on the
.sframe sections - decode, read, and create output data.  This
implies buildsystem changes to make and install libsframe before
libbfd.

The linker places the output .sframe section in a new segment of its
own: PT_GNU_SFRAME.  A new segment is not added, however, if the
generated .sframe section is empty.

When a section is discarded from the final link, the corresponding
entries in the .sframe section for those functions are also deleted.

The linker sorts the SFrame FDEs on start address by default and sets
the SFRAME_F_FDE_SORTED flag in the .sframe section.

This patch also adds support for generation of SFrame unwind
information for the .plt* sections on x86_64.  SFrame unwind info is
generated for IBT enabled PLT, lazy/non-lazy PLT.

The existing linker option --no-ld-generated-unwind-info has been
adapted to include the control of whether .sframe unwind information
will be generated for the linker generated sections like PLT.

Changes to the linker script have been made as necessary.

ChangeLog:

	* Makefile.def: Add install dependency on libsframe for libbfd.
	* Makefile.in: Regenerated.
	* bfd/Makefile.am: Add elf-sframe.c
	* bfd/Makefile.in: Regenerated.
	* bfd/bfd-in2.h (SEC_INFO_TYPE_SFRAME): Regenerated.
	* bfd/configure: Regenerate.
	* bfd/configure.ac: Add elf-sframe.lo.
	* bfd/elf-bfd.h (struct sframe_func_bfdinfo): New struct.
	(struct sframe_dec_info): Likewise.
	(struct sframe_enc_info): Likewise.
	(struct elf_link_hash_table): New member for encoded .sframe
	object.
	(struct output_elf_obj_tdata): New member.
	(elf_sframe): New access macro.
	(_bfd_elf_set_section_sframe): New declaration.
	* bfd/elf.c (get_segment_type): Handle new segment
	PT_GNU_SFRAME.
	(bfd_section_from_phdr): Likewise.
	(get_program_header_size): Likewise.
	(_bfd_elf_map_sections_to_segments): Likewise.
	* bfd/elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Add
	contents to the .sframe sections or .plt* entries.
	* bfd/elflink.c (elf_section_ignore_discarded_relocs): Handle
	SEC_INFO_TYPE_SFRAME.
	(_bfd_elf_default_action_discarded): Handle .sframe section.
	(elf_link_input_bfd): Merge .sframe section.
	(bfd_elf_final_link): Write the output .sframe section.
	(bfd_elf_discard_info): Handle discarding .sframe section.
	* bfd/elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Create
	.sframe section for .plt and .plt.sec.
	(_bfd_x86_elf_finish_dynamic_sections): Handle .sframe from
	.plt* sections.
	* bfd/elfxx-x86.h (PLT_SFRAME_FDE_START_OFFSET): New
	definition.
	(SFRAME_PLT0_MAX_NUM_FRES): Likewise.
	(SFRAME_PLTN_MAX_NUM_FRES): Likewise.
	(struct elf_x86_sframe_plt): New structure.
	(struct elf_x86_link_hash_table): New member.
	(struct elf_x86_init_table): New members for .sframe
	creation.
	* bfd/section.c: Add new definition SEC_INFO_TYPE_SFRAME.
	* binutils/readelf.c (get_segment_type): Handle new segment
	PT_GNU_SFRAME.
	* ld/ld.texi: Update documentation for
	--no-ld-generated-unwind-info.
	* ld/scripttempl/elf.sc: Support .sframe sections.
	* ld/Makefile.am (TESTSFRAMELIB): Use it.
	(check-DEJAGNU): Likewise.
	* ld/Makefile.in: Regenerated.
	* ld/configure.ac (TESTSFRAMELIB): Set to the .so or .a like TESTBFDLIB.
	* ld/configure: Regenerated.
	* bfd/elf-sframe.c: New file.

include/ChangeLog:

	* elf/common.h (PT_GNU_SFRAME): New definition.
	* elf/internal.h (struct elf_segment_map): Handle new segment
	type PT_GNU_SFRAME.

ld/testsuite/ChangeLog:

	* ld/testsuite/ld-bootstrap/bootstrap.exp: Add SFRAMELIB.
	* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test
	  sframe-simple-1.
	* ld/testsuite/ld-aarch64/sframe-bar.s: New file.
	* ld/testsuite/ld-aarch64/sframe-foo.s: Likewise.
	* ld/testsuite/ld-aarch64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-sframe/sframe-empty.d: New test.
	* ld/testsuite/ld-sframe/sframe-empty.s: New file.
	* ld/testsuite/ld-sframe/sframe.exp: New testsuite.
	* ld/testsuite/ld-x86-64/sframe-bar.s: New file.
	* ld/testsuite/ld-x86-64/sframe-foo.s: Likewise.
	* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-x86-64/sframe-plt-1.d: Likewise.
	* ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise.
	* ld/testsuite/ld-x86-64/x86-64.exp: Add new tests -
	  sframe-simple-1, sframe-plt-1.
	* ld/testsuite/lib/ld-lib.exp: Add new proc to check if
	  assembler supports SFrame section.
	* ld/testsuite/ld-sframe/discard.d: New file.
	* ld/testsuite/ld-sframe/discard.ld: Likewise.
	* ld/testsuite/ld-sframe/discard.s: Likewise.
2022-11-15 15:49:47 -08:00
GDB Administrator
8148339a74 Automatic date update in version.in 2022-11-15 00:00:31 +00:00
Dimitar Dimitrov
36f779c063 pru: bfd: Correct default to no execstack
Data and instruction memories are strictly separated, so it is not
possible to execute instructions from the stack memory on PRU.

I don't see any difference in testsuite results with or without this
change.

bfd/ChangeLog:

	* elf32-pru.c (elf_backend_default_execstack): Define as 0.

ld/ChangeLog:

	* testsuite/ld-elf/elf.exp (target_defaults_to_execstack):
	Return 0 for pru.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2022-11-14 17:42:22 +02:00
Srinath Parvathaneni
cafdb713d8 arm: Add support for Cortex-X1C CPU.
This patch adds support for Cortex-X1C CPU in Arm.

bfd/ChangeLog:

2022-11-09  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

        * cpu-arm.c (processors): Add Cortex-X1C CPU entry.

gas/ChangeLog:

2022-11-09  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

        * NEWS: Update docs.
        * config/tc-arm.c (arm_cpus): Add cortex-x1c to -mcpu.
        * doc/c-arm.texi: Update docs.
        * testsuite/gas/arm/cpu-cortex-x1c.d: New test.
2022-11-14 13:56:05 +00:00
Alan Modra
4f5c4fce88 objcopy renaming section with explicit flags
This tidies SEC_RELOC handling in bfd, in the process fixing a bug
with objcopy when renaming sections.

bfd/
	* reloc.c (_bfd_generic_set_reloc): Set/clear SEC_RELOC depending
	on reloc count.
	* elf64-sparc.c (elf64_sparc_set_reloc): Likewise.
binutils/
	* objcopy.c (copy_relocations_in_section): Remove now unnecessary
	clearing of SEC_RELOC.
	* testsuite/binutils-all/rename-section-01.d: New test.
	* testsuite/binutils-all/objcopy.exp: Run it.
gas/
	* write.c (size_seg): Remove unneccesary twiddle of SEC_RELOC.
	(write_relocs): Likewise.  Always call bfd_set_reloc.
2022-11-14 11:36:46 +10:30
GDB Administrator
f31e4e02ee Automatic date update in version.in 2022-11-14 00:00:31 +00:00
GDB Administrator
28ebf3f8d0 Automatic date update in version.in 2022-11-13 00:00:30 +00:00
GDB Administrator
c9ea6bd322 Automatic date update in version.in 2022-11-12 00:00:21 +00:00
Alan Modra
f7502dfe3f PR28834, PR26946 sanity checking section size
This patch provides a new function to sanity check section sizes.
It's mostly extracted from what we had in bfd_get_full_section_contents
but also handles compressed debug sections.
Improvements are:
- section file offset is taken into account,
- added checks that a compressed section can be read from file.

The function is then used when handling multiple .debug_* sections
that need to be read into a single buffer, to sanity check sizes
before allocating the buffer.

	PR 26946, PR 28834
	* Makefile.am (LIBBFD_H_FILES): Add section.c.
	* compress.c (bfd_get_full_section_contents): Move section size
	sanity checks..
	* section.c (_bfd_section_size_insane): ..to here.  New function.
	* dwarf2.c (read_section): Use _bfd_section_size_insane.
	(_bfd_dwarf2_slurp_debug_info): Likewise.
	* Makefile.in: Regenerate.
	* libbfd.h: Regenerate.
2022-11-11 18:05:36 +10:30
Alan Modra
d0e5049d8f Sanity check SHT_MIPS_OPTIONS size
* elfxx-mips.c (_bfd_mips_elf_section_from_shdr): Use
	bfd_malloc_and_get_section to read contents of .MIPS.options.
2022-11-11 18:05:36 +10:30
GDB Administrator
a686428a8b Automatic date update in version.in 2022-11-11 00:00:43 +00:00
Alan Modra
ac71c620fd mach-o reloc size overflow
* mach-o.c (bfd_mach_o_canonicalize_reloc): Set bfd_error on
	multiply overflow.
2022-11-10 20:29:03 +10:30
Alan Modra
a3eb71adfe Sanity check reloc count in get_reloc_upper_bound
The idea here is the stop tools from allocating up to 32G per section
for the arelent pointer array, only to find a little later that the
section reloc count was fuzzed.  This usually doesn't hurt much (on
systems that allow malloc overcommit) except when compiled with asan.

We already do this for ELF targets, and while fixing the logic
recently I decided other targets ought to do the same.

	* elf64-sparc.c (elf64_sparc_get_reloc_upper_bound): Sanity check
	section reloc count against file size.
	* mach-o.c (bfd_mach_o_get_reloc_upper_bound): Likewise.
	* aoutx.h (get_reloc_upper_bound): Likewise, and don't duplicate
	check done in bfd_get_reloc_upper_bound.
	* pdp11.c (get_reloc_upper_bound): Likewise.
	* coffgen.c (coff_get_reloc_upper_bound): Likewise.
2022-11-10 20:29:03 +10:30
GDB Administrator
8a484e98ae Automatic date update in version.in 2022-11-10 00:00:31 +00:00
H.J. Lu
1db13039a7 ld: Always output local symbol for relocatable link
PR ld/29761
	* elflink.c (elf_link_output_symstrtab): Don't skip local symbol
	in SEC_EXCLUDE section for relocatable link.
2022-11-08 18:39:28 -08:00