* config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
(elf_frob_file_after_relocs): ... here. New function.
* config/obj-elf.h (obj_from_file_after_relocs): New macro.
* write.c (write_object_file): Call *frob_after_relocs after the
call to write_relocs.
* config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
* config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
symbol, as this messes up linking. Instead, expand the recursive call
inline and change up the appropriate bits to get the 0x8000 offset
in the reloc addend.
(obj_elf_section): Add the section symbol to the symbol table.
* config/obj-elf.h (obj_begin): Define.
(elf_begin): Declare.
* as.c (perform_an_assembly_pass): Call obj_begin if it is
defined.
* obj-evax.h: move openvms definitions from here to tc-alpha.c.
* tc-alpha.c: add support for vms_case_hack like in vax/vms.
(load_expression): track clobbering of base reg before jmp/jsr.
(s_alpha_file): pass case_hack flags and source filename via
symbol table to bfd.
* tc-alpha.h (TC_CONS_FIX_NEW): define
mips_cpu is 5000, set interlocks and cop_interlocks.
(mips_ip): Give a better error message if the ISA level is wrong.
(md_parse_option): Recognize -mcpu=[v][r]5000.
* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
opcode doesn't want a register, then we don't have a match.
(md_assemble): Get size of the instruction from the opcode table.
So we choose the right opcode and so that we get the sizes right.
Add support for openVMS/Alpha.
* as.h (PRINTF_LIKE): Don't define if VMS, for now.
* config/obj-evax.c: New file.
* config/obj-evax.h: New file.
* config/tc-alpha.c: Add support for EVAX format if OBJ_EVAX is
defined.
* config/tc-alpha.h: Add support for EVAX format if OBJ_EVAX is
defined. Add case for bfd_target_evax_flavour.
* config/vms-a-conf.h: New file.
* conf-a-gas.com: New file.
* configure.in: Add target alpha-*-*vms*.
* configure: Rebuild.
* makefile.vms: New file.
* read.c (s_lcomm): Align bss_seg on 8 byte boundary if OBJ_EVAX.
Don't call ffs on openVMS/Alpha.
#ifndef OBJ_ELF lines. From Eric Valette <valette@crf.canon.fr>.
(tc_gen_reloc): If out of memory call as_fatal rather than
assert. If no howto found, call as_bad_where rather than
as_fatal. Change the error message slightly. Set howto to a
non-NULL value in order to keep going.
* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
(cons_fix_new_hppa): Don't coke on e_esel.
(tc_gen_reloc, SOM version): Handle R_COMP2 when used
to help generate exception handling tables.
(md_apply_fix): Don't try to apply fixups with an e_esel
selector.
(hppa_fix_adjustable): Fixups with e_esel selectors
are not adjustable.
Another stab at EH on the PA.
