This fixes a wart I've known about for years, but haven't done
anything about because BFD treats relocation sections as an adjunct to
the section they relocate. SHF_GROUP on the section thus implicitly
applies to its relocation section(s), but it is an error that the
reloc sections aren't part of the group.
Like many patches to gas, this wasn't as straightforward as it could
be due to a number of backends, i386, cr16 and others, removing relocs
in tc_get_reloc rather than marking them as "done" earlier in
md_apply_reloc. So it isn't possible for the group support to
reliably detect the presence of relocs by looking at fixups earlier
than write_relocs. However the group support needs to create
signature symbols, and that must be done before the symbol table is
frozen, before write_relocs. So split off the group sizing from
elf_adjust_symtab and put it in elf_frob_file_after_relocs.
bfd/
PR 21167
* elf.c (_bfd_elf_setup_sections): Don't trim reloc sections from
groups.
(_bfd_elf_init_reloc_shdr): Pass sec_hdr, use it to copy SHF_GROUP
flag from section.
(elf_fake_sections): Adjust calls. Exit immediately on failure.
(bfd_elf_set_group_contents): Add associated reloc section indices
to group contents
gas/
PR 21167
* config/obj-elf.c (struct group_list): Delete elt_count.
(groups): New static.
(build_group_lists): Don't count elements.
(elf_adjust_symtab): Use groups rather than auto list. Set up
pointer from group member to SHT_GROUP section. Don't size
SHT_GROUP section or clean up here..
(elf_frob_file_after_relocs): ..do so here instead.
* testsuite/gas/arc/jli-1.d,
* testsuite/gas/elf/groupautob.d,
* testsuite/gas/mips/compact-eh-eb-2.d,
* testsuite/gas/mips/compact-eh-eb-5.d,
* testsuite/gas/mips/compact-eh-el-2.d,
* testsuite/gas/mips/compact-eh-el-5.d: Adjust.
ld/
PR 21167
* testsuite/ld-elf/group9b.d: Adjust for relocs included in group.
opcodes/
* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
VLE multimple load/store instructions. Old e_ldm* variants are
kept as aliases.
Add missing e_lmvmcsrrw and e_stmvmcsrrw.
gas/
* testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
support for the VLE multiple load/store instructions.
* testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
driver.
* testsuite/gas/ppc/ppc.exp: Run it.
PR 22179
opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
names for the fmv.x.s and fmv.s.x instructions respectively.
gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
renamed fmv.x.s and fmv.s.x instructions.
* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
Fix commit e407c74b5b ("Support for MIPS R5900 (Sony Playstation 2)"),
<https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and add the
handling of E_MIPS_MACH_5900, correctly showing `5900' among `Flags:' in
the output of `-h' rather than `unknown CPU'.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_5900>: New case.
gas/
* testsuite/gas/mips/elf_mach_5900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
If a .stabs directive was used before another .set directive in a MIPS
source file, s_mips_stab would call mips_mark_labels without having
initialized the mips_opts structure yet. Fix this by calling
file_mips_check_options which will initialize mips_opts if necessary.
gas/
PR gas/21762
* config/tc-mips.c (s_mips_stab): Insert call to
file_mips_check_options.
* testsuite/gas/mips/micromips@stabs-symbol-type.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/mips16@stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.s: New test source.
PowerPC64 .cfi directives use DW_EH_PE_sdata4 encoding for .eh_frame,
so there is no real reason why .eh_frame should be 8 byte aligned.
gas/
* config/tc-ppc.h (EH_FRAME_ALIGNMENT): Define.
ld/
* testsuite/ld-powerpc/tlsopt5.wf: Update for reduced alignment.
"sec" gets set to NULL on errors in the offset expression. This patch
disables part of the reloc expression processing that needs "sec"
valid. I didn't disable the entire reloc expression handling so that
errors in the reloc expression are reported even when the offset
expression has an error.
PR 22127
* write.c (resolve_reloc_expr_symbols): Don't segfault when
sec has been set to NULL.
Since the NOTRACK prefix is no longer required to be the last prefix
before the REX prefix, restriction on the NOTRACK prefix position is
removed from assembler as well as disassembler. Assembler encodes the
NOTRACK prefix the same way as the DS segment register, which places
it before other prefixes. Disassembler displays prefixes in the order
they appear.
gas/
* config/tc-i386.c (NOTRACK_PREFIX): Removed.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(parse_insn): Remove restriction on NOTRACK prefix position.
* testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix
before other prefixes.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK
prefix before other prefixes.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
* testsuite/gas/i386/notrack-intel.d: Updated.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
opcodes/
* i386-dis.c (last_active_prefix): Removed.
(ckprefix): Don't set last_active_prefix.
(NOTRACK_Fixup): Don't check last_active_prefix.
When linking the following code
.global _prog_start
_prog_start:
mv x1, x1
mv x2, x2
.align 2
rvc_boundry:
.option norvc
.align 3
mv x3, x3
we currently emit an invalid two-byte 0 instruction. The actual output
code looks like
0000000080000000 <_prog_start>:
80000000: 8086 mv ra,ra
80000002: 810a mv sp,sp
0000000080000004 <rvc_boundry>:
80000004: 0000 unimp
80000006: 0001 nop
80000008: 00018193 mv gp,gp
This ends up manifesting due to the two-byte compressed NOP that's
pessimisticly emitted by the ".align 2", which results in "rvc_boundry"
being 2-byte aligned. frag_align_code() then goes and outputs a 2-byte
NOP (which is invalid in no-RVC mode) to align the code back to a 4-byte
boundry, which can't be relaxed away by the linker as it's not part of
the R_RISCV_RELAX relocation.
The fix is to just always emit the worst case possible alignment into
the output as a single R_RISCV_RELAX, which the linker will then fix up.
With this patch I get the expected code generation
0000000080000000 <_prog_start>:
80000000: 8086 mv ra,ra
80000002: 810a mv sp,sp
0000000080000004 <rvc_boundry>:
80000004: 00000013 nop
80000008: 00018193 mv gp,gp
gas/ChangeLog
2017-09-07 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_frag_align_code): Emit the entire
alignment sequence inside R_RISCV_ALIGN.
Fix a bug in commit a6ebf6169a ("MIPS: Convert cross-mode BAL to
JALX") and in BFD linker relaxation correct the microMIPS interpretation
of the branch offset, which is supposed to be shifted by 1 bit, rather
than 2 as in the regular MIPS case.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS
branch offset interpretation.
gas/
* testsuite/gas/mips/branch-addend-micromips.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n32.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n64.d: New test.
* testsuite/gas/mips/branch-addend-micromips.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Fix a bug in commit 8b10b0b3e1 ("MIPS: Add options to control branch
ISA checks") and with the `-mignore-branch-isa' command-line option also
lift a GAS check for invalid MIPS16 branches between ISA modes, which is
made separately from regular MIPS and microMIPS checks.
gas/
* config/tc-mips.c (md_convert_frag): Respect
`mips_ignore_branch_isa'.
* testsuite/gas/mips/branch-local-5.d: New test.
* testsuite/gas/mips/branch-local-n32-5.d: New test.
* testsuite/gas/mips/branch-local-n64-5.d: New test.
* testsuite/gas/mips/branch-local-6.d: New test.
* testsuite/gas/mips/branch-local-n32-6.d: New test.
* testsuite/gas/mips/branch-local-n64-6.d: New test.
* testsuite/gas/mips/branch-local-7.d: New test.
* testsuite/gas/mips/branch-local-n32-7.d: New test.
* testsuite/gas/mips/branch-local-n64-7.d: New test.
* testsuite/gas/mips/branch-local-ignore-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-6.d: New test.
* testsuite/gas/mips/branch-local-5.l: New stderr output.
* testsuite/gas/mips/branch-local-6.l: New stderr output.
* testsuite/gas/mips/branch-local-5.s: New test source.
* testsuite/gas/mips/branch-local-6.s: New test source.
* testsuite/gas/mips/branch-local-7.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-sparc.c (tc_gen_reloc): Convert BFD_RELOC_8/16/32/64
into the corresponding BFD_RELOC_8/16/32/64_PCREL relocation
when requested.
* config/tc-sparc.h (DIFF_EXPR_OK): Define to enable PC-relative
diff relocations.
(TC_FORCE_RELOCATION_SUB_LOCAL): Define to ensure only supported
relocations are made PC-relative.
(CFI_DIFF_EXPR_OK): Define to 0 to force BFD_RELOC_32_PCREL to
be used directly, since otherwise BFD_RELOC_SPARC_UA32 will be
used for .eh_frame which cannot in general be converted to a
BFD_RELOC_32_PCREL due to alignment requirements.
We got a report from the linux-arm-kernel folks about getting spurious
warnings when building the kernel with binutils 2.29. See
https://www.spinics.net/lists/arm-kernel/msg599929.html
which boils down to this testcase.
$> cat /tmp/tst.s
lr .req x30
/tmp/tst.s: Assembler messages:
/tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr'
Instead let's treat this as a proper alias at startup time thus
avoiding the problem and treating these as proper aliases
rather than new registers. This means that attempts to redefine
the alias with the same "name" will provoke no warning and attempts
to redefine the alias to something else will provoke the above mentioned
warning.
Tested make check-gas and no regressions.
Ok to apply to trunk (and backport to 2.29 branch)?
Regards
Ramana
We can't create alias of common symbol. Local alias of common symbol has
been disallowed. But global alias of common symbol is disallowed when the
common symbol is seen first and silently dropped otherwise. This patch
disallows alias of common symbol in all cases.
gas/
PR gas/21667
* read.c (pseudo_set): Update error message for alias of common
symbol.
* write.c (write_object_file): Disallow both local and global
aliases of common symbol.
* testsuite/gas/elf/common5a.d: New file.
* testsuite/gas/elf/common5a.l: Likewise.
* testsuite/gas/elf/common5a.s: Likewise.
* testsuite/gas/elf/common5b.d: Likewise.
* testsuite/gas/elf/common5b.l: Likewise.
* testsuite/gas/elf/common5b.s: Likewise.
* testsuite/gas/elf/common5c.d: Likewise.
* testsuite/gas/elf/common5c.s: Likewise.
* testsuite/gas/elf/common5d.d: Likewise.
* testsuite/gas/elf/common5d.s: Likewise.
* testsuite/gas/elf/elf.exp: Run common5a, common5b, common5c
and common5d.
PR gas/21939
* config/obj-macho.c (obj_mach_o_set_indirect_symbols): Increase
size of indirect_syms array so that it is large enough to hold
every symbol if necessary.
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
PR 21809
* config/tc-aarch64.c (aarch64_init_frag): Do not set a mapping
state for frags in debug sections.
* config/tc-arm.c (arm_init_frag): Likewise.
Trying to build (for mmix-knuth-mmixware but I don't think that
matters) yields the following (repeatable on e.g. CompileFarm gcc20
sporting gcc-4.7.2 as default):
gcc -DHAVE_CONFIG_H -I. -I/home/hp/binutils/src/gas -I. -I/home/hp/binutils/src/gas -I../bfd -I/home/hp/binutils/src/gas/config -I/home/hp/binutils/src/gas/../include -I/home/hp/binutils/src/gas/.. -I/home/hp/binutils/src/gas/../bfd -DLOCALEDIR="\"/usr/local/share/locale\"" -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -Wwrite-strings -I/home/hp/binutils/src/gas/../zlib -g -O2 -MT dwarf2dbg.o -MD -MP -MF .deps/dwarf2dbg.Tpo -c -o dwarf2dbg.o /home/hp/binutils/src/gas/dwarf2dbg.c
cc1: warnings being treated as errors
/home/hp/binutils/src/gas/dwarf2dbg.c: In function 'dwarf2dbg_final_check':
/home/hp/binutils/src/gas/dwarf2dbg.c:2246: error: declaration of 'expr' shadows a global declaration
/home/hp/binutils/src/gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [dwarf2dbg.o] Error 1
IIRC this is a false namespace clash and the warning is not observable
with a new-enough gcc. Committed as obvious.
brgds, H-P
PS. Idea: -Wcompiler; warn about constructs problematic with e.g. old gcc. 1/2 ;-)
With IBM z14 officially announced I can add z14 as CPU name.
No regressions with that patch on s390x.
gas/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.
The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
bfd * elf32-xtensa.c (elf_xtensa_get_plt_section): Increase length of
plt_name buffer.
(elf_xtensa_get_gotplt_section): Increase length of got_name
buffer.
* mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Add a
default return of FALSE.
* mach-o-i386.c (bfd_mach_o_i386_canonicalize_one_reloc): Add a
default return of FALSE.
binutils * dwarf.c (dwarf_vmatoa_1): Do not pass a NULL string pointer to
sprintf.
* srconv.c (walk_tree_type): Initialise the spare field of the
IT_dty structure.
gas * config/tc-pru.c (md_assemble): Add continue statement after
handling 'E' operand character.
* config/tc-v850.c (md_assemble): Initialise the 'insn' variable.
This patch adds support for the ARM Cortex-A55 and
Cortex-A75 processors.
The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A
architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions,
including support for the 16-bit floating point extensions.
The 16-bit floating-point extensions are optional, and we haven't defined
an option mapping straight to them thus far, so this patch first needs to
add one of those in include/opcode/arm.h, then we can simply add the CPU names
as usual in config/tc-arm.c .
Tested on arm-none-eabi.
2017-07-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75.
* doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Tristan - are you ok with the backports ?
Applied to trunk.
regards Ramana
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.
Use a switch on the relaxation type rather than a chain of conditionals
in microMIPS fixup creation, improving source code structure and aiding
the compiler with code generation.
gas/
* config/tc-mips.c (md_convert_frag): Use a switch on the
microMIPS relaxation type rather than a chain of conditionals.
