* ns32k-dis.c: Deleted all code in "#ifdef GDB".
(invalid_float): Enabled general version, doesn't require running
on ns32k host.
Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au)
* opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped
from distribution. A ns32k-dis.c from a previous distribution has
been brought up to date and supports the new interface.
* disaaemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
* configure.in: add bfd_ns32k_arch target support.
* Makefile.in: add ns32k-dis.o to ALL_MACHINES.
Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o.
removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag
instead. Add new operand SISIGNOPT.
(powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT.
Based on patch from David Edelsohn (edelsohn@npac.syr.edu).
* ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather
than signedp field.
(print_insn_m68k): If an instruction uses place 'i', it uses at
least four fixed bytes.
(print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For
extended float, convert to double using floatformat_to_double, not
ieee_extended_to_double, and fetch the data before converting it.
Floating point format for 'H' operand is backwards from normal
case (0 == double, 1 == single). For '4', '6', '7', '9', and '8'
operands (fmpyadd and fmpysub), handle bizarre register translation
correctly for single precision format.
single number giving a bitmask for the MB and ME fields of an M
form instruction. Change NB to accept 32, and turn it into 0;
also turn 0 into 32 when disassembling. Seperated SH from NB.
(insert_mbe, extract_mbe): New functions.
(insert_nb, extract_nb): New functions.
(SC_MASK): Mask out SA and LK bits.
(powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT,
RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark
"bctr" and "bctrl" as accepted by POWER. Change "rlwimi",
"rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.",
"rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to
use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions.
(powerpc_macros): Define table of macro definitions.
(powerpc_num_macros): Define.
opcodes for POWER (RS/6000).
* ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler.
* Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o.
(CFILES): Add ppc-dis.c.
(ppc-dis.o, ppc-opc.o): New targets.
* configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch.
than s,t. Change div macro to be d,v,t rather than d,s,t.
Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu,
rem and remu which generates only the corresponding div
instruction. This is for compatibility with the MIPS assembler,
which only generates the simple machine instruction when an
explicit destination of $0 is used.
* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
Change d,s,t form to d,v,t. Likewise for divu, ddiv and ddivu.
This is for compatibility with the MIPS assembler, which only
generates the simple machine instruction when an explicit
destination of $0 is used.
