This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BF instruction.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.
This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
1. Use single entry for vcvtne2ps2bf16 and vdpbf16ps with Disp8ShiftVL.
2. Use 5 entries, instead of 8, for vcvtneps2bf16.
* i386-opc.tbl: Consolidate AVX512 BF16 entries.
* i386-init.h: Regenerated.
* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
op_separator to control printing of spaces, comma and parens
rather than need_comma, need_paren and spaces vars.
This patch fixes a problem with disassembly of branch instructions
for processors complying with PowerPC ISA versions prior to version
2.0, ie. those that use "y" bit branch taken hints. Many of the
extended bcctr and bclr mnemonics that should have disassembled with a
"-" suffix, ie. not taken, did not display the "-" due to the ordering
in powerpc_opcodes. I believe it's been that way from the original
85dcf36d72 commit of ppc-opc.c.
I've also added a BH field (optional) to a few opcodes. This gives
better disassembly in raw mode, showing the branch taken hint in the
mnemonic as is done for bc. It would be reasonable to add a BH
field to all bcctr, bclr, and bctar extended mnemonics but that runs
into a small difficulty: Currently we print all or none of the
optional operands. That means for example that "bgectr cr2" would
display as "bgectr cr2,0" if a BH field is added to bgectr.
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
to favour printing of "-" branch hint when using the "y" bit.
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
When an instruction has operands, the PowerPC disassembler prints
spaces after the opcode so as to line up operands. If the operands
are all optional and all default value, then no operands are printed,
leaving trailing spaces. This patch fixes that.
opcodes/
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
opcode until first operand is output.
gas/
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
ld/
* testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
* testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Similar to the AArch64 patches the Arm disassembler has the same issues with
out of order sections but also a few short comings.
For one thing there are multiple code blocks to determine mapping symbols, and
they all work slightly different, and neither fully correct. The first thing
this patch does is centralise the mapping symbols search into one function
mapping_symbol_for_insn. This function is then updated to perform a search in
a similar way as AArch64.
Their used to be a value has_mapping_symbols which was used to determine the
default disassembly for objects that have no mapping symbols. The problem with
the approach was that it was determining this value in the same loop that needed
it, which is why this field could take on the states -1, 0, 1 where -1 means
"don't know". However this means that until you actually find a mapping symbol
or reach the end of the disassembly glob, you don't know if you did the right
action or not, and if you didn't you can't correct it anymore.
This is why the two jump-reloc-veneers-* testcases end up disassembling some
insn as data when they shouldn't.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for Arm [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix
this we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section
than we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2018q4-documentation#aaelf32-table4-7
binutils/ChangeLog:
* testsuite/binutils-all/arm/in-order-all.d: New test.
* testsuite/binutils-all/arm/in-order.d: New test.
* testsuite/binutils-all/arm/objdump.exp: Support .d tests.
* testsuite/binutils-all/arm/out-of-order-all.d: New test.
* testsuite/binutils-all/arm/out-of-order.T: New test.
* testsuite/binutils-all/arm/out-of-order.d: New test.
* testsuite/binutils-all/arm/out-of-order.s: New test.
ld/ChangeLog:
* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Update disassembly.
* testsuite/ld-arm/jump-reloc-veneers-long.d: Update disassembly.
opcodes/ChangeLog:
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
(mapping_symbol_for_insn): Implement new algorithm.
(print_insn): Remove duplicate code.
The documentation for -D says that on Arm platforms -D should disassemble
data as instructions.
"If the target is an ARM architecture this switch also has the effect of
forcing the disassembler to decode pieces of data found in code sections
as if they were instructions. "
This makes it do as it says on the tincan so it's more consistent with
aarch32. The usecase here is for baremetal developers who have created
their instructions using .word directives instead if .insn.
Though for Linux users I do find this behavior somewhat non-optimal.
Perhaps there should be a new flag that just disassembles the values
following the actual mapping symbol?
binutils/ChangeLog:
* testsuite/binutils-all/aarch64/in-order-all.d: New test.
* testsuite/binutils-all/aarch64/out-of-order-all.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.d:
opcodes/ChangeLog:
* aarch64-dis.c (print_insn_aarch64):
Implement override.
My previous patch for AArch64 was not enough to catch all the cases where
disassembling an out-of-order section could go wrong. It had missed the case
DATA sections could be incorrectly disassembled as TEXT.
Out of order here refers to an object file where sections are not listed in a
monotonic increasing VMA order.
The ELF ABI for AArch64 [1] specifies the following for mapping symbols:
1) A text section must always have a corresponding mapping symbol at it's
start.
2) Data sections do not require any mapping symbols.
3) The range of a mapping symbol extends from the address it starts on up to
the next mapping symbol (exclusive) or section end (inclusive).
However there is no defined order between a symbol and it's corresponding
mapping symbol in the symbol table. This means that while in general we look
up for a corresponding mapping symbol, we have to make at least one check of
the symbol below the address being disassembled.
When disassembling different PCs within the same section, the search for mapping
symbol can be cached somewhat. We know that the mapping symbol corresponding to
the current PC is either the previous one used, or one at the same address as
the current PC.
However this optimization and mapping symbol search must stop as soon as we
reach the end or start of the section. Furthermore if we're only disassembling
a part of a section, the search is a allowed to search further than the current
chunk, but is not allowed to search past it (The mapping symbol if there, must
be at the same address, so in practice we usually stop at PC+4).
lastly, since only data sections don't require a mapping symbol the default
mapping type should be DATA and not INSN as previously defined, however if the
binary has had all its symbols stripped than this isn't very useful. To fix this
we determine the default based on the section flags. This will allow the
disassembler to be more useful on stripped binaries. If there is no section than
we assume you to be disassembling INSN.
[1] https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4#aaelf64-section4-5-4
binutils/ChangeLog:
* testsuite/binutils-all/aarch64/in-order.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.d: Disassemble data as
well.
opcodes/ChangeLog:
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
order.
The AArch64 disassembler has an optimization that it uses to reduce the amount
it has to search for mapping symbols during disassembly. This optimization
assumes that sections are listed in the section header in monotonic increasing
VMAs. However this is not a requirement for the ELF specification.
Because of this when such "out of order" sections occur the disassembler would
pick the wrong mapping symbol to disassemble the section with.
This fixes it by explicitly passing along the stop offset for the current
disassembly glob and when this changes compared to the previous one we've seen
the optimization won't be performed. In effect this restarts the search from
a well defined starting point. Usually the symbol's address.
The existing stop_vma can't be used for this as it is allowed to be unset and
setting this unconditionally would change the semantics of this field.
binutils/ChangeLog:
* objdump.c (disassemble_bytes): Pass stop_offset.
* testsuite/binutils-all/aarch64/out-of-order.T: New test.
* testsuite/binutils-all/aarch64/out-of-order.d: New test.
* testsuite/binutils-all/aarch64/out-of-order.s: New test.
include/ChangeLog:
* dis-asm.h (struct disassemble_info): Add stop_offset.
opcodes/ChangeLog:
* aarch64-dis.c (last_stop_offset): New.
(print_insn_aarch64): Use stop_offset.
The software trap instruction HLT that was introduced in Armv8-a is used
as the semihosting trap instruction in AArch64. In order to allow systems
configured to run AArch64 code to also run AArch32 with semihosting it was
decided that AArch32 should also use HLT in the case of the "mixed mode"
environment. This requires that HLT also be backported to all earlier
architectures. The instruction is in the undefined encoding space earlier
architectures but must trigger a semihosting trap [3].
The Arm Architectural Reference Manual [1] doesn't explicitly mention this
however this is an explicit requirement in the Semihosting-v2 protocol [2].
[1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
[3] 19a6e31c9d
gas/ChangeLog:
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
opcodes/ChangeLog:
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
The AArch64 instruction set has cut-outs inside instructions encodings for
when a given encoding that would normally fall within the encoding space of
an instruction is instead undefined.
This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case
where sz:L == 11.
gas/ChangeLog:
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
opcodes/ChangeLog:
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
opcodes/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch13 as cpu string.
* s390-opc.c: Add new instruction formats and instruction opcode
masks.
* s390-opc.txt: Add new arch13 instructions.
include/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH13.
gas/ChangeLog:
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
* doc/c-s390.texi: Document arch13 march option.
* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
* testsuite/gas/s390/zarch-arch13.d: New test.
* testsuite/gas/s390/zarch-arch13.s: New test.
* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
also for z13.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.
STGZM Xt, [<Xn|SP>]
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
*** opcodes/ChangeLog ***
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Check for null before dereferencing an operand pointer. Normally
this situation should never arise, but could happen if a "partial"
instruction is encountered at the end of a file or section.
opcodes/
* s12z-dis.c (print_insn_s12z): Do not dereference an
operand if it is null.
gas/
* testsuite/gas/s12z/jsr.s: New case.
* testsuite/gas/s12z/jsr.d: New case.
opcodes/
* s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is
zero.
This change adds an abstraction layer between the decoding of machine
operations and their disassembled textual representation. This allows
the decoding routines to be re-used for other purposes (at the expense)
of slightly slower running time.
ChangeLog: opcodes/
* s12z-opc.c: New file.
* s12z-opc.h: New file.
* s12z-dis.c: Removed all code not directly related to display
of instructions. Used the interface provided by the new files
instead.
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
* Makefile.in: regenerate.
* configure.ac (bfd_s12z_arch): Correct the dependencies.
* configure: regenerate.
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if
available. Apparently MacOS Mojave defines int64_t as long long even
though long is also 64 bits, which confuses the logic selecting
PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on
Mojave.
PR 24028
include/
* opcode/ppc.h (PPC_INT_FMT): Delete.
opcodes/
* ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with
PRId64/PRIx64.
PR gas/23956
gas/
* config/tc-riscv.c (validate_riscv_insn) <'1'>: New case.
(percent_op_null): New.
(riscv_ip) <'j'>: Set imm_reloc before p.
<'1'>: New case.
<'0'>: Use percent_op_null and don't set imm_reloc.
<alu_op>: Handle *args == '1'.
* testsuite/gas/riscv/tprel-add.d: New.
* testsuite/gas/riscv/tprel-add.l: New.
* testsuite/gas/riscv/tprel-add.s: New.
opcodes/
* riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
When configuring with '--enbale-cgen-maint' the default for both the
opcodes/ and sim/ directories is to assume that the cgen source is
within the binutils-gdb source tree as binutils-gdb/cgen/.
In the old cvs days, this worked well, as cgen was just another
sub-module of the single cvs repository and could easily be checked
out within the binutils-gdb directory, and managed by cvs in the
normal way.
Now that binutils-gdb is in git, while cgen is still in cvs, placing
the cgen respository within the binutils-gdb tree is more troublesome,
and it would be nice if the two tools could be kept separate.
Luckily there is already some initial code in the configure.ac files
for both opcodes/ and sim/ to support having cgen be located outside
of the binutils-gdb tree, however, this was speculative code written
imagining a future where cgen would be built and installed to some
location.
Right now there is no install support for cgen, and so the configure
code in opcodes/ and sim/ doesn't really do anything useful. In this
commit I repurpose this code to allow binutils-gdb to be configured so
that it can make use of a cgen source directory that is outside of the
binutils-gdb tree.
With this commit applied it is now possible to configure and build
binutils-gdb like this:
/path/to/binutils-gdb/src/configure --enable-cgen-maint=/path/to/cgen/src/cgen/
make all-opcodes
make -C opcodes run-cgen-all
Just in case anyone is still using cgen inside the binutils-gdb tree,
I have left the default behaviour of '--enable-cgen-maint' (with no
parameter) unchanged, that is it looks for the cgen directory as
'binutils-gdb/cgen/'.
opcodes/ChangeLog:
* configure.ac (enable-cgen-maint): Support passing path to cgen
source tree.
* configure: Regenerate.
sim/ChangeLog:
* common/acinclude.m4 (enable-cgen-maint): Support passing path to
cgen source tree.
* cris/configure: Regenerate.
* frv/configure: Regenerate.
* iq2000/configure: Regenerate.
* lm32/configure: Regenerate.
* m32r/configure: Regenerate.
* or1k/configure: Regenerate.
* sh64/configure: Regenerate.
The RISC-V assembler generates fake labels with the name '.L0 ' as
part of the debug information (see
gas/config/tc-riscv.h:FAKE_LABEL_NAME).
The problem is that currently, when disassembling an object file, the
output looks like this (this is an example from the GDB testsuite, but
is pretty representative of anything with debug information):
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
0000000000000026 <.L0 >:
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
0000000000000034 <.L0 >:
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L0 >
0000000000000046 <.L0 >:
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
0000000000000050 <.L0 >:
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <.L0 +0xe>
0000000000000066 <.L0 >:
66: 4785 li a5,1
68: a869 j 102 <.L0 >
000000000000006a <.L0 >:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L0 +0x8>
The frequent repeated '.L0 ' labels are pointless, as they are
non-unique there's no way to match a use of '.L0 ' to its appearence
in the output, so we'd be better off just not printing it at all.
That's what this patch does by defining a 'symbol_is_valid' method for
RISC-V. With this commit, the same disassembly now looks like this:
000000000000001e <main>:
1e: 7179 addi sp,sp,-48
20: f406 sd ra,40(sp)
22: f022 sd s0,32(sp)
24: 1800 addi s0,sp,48
26: 87aa mv a5,a0
28: feb43023 sd a1,-32(s0)
2c: fcc43c23 sd a2,-40(s0)
30: fef42623 sw a5,-20(s0)
34: fec42783 lw a5,-20(s0)
38: 0007871b sext.w a4,a5
3c: 678d lui a5,0x3
3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d>
42: 02f71463 bne a4,a5,6a <.L4>
46: 000007b7 lui a5,0x0
4a: 0007b783 ld a5,0(a5) # 0 <need_malloc>
4e: 6f9c ld a5,24(a5)
50: 86be mv a3,a5
52: 466d li a2,27
54: 4585 li a1,1
56: 000007b7 lui a5,0x0
5a: 00078513 mv a0,a5
5e: 00000097 auipc ra,0x0
62: 000080e7 jalr ra # 5e <main+0x40>
66: 4785 li a5,1
68: a869 j 102 <.L5>
000000000000006a <.L4>:
6a: 000007b7 lui a5,0x0
6e: 00078513 mv a0,a5
72: 00000097 auipc ra,0x0
76: 000080e7 jalr ra # 72 <.L4+0x8>
In order to share the fake label between the assembler and the
libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME
and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have
just moved FAKE_LABEL_NAME to the include file, however, I thnk this
would be confusing, someone working on the assembler would likely not
expect to find FAKE_LABEL_NAME defined outside of the assembler source
tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the
assembler standard FAKE_LABEL_ defines in the assembler source, but
still share the RISCV_FAKE_LABEL_* with libopcodes.
gas/ChangeLog:
* config/tc-riscv.h (FAKE_LABEL_NAME): Define as
RISCV_FAKE_LABEL_NAME.
(FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR.
include/ChangeLog:
* dis-asm.h (riscv_symbol_is_valid): Declare.
* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
(RISCV_FAKE_LABEL_CHAR): Define.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Add RISC-V
initialisation.
* riscv-dis.c (riscv_symbol_is_valid): New function.
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.
2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
opcodes:
PR 23193
PR 19721
* aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
encoding as MOV if the shift operation is a left shift of zero.
gas:
PR 23193
PR 19721
* testsuite/gas/aarch64/pr19721.s: Add new test cases.
* testsuite/gas/aarch64/pr19721.d: Correct existing test
cases and add new ones.
