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82 Commits

Author SHA1 Message Date
H.J. Lu
42164a7195 Implement Intel Transactional Synchronization Extensions 
gas/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (HLE_PREFIX): New.
	(check_hle): Likewise.
	(_i386_insn): Add have_hle.
	(cpu_arch): Add .hle and .rtm.
	(md_assemble): Call check_hle if i.have_hle isn't zero.
	(parse_insn): Set i.have_hle to 1 for HLE prefix.
	(output_jump): Support up to 2 byte opcode.

	* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.

gas/testsuite/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/hle-intel.d: New.
	* gas/i386/hle.d: Likewise.
	* gas/i386/hle.s: Likewise.
	* gas/i386/hlebad.l: Likewise.
	* gas/i386/hlebad.s: Likewise.
	* gas/i386/rtm-intel.d: Likewise.
	* gas/i386/rtm.d: Likewise.
	* gas/i386/rtm.s: Likewise.
	* gas/i386/x86-64-hle-intel.d: Likewise.
	* gas/i386/x86-64-hle.d: Likewise.
	* gas/i386/x86-64-hle.s: Likewise.
	* gas/i386/x86-64-hlebad.l: Likewise.
	* gas/i386/x86-64-hlebad.s: Likewise.
	* gas/i386/x86-64-rtm-intel.d: Likewise.
	* gas/i386/x86-64-rtm.d: Likewise.
	* gas/i386/x86-64-rtm.s: Likewise.

	* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
	rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
	x86-64-rtm-intel.

include/opcode/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (XACQUIRE_PREFIX_OPCODE): New.
	(XRELEASE_PREFIX_OPCODE): Likewise.

opcodes/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (HLE_Fixup1): New.
	(HLE_Fixup2): Likewise.
	(HLE_Fixup3): Likewise.
	(Ebh1): Likewise.
	(Evh1): Likewise.
	(Ebh2): Likewise.
	(Evh2): Likewise.
	(Ebh3): Likewise.
	(Evh3): Likewise.
	(MOD_C6_REG_7): Likewise.
	(MOD_C7_REG_7): Likewise.
	(RM_C6_REG_7): Likewise.
	(RM_C7_REG_7): Likewise.
	(XACQUIRE_PREFIX): Likewise.
	(XRELEASE_PREFIX): Likewise.
	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	Ebh2/Evh2 on xchg.  Use Ebh3/Evh3 on mov.
	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	not, or, sbb, sub and xor.  Use Ebh3/Evh3 on mov.  Use
	MOD_C6_REG_7 and MOD_C7_REG_7.
	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7.  Add xend and
	xtest.
	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.

	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	CPU_RTM_FLAGS.
	(cpu_flags): Add CpuHLE and CpuRTM.
	(opcode_modifiers): Add HLEPrefixOk.

	* i386-opc.h (CpuHLE): New.
	(CpuRTM): Likewise.
	(HLEPrefixOk): Likewise.
	(i386_cpu_flags): Add cpuhle and cpurtm.
	(i386_opcode_modifier): Add hleprefixok.

	* i386-opc.tbl: Add HLEPrefixOk=3 to mov.  Add HLEPrefixOk to
	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	sbb, sub, xor and xadd.  Add HLEPrefixOk=2 to xchg with memory
	operand.  Add xacquire, xrelease, xabort, xbegin, xend and
	xtest.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2012-02-08 18:20:41 +00:00
H.J. Lu
8729a6f6a5 Add vmfunc 
gas/

2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add ".vmfunc".

	* doc/c-i386.texi: Document vmfunc.

gas/testsuite/

2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run vmfunc and x86-64-vmfunc.

	* gas/i386/vmfunc.d: New.
	* gas/i386/vmfunc.s: Likewise.
	* gas/i386/x86-64-vmfunc.d: Likewise.

opcodes/

2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (mod_table): Add vmfunc.

	* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
	(cpu_flags): CpuVMFUNC.

	* i386-opc.h (CpuVMFUNC): New.
	(i386_cpu_flags): Add cpuvmfunc.

	* i386-opc.tbl: Add vmfunc.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2012-01-13 22:19:32 +00:00
H.J. Lu
7a9068fe16 Add initial Intel K1OM support. 
bfd/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am (ALL_MACHINES): Add cpu-k1om.lo.
	(ALL_MACHINES_CFILES): Add cpu-k1om.c.
	* Makefile.in: Regenerated.

	* archures.c (bfd_architecture): Add bfd_arch_k1om.
	(bfd_k1om_arch): New.
	(bfd_archures_list): Add &bfd_k1om_arch.
	* bfd-in2.h: Regenerated.

	* config.bfd (targ64_selvecs): Add bfd_elf64_k1om_vec if
	bfd_elf64_x86_64_vec is supported.  Add bfd_elf64_k1om_freebsd_vec
	if bfd_elf64_x86_64_freebsd_vec is supported.
	(targ_selvecs): Likewise.

	* configure.in: Support bfd_elf64_k1om_vec and
	bfd_elf64_k1om_freebsd_vec.
	* configure: Regenerated.

	* cpu-k1om.c: New.

	* elf64-x86-64.c (elf64_k1om_elf_object_p): New.
	(bfd_elf64_k1om_vec): Likewise.
	(bfd_elf64_k1om_freebsd_vec): Likewise.

	* targets.c (bfd_elf64_k1om_vec): New.
	(bfd_elf64_k1om_freebsd_vec): Likewise.
	(_bfd_target_vector): Add bfd_elf64_k1om_vec and
	bfd_elf64_k1om_freebsd_vec.

binutils/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (init_dwarf_regnames): Handle EM_K1OM.

	* elfedit.c (elf_machine): Support EM_K1OM.
	(elf_class): Likewise.

	* readelf.c (guess_is_rela): Handle EM_K1OM.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(get_section_type_name): Likewise.
	(get_elf_section_flags): Likewise.
	(process_section_headers): Likewise.
	(get_symbol_index_type): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_32bit_pcrel_reloc): Likewise.
	(is_64bit_abs_reloc): Likewise.
	(is_64bit_pcrel_reloc): Likewise.
	(is_none_reloc): Likewise.

	* doc/binutils.texi: Mention K1OM for elfedit.

binutils/testsuite/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* binutils-all/elfedit.exp: Run elfedit-4.

	* binutils-all/elfedit-4.d: New.

gas/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add k1om.
	(i386_align_code): Handle PROCESSOR_K1OM.
	(check_cpu_arch_compatible): Check EM_K1OM.
	(i386_arch): Handle Intel K1OM.
	(i386_mach): Return bfd_mach_k1om for Intel K1OM.
	(i386_target_format): Return ELF_TARGET_K1OM_FORMAT for Intel
	K1OM.

	* config/tc-i386.h (ELF_TARGET_K1OM_FORMAT): New.
	(processor_type): Add PROCESSOR_K1OM.

	* doc/c-i386.texi: Document k1om.

gas/testsuite/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/k1om.d: New.
	* gas/i386/k1om-inval.l: Likewise.
	* gas/i386/k1om-inval.s: Likewise.

	* gas/i386/i386.exp: Run k1om-inval and k1om.

include/elf/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* common.h (EM_K1OM): New.

ld/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am (ALL_64_EMULATIONS): Add eelf_k1om.o and
	eelf_k1om_fbsd.o
	(eelf_k1om.c): New.
	(eelf_k1om_fbsd.c): Likewise.
	* Makefile.in: Regenerated.

	* configure.tgt (targ64_extra_emuls): Add elf_k1om if elf_x86_64
	is supported.  Add elf_k1om_fbsd if elf_x86_64_fbsd is supported.
	(targ_extra_emuls): Likewise.

	* emulparams/elf_k1om.sh: New.
	* emulparams/elf_k1om_fbsd.sh: Likewise.

ld/testsuite/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-x86-64/abs-k1om.d: New.
	* ld-x86-64/protected2-k1om.d: Likewise.
	* ld-x86-64/protected3-k1om.d: Likewise.

	* ld-x86-64/x86-64.exp: Run abs-k1om, protected2-k1om and
	protected3-k1om.

opcodes/

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_k1om_arch.
	* configure: Regenerated.

	* disassemble.c (disassembler): Handle bfd_k1om_arch.

	* i386-dis.c (print_insn): Handle bfd_mach_k1om and
	bfd_mach_k1om_intel_syntax.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
	~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
	(cpu_flags): Add CpuK1OM.

	* i386-opc.h (CpuK1OM): New.
	(i386_cpu_flags): Add cpuk1om.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2011-07-22 20:22:38 +00:00
H.J. Lu
6c30d220f1 Support AVX Programming Reference (June, 2011). 
gas/

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* config/tc-i386.c (i386_error): Add invalid_vsib_address and
	unsupported_vector_index_register.
	(cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid.
	(check_VecOperands): New.
	(match_template): Call check_VecOperands.  Handle
	invalid_vsib_address and unsupported_vector_index_register.
	(build_modrm_byte): Support VecSIB.  Check register-only source
	operand when two source operands are swapped.
	(i386_index_check): Allow Xmm/Ymm index registers.

	* doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt
	and invpcid./invpcid.

gas/testsuite/

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* gas/i386/arch-10-1.l: Updated.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.

	* gas/i386/arch-10.s: Add LZCNT to comments.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/arch-10-lzcnt.d: New.
	* gas/i386/avx-gather-intel.d: Likewise.
	* gas/i386/avx-gather.d: Likewise.
	* gas/i386/avx-gather.s: Likewise.
	* gas/i386/avx2-intel.d: Likewise.
	* gas/i386/avx2.d: Likewise.
	* gas/i386/avx2.s: Likewise
	* gas/i386/avx256int-intel.d: Likewise.
	* gas/i386/avx256int.d: Likewise.
	* gas/i386/avx256int.s: Likewise.
	* gas/i386/bmi2-intel.d: Likewise.
	* gas/i386/bmi2.d: Likewise.
	* gas/i386/bmi2.s: Likewise.
	* gas/i386/inval-invpcid.l:Likewise.
	* gas/i386/inval-invpcid.s: Likewise.
	* gas/i386/invpcid-intel.d: Likewise.
	* gas/i386/invpcid.d: Likewise.
	* gas/i386/invpcid.s: Likewise.
	* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
	* gas/i386/x86-64-avx-gather-intel.d: Likewise.
	* gas/i386/x86-64-avx-gather.d: Likewise.
	* gas/i386/x86-64-avx-gather.s: Likewise.
	* gas/i386/x86-64-avx2-intel.d: Likewise.
	* gas/i386/x86-64-avx2.d: Likewise.
	* gas/i386/x86-64-avx2.s: Likewise.
	* gas/i386/x86-64-avx256int-intel.d: Likewise.
	* gas/i386/x86-64-avx256int.d: Likewise.
	* gas/i386/x86-64-avx256int.s: Likewise.
	* gas/i386/x86-64-bmi2-intel.d: Likewise.
	* gas/i386/x86-64-bmi2.d: Likewise.
	* gas/i386/x86-64-bmi2.s: Likewise.
	* gas/i386/x86-64-inval-invpcid.l: Likewise.
	* gas/i386/x86-64-inval-invpcid.s: Likewise.
	* gas/i386/x86-64-invpcid-intel.d: Likewise.
	* gas/i386/x86-64-invpcid.d: Likewise.
	* gas/i386/x86-64-invpcid.s: Likewise.

opcodes/

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (XMGatherQ): New.
	* i386-dis.c (EXxmm_mb): New.
	(EXxmm_mb): Likewise.
	(EXxmm_mw): Likewise.
	(EXxmm_md): Likewise.
	(EXxmm_mq): Likewise.
	(EXxmmdw): Likewise.
	(EXxmmqd): Likewise.
	(VexGatherQ): Likewise.
	(MVexVSIBDWpX): Likewise.
	(MVexVSIBQWpX): Likewise.
	(xmm_mb_mode): Likewise.
	(xmm_mw_mode): Likewise.
	(xmm_md_mode): Likewise.
	(xmm_mq_mode): Likewise.
	(xmmdw_mode): Likewise.
	(xmmqd_mode): Likewise.
	(ymmxmm_mode): Likewise.
	(vex_vsib_d_w_dq_mode): Likewise.
	(vex_vsib_q_w_dq_mode): Likewise.
	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	(PREFIX_0F3882): Likewise.
	(PREFIX_VEX_0F3816): Likewise.
	(PREFIX_VEX_0F3836): Likewise.
	(PREFIX_VEX_0F3845): Likewise.
	(PREFIX_VEX_0F3846): Likewise.
	(PREFIX_VEX_0F3847): Likewise.
	(PREFIX_VEX_0F3858): Likewise.
	(PREFIX_VEX_0F3859): Likewise.
	(PREFIX_VEX_0F385A): Likewise.
	(PREFIX_VEX_0F3878): Likewise.
	(PREFIX_VEX_0F3879): Likewise.
	(PREFIX_VEX_0F388C): Likewise.
	(PREFIX_VEX_0F388E): Likewise.
	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	(PREFIX_VEX_0F38F5): Likewise.
	(PREFIX_VEX_0F38F6): Likewise.
	(PREFIX_VEX_0F3A00): Likewise.
	(PREFIX_VEX_0F3A01): Likewise.
	(PREFIX_VEX_0F3A02): Likewise.
	(PREFIX_VEX_0F3A38): Likewise.
	(PREFIX_VEX_0F3A39): Likewise.
	(PREFIX_VEX_0F3A46): Likewise.
	(PREFIX_VEX_0F3AF0): Likewise.
	(VEX_LEN_0F3816_P_2): Likewise.
	(VEX_LEN_0F3819_P_2): Likewise.
	(VEX_LEN_0F3836_P_2): Likewise.
	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	(VEX_LEN_0F38F5_P_0): Likewise.
	(VEX_LEN_0F38F5_P_1): Likewise.
	(VEX_LEN_0F38F5_P_3): Likewise.
	(VEX_LEN_0F38F6_P_3): Likewise.
	(VEX_LEN_0F38F7_P_1): Likewise.
	(VEX_LEN_0F38F7_P_2): Likewise.
	(VEX_LEN_0F38F7_P_3): Likewise.
	(VEX_LEN_0F3A00_P_2): Likewise.
	(VEX_LEN_0F3A01_P_2): Likewise.
	(VEX_LEN_0F3A38_P_2): Likewise.
	(VEX_LEN_0F3A39_P_2): Likewise.
	(VEX_LEN_0F3A46_P_2): Likewise.
	(VEX_LEN_0F3AF0_P_3): Likewise.
	(VEX_W_0F3816_P_2): Likewise.
	(VEX_W_0F3818_P_2): Likewise.
	(VEX_W_0F3819_P_2): Likewise.
	(VEX_W_0F3836_P_2): Likewise.
	(VEX_W_0F3846_P_2): Likewise.
	(VEX_W_0F3858_P_2): Likewise.
	(VEX_W_0F3859_P_2): Likewise.
	(VEX_W_0F385A_P_2_M_0): Likewise.
	(VEX_W_0F3878_P_2): Likewise.
	(VEX_W_0F3879_P_2): Likewise.
	(VEX_W_0F3A00_P_2): Likewise.
	(VEX_W_0F3A01_P_2): Likewise.
	(VEX_W_0F3A02_P_2): Likewise.
	(VEX_W_0F3A38_P_2): Likewise.
	(VEX_W_0F3A39_P_2): Likewise.
	(VEX_W_0F3A46_P_2): Likewise.
	(MOD_VEX_0F3818_PREFIX_2): Removed.
	(MOD_VEX_0F3819_PREFIX_2): Likewise.
	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
	(VEX_LEN_0F3A0E_P_2): Likewise.
	(VEX_LEN_0F3A0F_P_2): Likewise.
	(VEX_LEN_0F3A42_P_2): Likewise.
	(VEX_LEN_0F3A4C_P_2): Likewise.
	(VEX_W_0F3818_P_2_M_0): Likewise.
	(VEX_W_0F3819_P_2_M_0): Likewise.
	(prefix_table): Updated.
	(three_byte_table): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(vex_w_table): Likewise.
	(mod_table): Likewise.
	(putop): Handle "LW".
	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
	(OP_EX): Likewise.
	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
	vex_vsib_q_w_dq_mode.
	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
	(OP_VEX): Likewise.

	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
	and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
	(opcode_modifiers): Add VecSIB.

	* i386-opc.h (CpuAVX2): New.
	(CpuBMI2): Likewise.
	(CpuLZCNT): Likewise.
	(CpuINVPCID): Likewise.
	(VecSIB128): Likewise.
	(VecSIB256): Likewise.
	(VecSIB): Likewise.
	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
	(i386_opcode_modifier): Add vecsib.

	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2011-06-10 21:27:40 +00:00
Quentin Neill
d535accd98 Add CpuF16C to CPU_BDVER2_FLAGS. 
opcodes/
	2011-06-02  Quentin Neill  <quentin.neill@amd.com>

		* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
		* i386-init.h: Regenerated.
 2011-06-03 20:06:20 +00:00
Quentin Neill
4cab4add34 2011-05-10 Quentin Neill <quentin.neill@amd.com> 
gas/
        * config/tc-i386.c (cpu_arch): Add bdver2 and rename
        PROCESSOR_BDVER1 to PROCESSOR_BDVER.
        (i386_align_code): Rename PROCESSOR_BDVER1.
        (processor_type): Ditto.
        * doc/c-i386.texi: Add bdver2.

opcodes/
        * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
        * i386-init.h: Regenerated.

gas/testsuite/
        * gas/i386/i386.exp: Add new bdver2 test cases.
        * gas/i386/nops-1-bdver2.d: New.
        * gas/i386/x86-64-nops-1-bdver2.d: New.
 2011-05-11 22:35:20 +00:00
Quentin Neill
b13a3ca683 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits 
from bdver1 flags.
 2011-04-19 23:45:17 +00:00
Quentin Neill
2a2a0f38e7 Add support for TBM instructions. 
gas/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.

	* doc/c-i386.texi (i386-TBM): New section.

opcodes/

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

gas/testsuite

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* gas/i386/tbm.s: New.
	* gas/i386/tbm.d: New.
	* gas/i386/tbm-intel.d: New.
	* gas/i386/x86-64-tbm.s: New.
	* gas/i386/x86-64-tbm.d: New.
	* gas/i386/x86-64-tbm-intel.d: New.
	* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
	* gas/i386/arch-10.s: Add a TBM instruction.
	* gas/i386/arch-10-1.l: Add TBM instruction pattern.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
 2011-01-17 18:40:36 +00:00
H.J. Lu
f12dc42220 Implement BMI instructions. 2011-01-05 00:16:57 +00:00
H.J. Lu
4fb3aee212 Update copyright in comments to 2011. 2011-01-01 21:42:17 +00:00
H.J. Lu
0db46eb403 Update copyright to 2011. 
binutils/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* version.c (print_version): Update copyright to 2011.

gas/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* gas.c (parse_args): Update copyright to 2011.

gold/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* version.cc (print_version): Update copyright to 2011.

ld/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* ldver.c (ldversion): Update copyright to 2011.

opcodes/

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright to 2011.
 2011-01-01 20:55:48 +00:00
H.J. Lu
da98bb4c74 Add CpuNop to CPU_GENERIC64_FLAGS. 
gas/testsuite/

2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run x86-64-nops-1-g64.

	* gas/i386/x86-64-nops-1.d: Remove -mtune=generic64.

	* gas/i386/x86-64-nops-1-g64.d: New.

opcodes/

2010-10-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.

	* i386-init.h: Regenerated.
 2010-10-16 21:53:16 +00:00
H.J. Lu
56ffb74112 Add CheckRegSize to instructions which require register size check. 
gas/

2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (match_template): Check checkregsize
	instead of w for register size check.

gas/testsuite/

2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run inval-reg.

	* gas/i386/inval-reg.l: New.
	* gas/i386/inval-reg.s: Likewise.

opcodes/

2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add CheckRegSize.

	* i386-opc.h (CheckRegSize): New.
	(i386_opcode_modifier): Add checkregsize.

	* i386-opc.tbl: Add CheckRegSize to instructions which
	require register size check.
	* i386-tbl.h: Regenerated.
 2010-10-14 18:45:10 +00:00
H.J. Lu
2210942396 Don't generate multi-byte NOPs for i686. 
gas/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* config/tc-i386.c (arch_entry): Add negated bit to
	  disambiguate flag names starting with "no".
	  (cpu_arch): Add negated bit definitions.  Add
	  ".nop" CPU extension.
	  (i386_align_code): Use new .cpunop bit to decide
	  when to generate alignment using nops.
	  (set_cpu_arch): Use negated bit instead to decide
	  when to use cpu_flags or vs. cpu_flags_and_not.
	  (md_parse_option): Likewise.

gas/testsuite/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* gas/i386/arch-10-1.l: Add nopl instruction.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/arch-10.s: Likewise.
	* gas/i386/arch-10.d: Add nopl instruction, and +nopl extension
	flag to as flags.
	* gas/i386/nops-5-i686.d: Change alignment code generated for
	-mtune=i686.
	* gas/i386/nops-5.d: Change alignment code generated for
	.arch i686.
	* gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/x86-64-nops-5.d: Likewise.

opcodes/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
	to processor flags for PENTIUMPRO processors and later.
	* i386-opc.h (enum): Add CpuNop.
	(i386_cpu_flags): Add cpunop bit.
	* i386-opc.tbl: Change nop cpu_flags.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2010-08-06 18:22:50 +00:00
H.J. Lu
c7b8aa3a72 Support AVX Programming Reference (June, 2010) 
gas/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
	and .f16c.

	* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.

gas/testsuite/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* gas/i386/arch-10.s: Add xsaveopt.
	* gas/i386/x86-64-arch-2.s: Likwise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

	* gas/i386/f16c-intel.d: New.
	* gas/i386/f16c.d: Likewise.
	* gas/i386/f16c.s: Likewise.
	* gas/i386/fsgs-intel.d: Likewise.
	* gas/i386/fsgs.d: Likewise.
	* gas/i386/fsgs.s: Likewise.
	* gas/i386/rdrnd-intel.d: Likewise.
	* gas/i386/rdrnd.d: Likewise.
	* gas/i386/rdrnd.s: Likewise.
	* gas/i386/x86-64-f16c-intel.d: Likewise.
	* gas/i386/x86-64-f16c.d: Likewise.
	* gas/i386/x86-64-f16c.s: Likewise.
	* gas/i386/x86-64-fsgs-intel.d: Likewise.
	* gas/i386/x86-64-fsgs.d: Likewise.
	* gas/i386/x86-64-fsgs.s: Likewise.
	* gas/i386/x86-64-rdrnd-intel.d: Likewise.
	* gas/i386/x86-64-rdrnd.d: Likewise.
	* gas/i386/x86-64-rdrnd.s: Likewise.

	* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
	rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
	x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.

	* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.

	* gas/i386/x86-64-xsave-intel.d: Updated.
	* gas/i386/x86-64-xsave.d: Likewise.

opcodes/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* i386-dis.c (PREFIX_0FAE_REG_0): New.
	(PREFIX_0FAE_REG_1): Likewise.
	(PREFIX_0FAE_REG_2): Likewise.
	(PREFIX_0FAE_REG_3): Likewise.
	(PREFIX_VEX_3813): Likewise.
	(PREFIX_VEX_3A1D): Likewise.
	(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
	PREFIX_VEX_3A1D.
	(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
	(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
	CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
	(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.

	* i386-opc.h (CpuXsaveopt): New.
	(CpuFSGSBase):Likewise.
	(CpuRdRnd): Likewise.
	(CpuF16C): Likewise.
	(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
	cpuf16c.

	* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
	wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 2010-07-01 21:55:02 +00:00
H.J. Lu
c75ef631bd Update copyright. 
gas/

2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c: Update copyright.

opcodes/

2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c: Update copyright.
	* i386-gen.c: Likewise.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.
 2010-02-11 13:41:19 +00:00
Sebastian Pop
a683cc34e4 2010-02-10 Quentin Neill <quentin.neill@amd.com> 
Sebastian Pop  <sebastian.pop@amd.com>

gas:
        * config/tc-i386.c (vec_imm4) New operand type.
        (fits_in_imm4): New.
        (VEX_check_operands): New.
        (check_reverse): Call VEX_check_operands.
        (build_modrm_byte): Reintroduce code for 5
        operand insns.  Fix whitespace.

gas/testsuite:
        * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
        * gas/i386/x86-64-xop.s: Likewise.
        * gas/i386/xop.d: Likewise.
        * gas/i386/xop.s: Likewise.

opcodes:
        * i386-dis.c (OP_EX_VexImmW): Reintroduced
        function to handle 5th imm8 operand.
        (PREFIX_VEX_3A48): Added.
        (PREFIX_VEX_3A49): Added.
        (VEX_W_3A48_P_2): Added.
        (VEX_W_3A49_P_2): Added.
        (prefix table): Added entries for PREFIX_VEX_3A48
        and PREFIX_VEX_3A49.
        (vex table): Added entries for VEX_W_3A48_P_2 and
        and VEX_W_3A49_P_2.
        * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
        for Vec_Imm4 operands.
        * i386-opc.h (enum): Added Vec_Imm4.
        (i386_operand_type): Added vec_imm4.
        * i386-opc.tbl: Add entries for vpermilp[ds].
        * i386-init.h: Regenerated.
        * i386-tbl.h: Regenerated.
 2010-02-11 05:06:14 +00:00
Sebastian Pop
68339fdf88 2010-02-03 Quentin Neill <quentin.neill@amd.com> 
gas/
	* config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1.
	(i386_align_code): Rename  PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1.
	* config/tc-i386.h (processor_type): Same.
	* doc/c-i386.texi: Change amdfam15 to bdver1.

opcodes/
	* i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
	to CPU_BDVER1_FLAGS
	* i386-init.h: Regenerated.

testsuite/
	* gas/i386/i386.exp: Rename amdfam15 test cases to bdver1.
	* gas/i386/x86-64-nops-1-amdfam15.d: Renamed test case to
	gas/i386/x86-64-nops-1-bdver1.d.
	* gas/i386/nops-1-amdfam15.d: Renamed test case to
	gas/i386/nops-1-bdver1.d.
 2010-02-03 20:36:14 +00:00
Sebastian Pop
69dd98654a 2010-01-06 Quentin Neill <quentin.neill@amd.com> 
gas/
       * config/tc-i386.c (cpu_arch): Add amdfam15.
         (i386_align_code): Add PROCESSOR_AMDFAM15 cases.
       * config/tc-i386.h (processor_type): Add PROCESSOR_AMDFAM15.
       * doc/c-i386.texi: Add amdfam15.

opcodes/
       * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
       * i386-init.h: Regenerated.

testsuite/
       * gas/i386/i386.exp: Add new amdfam15 test cases.
       * gas/i386/nops-1-amdfam15.d: New.
 2010-01-06 22:52:47 +00:00
H.J. Lu
2426c15ff8 Replace VexNDS, VexNDD and VexLWP with VexVVVV. 
gas/

2009-12-19  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_operands): Check vexvvvv instead
	of vexnds and vexndd.
	(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
	and vexlwp.

opcodes/

2009-12-19  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
	VexLWP.  Add VexVVVV.

	* i386-opc.h (VexNDS): Removed.
	(VexNDD): Likewise.
	(VexLWP): Likewise.
	(VEXXDS): New.
	(VEXNDD): Likewise.
	(VEXLWP): Likewise.
	(VexVVVV): Likewise.
	(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
	Add vexvvvv.

	* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
	VexVVVV=2 and VexLWP with VexVVVV=3.
	* i386-tbl.h: Regenerated.
 2009-12-19 18:36:27 +00:00
H.J. Lu
94ff3a50d8 Move Imm1 before Imm8. 
2009-12-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_types): Move Imm1 before Imm8.
 2009-12-18 21:07:58 +00:00
H.J. Lu
2eb952a4d9 Remove ByteOkIntel. 
gas/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
	Intel syntax if size is ignored and b/l/w suffixes are
	illegal.
	(check_byte_reg): Remove byteokintel check.

opcodes/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove ByteOkIntel.

	* i386-opc.h (ByteOkIntel): Removed.
	(i386_opcode_modifier): Remove byteokintel.

	* i386-opc.tbl: Remove ByteOkIntel.
	* i386-tbl.h: Regenerated.
 2009-12-16 20:08:32 +00:00
H.J. Lu
7f399153c6 Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. 
gas/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38,
	vex0f3a, xop08, xop09 and xop0a with vexopcode.

opcodes/

2009-12-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38,
	Vex0F3A, XOP08, XOP09 and XOP0A.  Add VexOpcode.

	* i386-opc.h (Vex0F): Removed.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(VexOpcode): New.
	(VEX0F): Likewise.
	(VEX0F38): Likewise.
	(VEX0F3A): Likewise.
	(XOP08): Defined as a macro.
	(XOP09): Likewise.
	(XOP0A): Likewise.
	(i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08,
	xop09 and xop0a.  Add vexopcode.

	* i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
	VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3,
	XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5.
	* i386-tbl.h: Regenerated.
 2009-12-16 15:43:16 +00:00
H.J. Lu
8cd7925b45 Replace Vex2Sources and Vex3Sources with VexSources. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_operands): Check vexsources
	instead of vex3sources.
	(build_modrm_byte): Check vexsources instead of vex2sources
	and vex3sources.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove Vex3Sources and
	Vex2Sources.  Add VexSources.

	* i386-opc.h ()Vex2Sources: Removed.
	(Vex3Sources): Likewise.
	(VEX2SOURCES): New.
	(VEX3SOURCES): Likewise.
	(VexSources): Likewise.
	(i386_opcode_modifier): Remove vex2sources and vex3sources.
	Add vexsources.

	* i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
	Vex3Sourceswith VexSources=2.
	* i386-tbl.h: Regenerated.
 2009-12-16 04:00:35 +00:00
H.J. Lu
1ef99a7be9 Remove VexW0 and VexW1. Add VexW. 
gas/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1
	with vexw.
	(build_modrm_byte): Likewise.

opcodes/

2009-12-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1.  Add
	VexW.

	* i386-opc.h (VexW0): Removed.
	(VexW1): Likewise.
	(VEXW0): New.
	(VEXW1): Likewise.
	(VexW): Likewise.
	(i386_opcode_modifier): Remove vexw0 and vexw1.  Add vexw.

	* i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with
	Vex=2.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-12-16 02:10:45 +00:00
Sebastian Pop
f0ae4a24b0 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> 
gas/
	* config/tc-i386.c (cpu_arch): Remove cvt16.
	(md_show_usage): Same.
	* doc/c-i386.texi: Same.

	gas/testsuite/
	* gas/i386/cvt16.d: Removed.
	* gas/i386/cvt16.s: Removed.
	* gas/i386/x86-64-cvt16.d: Removed.
	* gas/i386/x86-64-cvt16.s: Removed.
	* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.

	opcodes/
	* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
	(VEX_LEN_XOP_08_A1): Removed.
	(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
	VEX_LEN_XOP_08_A1.
	(vex_len_table): Same.
	* i386-gen.c (CPU_CVT16_FLAGS): Removed.
	(cpu_flags): Remove field for CpuCVT16.
	* i386-opc.h (CpuCVT16): Removed.
	(i386_cpu_flags): Remove bitfield cpucvt16.
	(i386-opc.tbl): Remove CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 20:28:59 +00:00
Sebastian Pop
5dd85c9970 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> 
Quentin Neill  <quentin.neill@amd.com>

	gas/
	* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
	(build_vex_prefix): Handle xop08.
	(md_assemble): Don't special case the constant 3 for insns using MODRM.
	(build_modrm_byte): Handle vex2sources.
	(md_show_usage): Add xop and cvt16.
	* doc/c-i386.texi: Document fma4, xop, and cvt16.

	gas/testsuite/
	* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
	Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
	* gas/i386/lwp.d: Update name of the testcase.
	* gas/i386/x86-64-xop.d: New.
	* gas/i386/x86-64-xop.s: New.
	* gas/i386/xop.d: New.
	* gas/i386/xop.s: New.
	* gas/i386/cvt16.d: New.
	* gas/i386/cvt16.s: New.

	opcodes/
	* i386-dis.c (OP_Vex_2src_1): New.
	(OP_Vex_2src_2): New.
	(Vex_2src_1): New.
	(Vex_2src_2): New.
	(XOP_08): Added.
	(VEX_LEN_XOP_08_A0): Added.
	(VEX_LEN_XOP_08_A1): Added.
	(VEX_LEN_XOP_09_80): Added.
	(VEX_LEN_XOP_09_81): Added.
	(xop_table): Added an entry for XOP_08.  Handle xop instructions.
	(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
	VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
	(get_valid_dis386): Handle XOP_08.
	(OP_Vex_2src): New.
	* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
	(cpu_flags): Add CpuXOP and CpuCVT16.
	(opcode_modifiers): Add XOP08, Vex2Sources.
	* i386-opc.h (CpuXOP): Added.
	(CpuCVT16): Added.
	(i386_cpu_flags): Add cpuxop and cpucvt16.
	(XOP08): Added.
	(Vex2Sources): Added.
	(i386_opcode_modifier): Add xop08, vex2sources.
	* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 04:04:17 +00:00
H.J. Lu
c32fa91d70 gas/ 
2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (LOCKREP_PREFIX): Removed.
	(REP_PREFIX): New.
	(LOCK_PREFIX): Likewise.
	(PREFIX_GROUP): Likewise.
	(REX_PREFIX): Updated.
	(MAX_PREFIXES): Likewise.
	(add_prefix): Updated.  Return enum PREFIX_GROUP.
	(md_assemble): Check for lock without a lockable instruction.
	(parse_insn): Updated.
	(output_insn): Likewise.

gas/testsuite/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
	x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.

	* gas/i386/lock-1-intel.d: New.
	* gas/i386/lock-1.d: Likewise.
	* gas/i386/lock-1.s: Likewise.
	* gas/i386/lockbad-1.l: Likewise.
	* gas/i386/lockbad-1.s: Likewise.
	* gas/i386/x86-64-lock-1-intel.d: Likewise.
	* gas/i386/x86-64-lock-1.d: Likewise.
	* gas/i386/x86-64-lock-1.s: Likewise.
	* gas/i386/x86-64-lockbad-1.l: Likewise.
	* gas/i386/x86-64-lockbad-1.s: Likewise.

opcodes/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IsLockable.

	* i386-opc.h (IsLockable): New.
	(i386_opcode_modifier): Add islockable.

	* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
	bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
	xor, xadd and xchg.
	* i386-tbl.h: Regenerated.
 2009-11-12 18:57:14 +00:00
Sebastian Pop
f88c9eb030 2009-11-05 Sebastian Pop <sebastian.pop@amd.com> 
Quentin Neill  <quentin.neill@amd.com>

	* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
	(build_vex_prefix): Handle xop09 and xop0a.
	(build_modrm_byte): Handle vexlwp.
	(md_show_usage): Add lwp.
	* gas/doc/c-i386.texi (i386-LWP): New section.

	* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
	run lwp in 32-bit mode.
	* gas/testsuite/gas/i386/x86-64-lwp.d: New.
	* gas/testsuite/gas/i386/x86-64-lwp.s: New.
	* gas/testsuite/gas/i386/lwp.d: New.
	* gas/testsuite/gas/i386/lwp.s: New.

	* opcodes/i386-dis.c (OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	(USE_XOP_8F_TABLE): New.
	(XOP_8F_TABLE): New.
	(REG_XOP_LWPCB): New.
	(REG_XOP_LWP): New.
	(XOP_09): New.
	(XOP_0A): New.
	(reg_table): Redirect REG_8F to XOP_8F_TABLE.
	Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
	(xop_table): New.
	(get_valid_dis386): Handle USE_XOP_8F_TABLE.
	Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
	to access to the vex_table.
	(OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
	(cpu_flags): Add CpuLWP.
	(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
	* opcodes/i386-opc.h (CpuLWP): New.
	(i386_cpu_flags): Add bit cpulwp.
	(VexLWP): New.
	(XOP09): New.
	(XOP0A): New.
	(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
	* opcodes/i386-opc.tbl (llwpcb): Added.
	(lwpval): Added.
	(lwpins): Added.
 2009-11-05 23:40:05 +00:00
H.J. Lu
2bf05e5730 gas/ 
2009-09-24  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (build_vex_prefix): Check vex == 2 instead
	of vex256.

opcodes/

2009-09-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove Vex256.
	(set_bitfield): Handle XXX=V.

	* i386-opc.h (Vex): Update comments.
	(Vex256): Removed.
	(VexNDS): Updated.
	(i386_opcode_modifier): Change vex to 2 bits.  Remove vex256.

	* i386-opc.tbl: Replace "Vex|Vex256" with Vex=2.
	* i386-tbl.h: Regenerated.
 2009-09-24 16:37:09 +00:00
Nick Clifton
d3ce72d070 Updated sources to avoid using the identifier name "new", which is a 
keyword in c++.

        * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable
        new to new_symbol.
        * bfd/coffgen.c (coff_make_empty_symbol)
        (coff_bfd_make_debug_symbol): Rename variable new to new_symbol.
        * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable
        new to new_insn.
        * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to
        new_d.
        * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new
        to new_symbol.
        * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument
        new to new_reloc.
        * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string.
        * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to
        new_symbol.
        * bfd/linker.c (bfd_new_link_order): Rename variable new to
        new_lo.
        * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to
        symbol.
        * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to
        new_symbol_type.
        * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable
        new to new_symbol_type.
        * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new
        to new_symbol.
        * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to
        new_dump.
        (read_hdr, rs6000coff_core_p)
        (rs6000coff_core_file_matches_executable_p)
        (rs6000coff_core_file_failing_command)
        (rs6000coff_core_file_failing_signal): Updated function to use new
        union member name.
        * bfd/som.c (som_make_empty_symbol): Rename variable new to
        new_symbol_type.
        * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new
        to new_symbol.
        * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename
        variable new to new_symbol.
        * binutils/nlmconv.c (main): Rename variable new to new_name.
        * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to
        new_reg.
        * gas/config/tc-dlx.c (parse_operand): Rename variable new to
        new_pos.
        * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable
        new to newr.
        * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable
        new to new_pointer.
        * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got):
        Change name from new to new_pointer.
        * gas/config/tc-or32.c (parse_operand): Rename variable new to
        new_pointer.
        * gas/config/tc-pdp11.c (md_assemble): Rename variable new to
        new_pointer.
        * gas/config/tc-pj.c (alias): Change argument new to new_name.
        * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable
        new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable
        new to new_i2n. (s3_convert): Rename variables old and new to
        r_old and r_new.
        * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable
        new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable
        new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename
        variables old and new to r_old and r_new.
        * gas/config/tc-sh.c (parse_exp): Rename variable new to
        new_pointer.
        * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to
        new_pointer.
        * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new
        to new_pointer.
        * gas/config/tc-z8k.c (parse_exp): Rename variable new to
        new_pointer.
        * gas/listing.c (listing_newline): Rename variable new to new_i.
        * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop)
        (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new
        to new_e.
        * ld/ldfile.c (ldfile_add_library_path): Rename variable new to
        new_dirs. (ldfile_add_arch): Rename variable new to new_arch.
        * ld/ldlang.c (new_statement, lang_final, lang_add_wild)
        (lang_target, lang_add_fill, lang_add_data, lang_add_assignment)
        (lang_add_insert): Rename variable new to new_stmt. (new_afile):
        Added missing cast. (lang_memory_region_lookup): Rename variable
        new to new_region. (init_os): Rename variable new to
        new_userdata. (lang_add_section): Rename variable new to
        new_section. (ldlang_add_undef): Rename variable new to
        new_undef. (realsymbol): Rename variable new to new_name.
        * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op.

        Updated sources to avoid using the identifier name "template",
        which is a keyword in c++.

        * bfd/elf32-arm.c (struct stub_def): Rename member template to
        template_sequence. (arm_build_one_stub,
        find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub):
        Rename variable template to template_sequence.
        * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl):
        Rename variable template to template_val.
        * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct
        asm_barrier_opt): Change member template to
        template_name. (md_begin): Update code to reflect new member
        names.
        * gas/config/tc-i386.c (struct templates, struct _i386_insn)
        (match_template, cpu_flags_match, match_reg_size, match_mem_size)
        (operand_size_match, md_begin, i386_print_statistics, pi)
        (build_vex_prefix, md_assemble, parse_insn, optimize_imm)
        (optimize_disp): Updated code to use new names. (parse_insn):
        Added casts.
        * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated
        code to use new names.
        * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member
        template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst,
        s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to
        use new names.
        * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member
        template to template_name. (s7_parse_16_32_inst,
        s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to
        use new names.
        * gas/config/tc-tic30.c (md_begin, struct tic30_insn)
        (md_assemble): Update code to use new names.
        * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin)
        (optimize_insn, tic54x_parse_insn, next_line_shows_parallel):
        Update code to use new names.
        * include/opcode/tic30.h (template): Rename type template to
        insn_template. Updated code to use new name.
        * include/opcode/tic54x.h (template): Rename type template to
        insn_template.
        * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name.
        * opcodes/i386-dis.c (putop): Update code to use new name.
        * opcodes/i386-gen.c (process_i386_opcodes): Update code to use
        new name.
        * opcodes/i386-opc.h (struct template): Rename struct template to
        insn_template. Update code accordingly.
        * opcodes/i386-tbl.h (i386_optab): Update type to use new name.
        * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template
        to template_val.
        * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction):
        Update code to use new name.
        * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size)
        (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn):
        Update code to use new name.
        * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab):
        Update type to new name.
 2009-08-29 22:11:02 +00:00
H.J. Lu
8a9036a406 bfd/ 
2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* archures.c (bfd_architecture): Add bfd_arch_l1om.
	(bfd_l1om_arch): New.
	(bfd_archures_list): Add &bfd_l1om_arch.
	* bfd-in2.h: Regenerated.

	* config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if
	bfd_elf64_x86_64_vec is supported.  Add bfd_elf64_l1om_freebsd_vec
	if bfd_elf64_x86_64_freebsd_vec is supported.
	(targ_selvecs): Likewise.

	* configure.in: Support bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.
	* configure: Regenerated.

	* cpu-l1om.c: New.

	* elf64-x86-64.c (elf64_l1om_elf_object_p): New.
	(bfd_elf64_l1om_vec): Likewise.
	(bfd_elf64_l1om_freebsd_vec): Likewise.

	* Makefile.am (ALL_MACHINES): Add cpu-l1om.lo.
	(ALL_MACHINES_CFILES): Add cpu-l1om.c.
	* Makefile.in: Regenerated.

	* targets.c (bfd_elf64_l1om_vec): New.
	(bfd_elf64_l1om_freebsd_vec): Likewise.
	(_bfd_target_vector): Add bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.

binutils/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* readelf.c (guess_is_rela): Handle EM_L1OM.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(get_section_type_name): Likewise.
	(get_elf_section_flags): Likewise.
	(get_symbol_index_type): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_32bit_pcrel_reloc): Likewise.
	(is_64bit_abs_reloc): Likewise.
	(is_64bit_pcrel_reloc): Likewise.
	(is_none_reloc): Likewise.

gas/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add l1om.
	(check_cpu_arch_compatible): New.
	(set_cpu_arch): Use it.
	(i386_arch): New.
	(i386_mach): Return bfd_mach_l1om for Intel L1OM.
	(md_show_usage): Display l1om.
	(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
	cpu_arch_isa_flags.bitfield.cpul1om is set.

	* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
	(i386_arch): New.
	(ELF_TARGET_L1OM_FORMAT): Likewise.

	* doc/c-i386.texi: Document l1om.

gas/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/l1om.d: New.
	* gas/i386/l1om-inval.l: Likewise.
	* gas/i386/l1om-inval.s: Likewise.

	* gas/i386/i386.exp: Run l1om-inval and l1om.

include/elf/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* common.h (EM_L1OM): New.

ld/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64
	is supported.  Add elf_l1om_fbsd if elf_x86_64_fbsd is supported.
	(targ_extra_emuls): Likewise.

	* Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and
	eelf_l1om_fbsd.o
	(eelf_l1om.c): New.
	(eelf_l1om_fbsd.c): Likewise.
	* Makefile.in: Regenerated.

	* emulparams/elf_l1om.sh: New.
	* emulparams/elf_l1om_fbsd.sh: Likewise.

ld/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-x86-64/abs-l1om.d: New.
	* ld-x86-64/protected2-l1om.d: Likewise.
	* ld-x86-64/protected3-l1om.d: Likewise.

	* ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and
	protected3-l1om.

opcodes/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_l1om_arch.
	* disassemble.c (disassembler): Likewise.

	* configure: Regenerated.

	* i386-dis.c (print_insn): Handle bfd_mach_l1om and
	bfd_mach_l1om_intel_syntax.  Use 8 bytes per line for Intel L1OM.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM.
	Add CPU_L1OM_FLAGS.
	(cpu_flags): Add CpuL1OM.
	(set_bitfield): Take an argument to set the value field.
	(process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY).
	(process_i386_opcode_modifier): Updated.
	(process_i386_operand_type): Likewise.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

	* i386-opc.h (CpuL1OM): New.
	(CpuXsave): Updated.
	(i386_cpu_flags): Add cpul1om.
 2009-07-25 14:58:58 +00:00
Jan Beulich
309d33736f gas/ 
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx,
	.nosse, and .noavx.
	(cpu_flags_and_not): New.
	(set_cpu_arch): Check whether sub-architecture specified is a
	feature disable.
	(md_parse_option): Likewise.
	(parse_real_register): Don't return floating point register
	when x87 functionality is disabled.
	(md_show_usage): Add new sub-options.
	* doc/c-i386.texi: Update with new command line sub-options.

gas/testsuite/
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/8087.[ds]: New.
	* gas/i386/287.[ds]: New.
	* gas/i386/387.[ds]: New.
	* gas/i386/no87.[ls]: New.
	* gas/i386/no87-2.[ls]: New.
	* gas/i386/i386.exp: Run new tests.
	* gas/i386/att-regs.s: Also check FPU register access.
	* gas/i386/intel-regs.s: Likewise.
	* gas/i386/att-regs.d: Adjust expectations.
	* gas/i386/intel-regs.d: Likewise.

opcodes/
2009-07-24  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add
	frstpm.
	* i386-gen.c (cpu_flag_init): Add FP enabling flags where needed.
	(cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP.
	(set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387.
	* i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP):
	Define.
	(union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687,
	and cpufisttp.
	* i386-opc.tbl: Qualify floating point instructions by their
	respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos,
	and fsincos to be avilable only on 387. Fix fstsw ax to be
	available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm,
	and frstpm.
	* i386-init.h, i386-tbl.h: Regenerate.
 2009-07-24 15:41:20 +00:00
Dwarakanath Rajagopal
922d8de8c1 <gas changes> 
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS.
	(build_modrm_byte): Add support to handle FMA4 instructions.
	(md_show_usage): Add fma4.

<gas/testsuite changes>
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* gas/i386/i386.exp: Add FMA4 tests.
	* gas/i386/x86-64-fma4.d: Ditto.
	* gas/i386/fma4.d: Ditto.
	* gas/i386/x86-64-fma4.s: Ditto.
	* gas/i386/fma4.s: Ditto.

<opcodes changes>
2009-07-06  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* i386-opc.h (CpuFMA4): Add CpuFMA4.
	(i386_cpu_flags): New.
	* i386-gen.c: Add CPU_FMA4_FLAGS.
	* i386-opc.tbl: Add FMA4 instructions.
	* i386-tbl.h: Regenerate.
	* i386-init.h: Regenerate.
	* i386-dis.c (OP_VEX_FMA): New. Handle FMA4.
	(OP_XMM_VexW): Ditto.
	(OP_EX_VexW): Ditto.
	(VEXI4_Fixup): Ditto.
	(VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros.
	(PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New.
	(PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New.
	(PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New.
	(PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New.
	(PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New.
	(PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New.
	(PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New.
	(VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New.
	(VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New.
	(VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New.
	(get_vex_imm8): New. handle FMA4.
	(OP_EX_VexReg): Ditto.
 2009-07-06 19:34:30 +00:00
Dwarakanath Rajagopal
c1e679ec0a <gas changes> 
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* config/tc-i386.c (process_drex): Delete. Remove SSE5 support.
	(build_modrm_byte): Remove DREX handling support.
	(DREX_*): Delete.
	(drex_byte): Delete.
	(md_assemble): Remove DREX handling support.
	(process_operands): Remove DREX, SSE5 support.
	(i386_insn): Remove DREX.

<gas/testsuite changes>
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* gas/i386/i386.exp: Remove SSE5 tests.
	* gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests.
	* gas/i386/x86-64-sse5.d: Ditto.
	* gas/i386/arch-10-1.l: Remove SSE5 tests.
	* gas/i386/arch-10-2.l: Ditto.
	* gas/i386/arch-10-3.l: Ditto.
	* gas/i386/arch-10-4.l: Ditto.
	* gas/i386/arch-10.d: Ditto.
	* gas/i386/arch-10.s: Ditto.
	* gas/i386/arch-4.s: Delete. Remove SSE5 tests.
	* gas/i386/arch-4.d: Ditto.
	* gas/i386/arch-8.s: Ditto.
	* gas/i386/arch-8.d: Ditto.
	* gas/i386/arch-2.s: Remove SSE5 tests.
	* gas/i386/arch-2.d: Remove SSE5 tests.
	* gas/i386/x86-64-arch-2.s: Ditto.

<opcodes changes>
2009-05-22  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>

	* i386-opc.h (Cpusse5): Delete.
	(i386_cpu_flags): Delete.
	* i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc.
	* i386-opc.tbl: Remove SSE5 instructions.
	* i386-tbl.h: Regenerate.
	* i386-init.h: Regenerate.
	* i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling.
	(print_drex_arg): Delete.
	(OP_DREX4): Delete.
	(OP_DREX3): Delete.
	(OP_DREX_ICMP): Delete.
	(OP_DREX_FCMP): Delete.
	(DREX_*): Delete.
	(THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
 2009-05-22 15:57:25 +00:00
H.J. Lu
4c664d7bf7 gas/ 
2009-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (vex_imm4): Removed.
	(VEX_check_operands): Likewise.
	(match_template): Updated.

opcodes/

2009-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4.
	(operand_types): Remove Vex_Imm4.

	* i386-opc.h (Vex_Imm4): Removed.
	(OTMax): Updated.
	(i386_operand_type): Remove vex_imm4.

	* i386-opc.tbl: Remove Vex_Imm4 comments.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-02-23 20:41:46 +00:00
H.J. Lu
8acd537727 2009-01-13 H.J. Lu <hongjiu.lu@intel.com> 
* i386-gen.c (cpu_flag_init): Remove a white space.
	(operand_type_init): Likewise.
 2009-01-14 00:42:07 +00:00
H.J. Lu
bd5295b282 gas/ 
2009-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
	.syscall.
	(i386_align_code): Handle PROCESSOR_COREI7.
	(md_show_usage): Add corei7, clflush and syscall.
	(i386_target_format): Replace cpup4 with cpuclflush.

	* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.

	* doc/c-i386.texi: Document corei7, clflush and syscall.

gas/testsuite/

2009-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10.s: Add clflush and syscall.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2009-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
	CpuClflush and CpuSYSCALL, respectively. Remove CpuK8.  Add
	CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
	(cpu_flags): Remove CpuP4, CpuK6 and CpuK8.  Add CpuClflush
	and CpuSYSCALL.
	(lineno): Removed.
	(set_bitfield): Take an argument, lineno.  Don't report lineno
	on error if it is -1.
	(process_i386_cpu_flag): Take an argument, lineno.
	(process_i386_opcode_modifier): Likewise.
	(process_i386_operand_type): Likewise.
	(output_i386_opcode): Likewise.
	(opcode_hash_entry): Add lineno.
	(process_i386_opcodes): Updated.
	(process_i386_registers): Likewise.
	(process_i386_initializers): Likewise.

	* i386-opc.h (CpuP4): Removed.
	(CpuK6): Likewise.
	(CpuK8): Likewise.
	(CpuClflush): New.
	(CpuSYSCALL): Likewise.
	(CpuMMX): Updated.
	(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8.  Add
	cpuclflush and cpusyscall.

	* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
	syscall and sysret.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-01-10 17:25:52 +00:00
H.J. Lu
1b7f3fb0dd gas/ 
2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .rdtscp.
	(md_show_usage): Display rdtscp.

	* doc/c-i386.texi: Document rdtscp.

gas/testsuite/

2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10.s: Add rdtscp.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2009-01-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS
	and CPU_AMDFAM10_FLAGS.  Add CPU_RDTSCP_FLAGS.
	(cpu_flags): Add CpuRdtscp.
	(set_bitfield): Remove CpuSledgehammer check.

	* i386-opc.h (CpuRdtscp): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpurdtscp.

	* i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-01-09 20:32:32 +00:00
H.J. Lu
22da050bbf 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> 
* i386-gen.c (process_copyright): Update for 2009.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2009-01-06 01:14:45 +00:00
H.J. Lu
b6169b206a gas/ 
2008-12-20  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (_i386_insn): Add swap_operand.
	(parse_insn): Handle ".s".
	(match_template): Handle swap_operand.

	* doc/c-i386.texi: Document .s suffix.

gas/testsuite/

2008-12-20  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
	sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
	x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.

	* gas/i386/opts.d: New.
	* gas/i386/opts-intel.d: Likewise.
	* gas/i386/opts.s: Likewise.
	* gas/i386/sse2avx-opts.d: Likewise.
	* gas/i386/sse2avx-opts-intel.d: Likewise.
	* gas/i386/x86-64-opts.d: Likewise.
	* gas/i386/x86-64-opts-intel.d: Likewise.
	* gas/i386/x86-64-opts.s: Likewise.
	* gas/i386/x86-64-sse2avx-opts.d: Likewise.
	* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.

opcodes/

2008-12-20  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (EbS): New.
	(EvS): Likewise.
	(EMS): Likewise.
	(EXqS): Likewise.
	(EXxS): Likewise.
	(b_swap_mode): Likewise.
	(v_swap_mode): Likewise.
	(q_swap_mode): Likewise.
	(x_swap_mode): Likewise.
	(v_mode): Updated.
	(w_mode): Likewise.
	(t_mode): Likewise.
	(xmm_mode): Likewise.
	(swap_operand): Likewise.
	(dis386): Use EbS on movB.  Use EvS on moveS.
	(dis386_twobyte): Use EXxS on movapX.
	(prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
	vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
	(vex_table): Use EXxS on vmovapX.
	(vex_len_table): Use EXqS on vmovq.
	(intel_operand_size): Handle b_swap_mode, v_swap_mode,
	q_swap_mode and x_swap_mode.
	(OP_E_register): Handle b_swap_mode and v_swap_mode.
	(OP_EM): Handle v_swap_mode.
	(OP_EX): x_swap_mode and q_swap_mode.

	* i386-gen.c (opcode_modifiers): Add S.

	* i386-opc.h (S): New.
	(Modrm): Updated.
	(i386_opcode_modifier): Add s.

	* i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
	movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
	* i386-tbl.h: Regenerated.
 2008-12-20 17:40:51 +00:00
H.J. Lu
035475035d 2008-12-08 H.J. Lu <hongjiu.lu@intel.com> 
* i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
 2008-12-08 18:07:26 +00:00
H.J. Lu
c587b3f982 2008-09-30 H.J. Lu <hongjiu.lu@intel.com> 
* i386-gen.c: Include "hashtab.h".
	(next_field): Take a new argument, last.  Check last.
	(process_i386_cpu_flag): Updated.
	(process_i386_opcode_modifier): Likewise.
	(process_i386_operand_type): Likewise.
	(process_i386_registers): Likewise.
	(output_i386_opcode): New.
	(opcode_hash_entry): Likewise.
	(opcode_hash_table): Likewise.
	(opcode_hash_hash): Likewise.
	(opcode_hash_eq): Likewise.
	(process_i386_opcodes): Use opcode hash table and opcode array.
 2008-09-30 19:47:14 +00:00
H.J. Lu
f1f8f695c0 gas/ 
2008-05-02  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention XSAVE, EPT and MOVBE.

	* config/tc-i386.c (cpu_arch): Add .movbe and .ept.
	(md_show_usage): Add .movbe and .ept.

	* doc/c-i386.texi: Add movbe and ept to -march=.  Document
	.movbe and .ept.

gas/testsuite/

2008-05-02  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
	ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
	x86-64-inval-movbe.  x86-64-ept, x86-64-ept-intel and
	x86-64-inval-ept.

	* gas/i386/arch-10.s: Add movbe and invept.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/ept.d: New file
	* gas/i386/ept-intel.d: Likewise.
	* gas/i386/ept.s: Likewise.
	* gas/i386/inval-ept.l: Likewise.
	* gas/i386/inval-ept.s: Likewise.
	* gas/i386/inval-movbe.l: Likewise.
	* gas/i386/inval-movbe.s: Likewise.
	* gas/i386/movbe.d: Likewise.
	* gas/i386/movbe-intel.d: Likewise.
	* gas/i386/movbe.s: Likewise.
	* gas/i386/x86-64-inval-ept.l: Likewise.
	* gas/i386/x86-64-inval-ept.s: Likewise.
	* gas/i386/x86-64-inval-movbe.l: Likewise.
	* gas/i386/x86-64-inval-movbe.s: Likewise.
	* gas/i386/x86-64-ept.d: Likewise.
	* gas/i386/x86-64-ept-intel.d: Likewise.
	* gas/i386/x86-64-ept.s: Likewise.
	* gas/i386/x86-64-movbe.d: Likewise.
	* gas/i386/x86-64-movbe-intel.d: Likewise.
	* gas/i386/x86-64-movbe.s: Likewise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2008-05-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (MOVBE_Fixup): New.
	(Mo): Likewise.
	(PREFIX_0F3880): Likewise.
	(PREFIX_0F3881): Likewise.
	(PREFIX_0F38F0): Updated.
	(prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881.  Update
	PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
	(three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.

	* i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
	CPU_EPT_FLAGS.
	(cpu_flags): Add CpuMovbe and CpuEPT.

	* i386-opc.h (CpuMovbe): New.
	(CpuEPT): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpumovbe and cpuept.

	* i386-opc.tbl: Add entries for movbe and EPT instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2008-05-02 16:53:40 +00:00
H.J. Lu
81f8a9131a gas/ 
2008-04-22  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_assemble): Don't check SSE instructions
	if noavx is 0.

opcodes/

2008-04-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add NoAVX.

	* i386-opc.h (NoAVX): New.
	(OldGcc): Updated.
	(i386_opcode_modifier): Add noavx.

	* i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
	instructions which don't have AVX equivalent.
	* i386-tbl.h: Regenerated.
 2008-04-22 22:27:13 +00:00
H.J. Lu
594ab6a333 gas/ 
2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention XSAVE.  Change CLMUL to PCLMUL.

	* config/tc-i386.c (cpu_arch): Add .pclmul.
	(md_show_usage): Replace clmul with pclmul.
	* doc/c-i386.texi: Likewise.

gas/testsuite/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/arch-10.s: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.

	* gas/i386/arch-10.d: Replace clmul with pclmul.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.
 2008-04-04 16:34:23 +00:00
H.J. Lu
c0f3af977b binutils/ 
2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (dwarf_regnames_i386): Add AVX registers.
	(dwarf_regnames_x86_64): Likewise.

gas/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.

	* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
	Document -msse2avx, .avx, .aes, .clmul and .fma.

	* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
	(vex_prefix): Likewise.
	(sse2avx): Likewise.
	(CPU_FLAGS_ARCH_MATCH): Likewise.
	(CPU_FLAGS_64BIT_MATCH): Likewise.
	(CPU_FLAGS_32BIT_MATCH): Likewise.
	(CPU_FLAGS_PERFECT_MATCH): Likewise.
	(regymm): Likewise.
	(vex_imm4): Likewise.
	(fits_in_imm4): Likewise.
	(build_vex_prefix): Likewise.
	(VEX_check_operands): Likewise.
	(bad_implicit_operand): Likewise.
	(OPTION_MSSE2AVX): Likewise.
	(T_YMMWORD): Likewise.
	(_i386_insn): Add vex.
	(cpu_arch): Add .avx, .aes, .clmul and .fma.
	(cpu_flags_match): Changed to take a pointer to const template.
	Enable encoding SSE instructions with VEX prefix for -msse2avx.
	(match_mem_size): Also check ymmword.
	(operand_type_match): Clear ymmword.
	(md_begin): Allow '_' in mnemonic.
	(type_names): Add OPERAND_TYPE_VEX_IMM4.
	(process_immext): Update assert.
	(md_assemble): Don't call process_immext if sse2avx and immext
	are true.  Call build_vex_prefix if vex is true.
	(parse_insn): Updated for cpu_flags_match.
	(swap_operands): Handle 5 operands.
	(match_template): Handle 5 operands. Updated for cpu_flags_match.
	Check regymm.  Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
	(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
	(check_byte_reg): Check regymm.
	(process_operands): Duplicate the destination register for
	-msse2avx if needed.
	(build_modrm_byte): Updated for instructions with VEX encoding.
	(output_insn): Output VEX prefix if needed.
	(md_longopts): Add msse2avx.
	(md_parse_option): Handle OPTION_MSSE2AVX.
	(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
	(intel_e09): Support YMMWORD.
	(intel_e11): Likewise.
	(intel_get_token): Likewise.

gas/testsuite/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
	x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
	x86-64-avx-intel and x86-64-inval-avx.

	* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
	* gas/cfi/cfi-x86_64.s: Likewise.

	* gas/i386/aes.d: New.
	* gas/i386/aes.s: Likewise.
	* gas/i386/aes-intel.d: Likewise.
	* gas/i386/avx.d: Likewise.
	* gas/i386/avx.s: Likewise.
	* gas/i386/avx-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/i386.exp: Likewise.
	* gas/i386/inval-avx.l: Likewise.
	* gas/i386/inval-avx.s: Likewise.
	* gas/i386/sse2avx.d: Likewise.
	* gas/i386/sse2avx.s: Likewise.
	* gas/i386/x86-64-aes.d: Likewise.
	* gas/i386/x86-64-aes.s: Likewise.
	* gas/i386/x86-64-aes-intel.d: Likewise.
	* gas/i386/x86-64-avx.d: Likewise.
	* gas/i386/x86-64-avx.s: Likewise.
	* gas/i386/x86-64-avx-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.
	* gas/i386/x86-64-inval-avx.l: Likewise.
	* gas/i386/x86-64-inval-avx.s: Likewise.
	* gas/i386/x86-64-sse2avx.d: Likewise.
	* gas/i386/x86-64-sse2avx.s: Likewise.

	* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/rexw.s: Add AVX tests.

	* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.

	* gas/cfi/cfi-i386.d: Updated.
	* gas/cfi/cfi-x86_64.d: Likewise.
	* gas/i386/arch-10.d:  Likewise.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/rexw.d: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.

include/opcode/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (MAX_OPERANDS): Set to 5.
	(MAX_MNEM_SIZE): Changed to 20.

opcodes/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2008-04-03 14:03:21 +00:00
H.J. Lu
65da13b5e0 gas/ 
2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (inoutportreg): New.
	(process_immext): New.
	(md_assemble): Use it.
	(update_imm): Use imm16 and imm32s.
	(i386_att_operand): Use inoutportreg.

opcodes/

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.
 2008-02-16 16:16:48 +00:00
Jan Beulich
a60de03c61 gas/ 
2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.c (allow_pseudo_reg): New.
	(parse_real_register): Check for NULL just once. Allow all
	register table entries when allow_pseudo_reg is non-zero.
	Don't allow any registers without type when allow_pseudo_reg
	is zero.
	(tc_x86_regname_to_dw2regnum): Replace with ...
	(tc_x86_parse_to_dw2regnum): ... this.
	(tc_x86_frame_initial_instructions): Adjust for above change.
	* config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
	(tc_parse_to_dw2regnum): New.
	(tc_x86_regname_to_dw2regnum): Replace with ...
	(tc_x86_parse_to_dw2regnum): ... this.
	* dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
	(cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
	error handling.

gas/testsuite/
2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* gas/cfi/cfi-i386.s: Add code testing use of all registers.
	Fix a few comments.
	* gas/cfi/cfi-x86_64.s: Likewise.
	* gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.

opcodes/
2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.
 2008-02-13 10:14:40 +00:00
H.J. Lu
f03fe4c110 gas/ 
2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .xsave.
	(md_show_usage): Add .xsave.

	* doc/c-i386.texi: Add xsave to -march=.

gas/testsuite/

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10.s: Add xgetbv.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-10.d: Likewise.

opcodes/

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.
 2008-02-12 05:35:36 +00:00