When trying to run gdb.trace/tspeed.exp, I get:
ERROR: can't read "ipalib": no such variable
while executing
"gdb_load_shlib $ipalib"
(procedure "prepare_for_trace_test" line 5)
This problem seems to come from commit
c708f4d256 ("gdb: Don't call gdb_load_shlib unless GDB is running")
which moved the gdb_load_shlib call in prepare_for_trace_test. In order
to access the ipalib variable, we need to declare "global ipalib" first.
Then, this test uses nowarnings, for no good reason I could find. We
can remove that and fix the two trivial warnings that appear:
/home/emaisin/src/binutils-gdb/gdb/testsuite/gdb.trace/tspeed.c: In function 'main':
/home/emaisin/src/binutils-gdb/gdb/testsuite/gdb.trace/tspeed.c:87:16: warning: too many arguments for format [-Wformat-extra-args]
printf ("Negative times, giving up\n", max_iters);
^
/home/emaisin/src/binutils-gdb/gdb/testsuite/gdb.trace/tspeed.c:99:7: warning: implicit declaration of function 'sleep' [-Wimplicit-function-declaration]
sleep (1); /* set post-run breakpoint here */
^
gdb/testsuite/ChangeLog:
* gdb.trace/tspeed.exp: Remove nowarnings.
(prepare_for_trace_test): Declare "global ipalib".
* gdb.trace/tspeed.c: Include unistd.h.
(main): Remove superfluous printf argument.
2018-10-11 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* gdb.base/solib-vanish.exp: Fix regexp not to require a POSIX
directory prefix on the filename.
This is the result of an email thread starting here:
https://sourceware.org/ml/binutils/2018-09/msg00031.html
The main point of the thread is this observation:
* Supposing we had an object file with two globals, SomeGlobal and
SomeOtherGlobal, if one were to do "--globalize-symbol SomeGlobal
--keep-global-symbol SomeOtherGlobal", you might expect that both
SomeGlobal and SomeOtherGlobal are global in the output file... but it
isn't. Because --keep-global-symbol is set and doesn't include
SomeGlobal, SomeGlobal will be demoted to a local symbol. And because
the check to see if we should apply the --globalize-symbol flag checks
"flags" (the original flag set), and not "sym->flags", it decides not
to do anything, so SomeGlobal remains a local symbol. Although this is
a weird edge case, should this be changed so that --keep-global-symbol
implicitly keeps anything also specified via --globalize-symbol? (The
code seems technically correct with respect to the documentation, but
IMO the behavior is counter-intuitive).
binutils* objcopy.c (copy_main): Issue a fata error if the
--keep-global-symbol(s) and the --globalize-symbol(s) options are
used together.
* doc/binutils.texi: Document that the two options are
incompatible.
* testsuite/binutils-all/copy-5.d: New test.
* testsuite/binutils-all/objcopy.exp: Run the new test.
This commit fixes a resource leak found by Coverity, where interp's
constructor allocated memory for m_name that interp's destructor did
not free.
gdb/ChangeLog:
* interps.h (interp::m_name): Make private and mutable.
* interps.c (interp::~interp): Free m_name.
This is a follow-up of:
https://sourceware.org/ml/gdb-patches/2018-08/msg00347.html
Instead of going throttle and always enabling our selftests (even in
non-development builds), this patch is a bit more conservative and
introduces a configure option ("--enable-unit-tests") that allows the
user to choose whether she wants unit tests in the build or not. Note
that the current behaviour is retained: if no option is provided, GDB
will have selftests included in a development build, and will *not*
have selftests included in a non-development build.
The rationale for having this option is still the same: due to the
many racy testcases and random failures we see when running the GDB
testsuite, it is unfortunately not possible to perform a full test
when one is building a downstream package. As the Fedora GDB
maintainer and one of the Debian GDB uploaders, I feel like this
situation could be improved by, at least, executing our selftests
after the package has been built.
This patch introduces no regressions to our build.
OK?
gdb/ChangeLog:
2018-10-10 Sergio Durigan Junior <sergiodj@redhat.com>
Simon Marchi <simark@simark.ca>
* README (`configure' options): Add documentation for new
"--enable-unit-tests" option.
* acinclude.m4: Include "selftest.m4".
* configure: Regenerate.
* configure.ac: Use "GDB_AC_SELFTEST".
* maint.c (maintenance_selftest): Update message informing
that selftests have been disabled.
(maintenance_info_selftests): Likewise.
* selftest.m4: New file.
gdb/gdbserver/ChangeLog:
2018-10-10 Sergio Durigan Junior <sergiodj@redhat.com>
Simon Marchi <simark@simark.ca>
* acinclude.m4: Include "../selftest.m4".
* configure: Regenerate.
* configure.ac: Use "GDB_AC_SELFTEST".
* configure.srv: Use "$enable_unittests" instead of
"$development" when checking whether unit tests have been
enabled.
* server.c (captured_main): Update message informing that
selftests have been disabled.
gdb/testsuite/ChangeLog:
2018-10-10 Sergio Durigan Junior <sergiodj@redhat.com>
* gdb.gdb/unittest.exp: Update expected message informing that
selftests have been disabled.
* gdb.server/unittest.exp: Likewise.
squash! Add parameter to allow enabling/disabling selftests via configure
This commit adds a missing va_end found by Coverity.
gdb/ChangeLog:
* remote.c (remote_target::remote_send_printf): Add
missing va_end found by Coverity.
Some versions of _Unwind_RaiseException, e.g. on Fedora 28, use an
indirect jump to return to the exception handler.
This messes up the output of "record function-call-history /c" since the
return is interpreted as cross-function goto. It had been detected by
gdb.btrace/exception.exp.
Add a heuristic for "_Unwind_*" functions to interpret an indirect jump
that ends in one of our caller functions as return to the first instance
of that function in our call stack.
gdb/
* btrace.c (ftrace_update_function): Add indirect jump heuristic.
.PARISC.unwind has 32-bit addresses in both 32-bit ELF and 64-bit ELF.
Well, strictly speaking, the 32-bit "start" and "end" fields are
segment relative offsets. (The 64-bit ABI says so, while the 32-bit
ABI says they are addresses but it appears they are segment relative
offsets in practice. Likely the 32-bit ABI lacks an update.)
* readelf.c (hppa_process_unwind): Don't use eh_addr_size to
calculate number of entries.
(slurp_hppa_unwind_table): Don't use eh_addr_size here either.
This fixes he @pxref in Inferior.architecture to point to the "Frames
In Python" node, as originally intended; somewhat reverting an earlier
build fix. The initial patch had typod the "In".
Tested by "make info".
gdb/doc/ChangeLog
2018-10-09 Tom Tromey <tom@tromey.com>
* python.texi (Inferiors In Python): Link to "Frames In Python",
not "Unwinding Frames in Python".
There have been a few undefined behavior failures reported, and Pedro
suggested that the sanitizer be disabled by default. This patch
implements this.
gdb/ChangeLog
2018-10-09 Tom Tromey <tom@tromey.com>
* configure: Rebuild.
* sanitize.m4 (AM_GDB_UBSAN): Default to no.
* NEWS: Update --enable-ubsan documentation.
gdb/doc/ChangeLog
2018-10-09 Tom Tromey <tom@tromey.com>
* gdb.texinfo (Configure Options): Update --enable-ubsan
documentation.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence a new command line option of "+sb" is added for older
architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_sb): New.
(SB, SB_INSN): New.
(aarch64_opcode_table): Add entry for sb.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "sb" option
for older architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sb.s: New.
* testsuite/gas/aarch64/sb.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
* doc/c-aarch64.texi: Add documentation for the same.
*** include/ChnageLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
(AARCH64_ARCH_V8_5): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
(ARMV8_5, V8_5_INSN): New.
When calling gdb_start_cmd, it's the caller's responsibility to wait for gdb
to return to the prompt. In target_supports_scheduler_locking, that's not the
case, and consequently, target_supports_scheduler_locking fails spuriously.
Fix by using runto_main instead.
Build and reg-tested on x86_64-linux.
2018-10-09 Tom de Vries <tdevries@suse.de>
* lib/gdb.exp (target_supports_scheduler_locking): Replace gdb_start_cmd
with runto_main.
This commit fixes a buffer overrun found by Coverity, where
36 bytes are written into a 24 byte buffer.
gdb/ChangeLog:
* dwarf2read.c (create_dwp_hash_table): Fix buffer overrun
found by Coverity.
Prevents getting an error about dynamic symbols in sections indexed
64K+ when .dynsym is discarded.
* elflink.c (elf_link_output_extsym): Do not place symbols into a
discarded .dynsym.
This removes a couple of unused variables from riscv-fbsd-tdep.c.
This allows a --enable-targets=all build to complete on
x86-64 Fedora 28.
gdb/ChangeLog
2018-10-08 Tom Tromey <tom@tromey.com>
* riscv-fbsd-tdep.c (riscv_fbsd_sigframe_init): Remove unused
variable.
(riscv_fbsd_init_abi): Likewise.
gdb/ChangeLog:
* Makefile.in (ALLDEPFILES): Add riscv-fbsd-nat.c.
* NEWS: Mention new FreeBSD/riscv native configuration.
* configure.host: Add riscv*-*-freebsd*.
* configure.nat: Likewise.
* riscv-fbsd-nat.c: New file.
gdb/doc/ChangeLog:
* gdb.texinfo (Contributors): Add SRI International and University
of Cambridge for FreeBSD/riscv.
Support for collecting and supplying general purpose and floating
point register sets is provided along with signal frame unwinding.
FreeBSD only supports RV64 currently, so while some provision is made
for RV32 in the general-purpose register set, the changes have only
been tested on RV64.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-fbsd-tdep.o.
(HFILES_NO_SRCDIR): Add riscv-fbsd-tdep.h.
(ALLDEPFILES): Add riscv-fbsd-tdep.c.
* NEWS: Mention new FreeBSD/riscv target.
* configure.tgt: Add riscv*-*-freebsd*.
* riscv-fbsd-tdep.c: New file.
* riscv-fbsd-tdep.h: New file.
Currently, signal frame handlers require explicitly coded calls to
trad_frame_set_reg_addr() to describe the location of saved registers
within a signal frame. This change permits the regcache_map_entry
arrays used with regcache::supply_regset and regcache::collect_regset
to be used to describe a block of saved registers given an initial
address for the register block.
Some systems use the same layout for registers in core dump notes,
native register sets with ptrace(), and the register contexts saved in
signal frames. On these systems, a single register map can now be
used to describe the layout of registers in all three places.
If a register map entry's size does not match the native size of a
register, try to match the semantics used by
regcache::transfer_regset. If a register slot is too large, assume
that the register's value is stored in the first N bytes and ignore
the remaning bytes. If the register slot is smaller than the
register, assume the slot holds the low N bytes of the register's
value. Read these low N bytes from the target and zero-extend them to
generate a register value.
While here, document the semantics for both regcache::transfer_regset
and trad_frame with respect to register slot's whose size does not
match the register's size.
gdb/ChangeLog:
* regcache.h (struct regcache_map_entry): Note that this type can
be used with traditional frame caches.
* trad-frame.c (trad_frame_set_reg_regmap): New.
* trad-frame.h (trad_frame_set_reg_regmap): New.
This patch fixes the original problem - printing member in a virtual base,
using various expressions, do not yield the same value. Simple test case
below demonstrates the problem:
% cat t.cc
struct base { int i; };
typedef base tbase;
struct derived: virtual tbase { void func() { } };
int main() { derived().func(); }
% g++ -g t.cc
% gdb a.out
(gdb) break derived::func
(gdb) run
(gdb) p i
$1 = 0
(gdb) p base::i
$3 = 0
(gdb) p derived::i
$4 = 4196392
To fix the problem, add function get_baseclass_offset() which searches
recursively for the base class along the class hierarchy. If the base
is virtual, it uses "vptr" in virtual class object, which indexes to
its derived class's vtable, to get and returns the baseclass offset.
If the base is non-virtual, it returns the accumulated offset of its
parent classes. The offset is then added to the address of the class
object to access its member in value_struct_elt_for_reference().
Clang doesn't accept {0} as a valid C struct initializer under their implementation
of -Wmissing-field-initializers. This makes using C initializers a bit tricky.
Instead I'm changing the code to use memset instead, which at least GCC inlines and
generates the same code for. This also seems to be the idiom used in binutils for
most targets.
opcodes/
* aarch64-opc.c (verify_constraints): Use memset instead of {0}.
With
commit 64029e9368
Author: Alan Modra <amodra@gmail.com>
Date: Fri Oct 5 11:40:54 2018 +0930
Separate header PT_LOAD for -z separate-code
there is no need to add a GNU_PROPERTY_X86_ISA_1_USED note to force
program header in in non-code PT_LOAD segment when -z separate-code
is used.
bfd/
PR ld/23428
* elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Don't
add GNU_PROPERTY_X86_FEATURE_2_NEEDED to force program header
in non-code PT_LOAD segment.
ld/
PR ld/23428
* testsuite/ld-i386/property-x86-4a.d: Updated.
* testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-4a.d: Likewise.
Properly group orphan note sections. When placing orphan note section
as the first note section, place it after the section before all note
sections.
PR ld/23658
* ldlang.c (lang_insert_orphan): Properly group and place orphan
note sections. Properly handle orphan note section before all
note sections.
* testsuite/ld-elf/pr23658-1.d: Renamed to ...
* testsuite/ld-elf/pr23658-1a.d: This. Updated.
* testsuite/ld-elf/pr23658-1b.d: New test.
* testsuite/ld-elf/pr23658-1c.d: Likewise.
This patch, along with previous patches in the series, supports
putting the ELF file header and program headers in a PT_LOAD without
sections.
Logic governing whether headers a loaded has changed a little: The
primary reason to include headers is now the presence of
SIZEOF_HEADERS in a linker script. However, to support scripts that
may have reserved space for headers by hand, we continue to add
headers whenever the first section address is past the end of headers
modulo page size.
include/
* bfdlink.h (struct bfd_link_info): Add load_phdrs field.
bfd/
* elf-nacl.c (nacl_modify_segment_map): Cope with header PT_LOAD
lacking sections.
* elf.c (_bfd_elf_map_sections_to_segments): Assume file and
program headers are required when info->load_phdrs. Reorganize
code handling program headers. Generate a mapping without
sections just for file and program headers when -z separate-code
would indicate they should be on a different page to the first
section.
ld/
* ldexp.c (fold_name <SIZEOF_HEADERS>): Set link_info.load_phdrs.
* testsuite/ld-elf/loadaddr1.d: Pass -z noseparate-code.
* testsuite/ld-elf/loadaddr2.d: Likewise.
* testsuite/ld-i386/vxworks2.sd: Adjust expected output.
* testsuite/ld-powerpc/vxworks2.sd: Likewise.
* testsuite/ld-elf/overlay.d: Remove spu xfail.
* testsuite/ld-spu/ovl.lnk: Don't use SIZEOF_HEADERS.
* testsuite/ld-tic6x/dsbt-be.ld: Likewise.
* testsuite/ld-tic6x/dsbt-inrange.ld: Likewise.
* testsuite/ld-tic6x/dsbt-overflow.ld: Likewise.
* testsuite/ld-tic6x/dsbt.ld: Likewise.
Some time ago the pr19593 test was xfailed for alpha. This turned out
to be the wrong course of action since the test exposed a bug in
orphan section placement. On alpha, orphan sections were being
inserted before ". = SIZEOF_HEADERS" due to the test having two
assignments, and on alpha, an output section statement from
-Ttext-segment being passed to ld.
* ldlang.c (insert_os_after): Clear ignore_first on assignment to
dot, not any assignment. Clear ignore_first on output section
statement contents too.
* testsuite/ld-elf/pr19539.d: Remove alpha xfail.
p_vaddr is currently set from the first section vma if a segment has
sections, and to zero if a segment has no sections. This means we
lose p_vaddr when objcopy'ing executables if a segment without
sections has a non-zero p_vaddr.
This patch saves p_vaddr to p_vaddr_offset, and to make the use of
p_vaddr_offset consistent, inverts the sign. (It's now added to
section vma to get segment vaddr, and added to zero when there are no
sections.)
* elf.c (assign_file_positions_for_load_sections): Set p_vaddr
from m->p_vaddr_offset for segments without sections. Invert
sign of p_vaddr_offset.
(rewrite_elf_program_header, copy_elf_program_header): Save
old segment p_vaddr to p_vaddr_offset. Invert sign of
p_vaddr_offset.
Some targets don't set a default interpreter, resulting in an empty
.interp section unless --dynamic-linker is passed to ld. A PT_INTERP
without a path is rather useless.
The testsuite change fixes a failure on microblaze-linux.
bfd/
* elf.c (get_program_header_size): Don't count PT_INTERP if
.interp is empty.
(_bfd_elf_map_sections_to_segments): Don't create PT_INTERP if
.interp is empty.
ld/
* testsuite/ld-elf/pr22423.d: Pass --dynamic-linker to ld.
Overlay PT_LOAD headers are moved early for reasons explained by
comments in spu_elf_modify_segment_map. This patch fixes cases that
shouldn't occur in sane SPU executables.
* elf32-spu.c (spu_elf_modify_segment_map): Don't insert
overlays before segment containing headers.
This cleans up elf_segment_map allocation when the section array is
empty. "amt += (to - from - 1) * sizeof (asection *)", when "to" and
"from" are unsigned int results in an unsigned value inside the
parentheses. When "to" and "from" are equal on a 64-bit host,
0xffffffff * 8 is added to "amt", not -8 as desired.
The patch also renames a variable for consistency with other functions
using a similar index.
* elf.c (make_mapping): Cope with zero size array at end of
struct elf_segment_map.
(_bfd_elf_map_sections_to_segments): Likewise.
(rewrite_elf_program_header, copy_elf_program_header): Likewise.
(_bfd_elf_map_sections_to_segments): Rename phdr_index to hdr_index.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_cu) <producer_is_codewarrior>: New field.
(check_producer): Check if the producer is codewarrior.
(producer_is_codewarrior): New function.
(lnp_state_machine::record_line): Ignore is_stmt flag for records
produced by codewarrior.
(dwarf2_cu::dwarf2_cu): Initialize producer_is_codewarrior.
