The basic support for LoongArch has been merged into the upstream Linux
kernel since 5.19-rc1 on June 5, 2022. This commit adds orig_a0 which
is added into struct user_pt_regs [1] to match the upstream kernel, and
then the upstream GDB will work with the upstream kernel.
Note that orig_a0 was added into struct user_pt_regs in the development
cycle for merging LoongArch port into the upstream Linux kernel, so
earlier kernels (notably, the product kernel with version 4.19 used in
distros like UOS and Loongnix) don't have it. Inspect
arch/loongarch/include/uapi/asm/ptrace.h in the kernel tree to make sure.
To build upstream GDB for a kernel lacking orig_a0, it's necessary to
revert this commit locally.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h#n24
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Armv8-M architecture with Security extension features four stack pointers
to handle Secure and Non-secure modes.
This patch adds support to switch between them as needed during
unwinding, and replaces all updates of cache->prev_sp with calls to
arm_cache_set_prev_sp.
Signed-off-by: Torbjörn Svensson <torbjorn.svensson@st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
This patch removes the hardcoded access to PSP in
arm_m_exception_cache() and relies on the definition with the XML
descriptions.
Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
1. Since 32bit-pkeys.xml and 64bit-pkeys.xml are identical, consolidate
them into a single keys.xml.
2. Enable PKU for x32 to fix:
$ gdbserver :123456 x32-program
...
.../gdbserver/regcache.cc:255: A problem internal to GDBserver has been detected
.
Unknown register pkru requested
on Tiger Lake.
This commit adds Makefile, configure and NEWS for LoongArch.
Signed-off-by: Zhensong Liu <liuzhensong@loongson.cn>
Signed-off-by: Qing zhang <zhangqing@loongson.cn>
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
This commit adds initial target description support for LoongArch.
Signed-off-by: Zhensong Liu <liuzhensong@loongson.cn>
Signed-off-by: Qing zhang <zhangqing@loongson.cn>
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.
For the avoidance of doubt, all changes in this commits were
performed by the script.
Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:
cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
This patch adds gdbserver support for OpenRISC. This has been used for
debugging the glibc port that in being worked on here:
https://github.com/openrisc/or1k-glibc/tree/or1k-port-2
Hence the comment about registers definitions being inline with glibc.
This adds support for the half datatype, FP16, to the AVX512 register printing.
gdb/ChangeLog:
2020-07-21 Felix Willgerodt <Felix.Willgerodt@intel.com>
* i386-tdep.c (i386_zmm_type) <v32_half>: New field.
(i386_ymm_type) <v16_half>: New field.
(i386_gdbarch_init): Add set_gdbarch_half_format.
* features/i386/64bit-avx512.xml: Add half type.
* features/i386/64bit-avx512.c: Regenerated.
* features/i386/64bit-sse.xml: Add half type.
* features/i386/64bit-sse.c: Regenerated.
gdb/testsuite/ChangeLog:
2021-07-21 Felix Willgerodt <Felix.Willgerodt@intel.com>
* gdb.arch/x86-avx512fp16.c: New file.
* gdb.arch/x86-avx512fp16.exp: New file.
* lib/gdb.exp (skip_avx512fp16_tests): New function.
Values of type bfloat16 can also be used on 32-bit targets, which was missed
in the original enablement. This also adjusts the testcase to pass with
"unix/-m32", where only the lower 8 AVX registers are available.
gdb/ChangeLog:
2021-07-21 Felix Willgerodt <Felix.Willgerodt@intel.com>
* features/i386/32bit-sse.xml: Add bfloat16 type.
* features/i386/32bit-sse.c: Regenerated.
gdb/testsuite/ChangeLog:
2021-07-21 Felix Willgerodt <Felix.Willgerodt@intel.com>
* gdb.arch/x86-avx512bf16.exp: Only use x/z/ymm 0-7.
Clean up some things I noticed:
- we generate a regformats/microblaze-with-stack-protect.dat file. I
don't think this is used. It could be used by a GDBserver built for
Microblaze, but GDBserver isn't ported to Microblaze. So I don't
think that's used at all. Remove the entry in features/Makefile and
the file itself.
- There are a bunch of *-expedite values in features/Makefile for
architectures for which we don't generate dat files. AFAIK, these
*-expedite values are only used when generating dat files. Remove
those that are not necessary.
- 32bit-segments.xml is not listed in the Makfile, but it's used. This
means that it wouldn't get re-generated if we were to change how C
files are generated from the XML. It looks like it was simply
forgotten, add it.
Change-Id: I112d00db317102270e1df924473c37122ccb6c3a
This patch adds a target description and feature "mte" for aarch64.
It includes one new register, tag_ctl, that can be used to configure the
tag generation rules and sync/async modes. It is 64-bit in size.
The patch also adjusts the code that creates the target descriptions at
runtime based on CPU feature checks.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Take MTE flag into
account.
Slight refactor to hwcap flag checking.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for
MTE.
(aarch64_read_description): Add mte_p parameter and update to use it.
Update the documentation.
(aarch64_gdbarch_init): Update call to aarch64_read_description.
* aarch64-tdep.h (aarch64_read_description): Add mte_p parameter.
* arch/aarch64.c: Include ../features/aarch64-mte.c.
(aarch64_create_target_description): Add mte_p parameter and update
the code to use it.
* arch/aarch64.h (aarch64_create_target_description): Add mte_p
parameter.
* features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml.
* features/aarch64-mte.c: New file, generated.
* features/aarch64-mte.xml: New file.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to
aarch64_linux_read_description.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag
into account.
* linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension
for MTE.
(aarch64_linux_read_description): Add mte_p parameter and update to
use it.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p
parameter.
This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
This commit started as adding rv32e support to gdb. The rv32e
architecture is a cut-down rv32i, it only has 16 x-registers compared
to the usual 32, and an rv32e target should not have any floating
point registers.
In order to add this I needed to adjust the target description
validation checks that are performed from riscv_gdbarch_init, and I
finally got fed up with the current scheme of doing these checks and
rewrote this code.
Unfortunately the rv32e changes are currently mixed in with the
rewrite of the validation scheme. I could split these apart if anyone
is really interested in seeing these two ideas as separate patches.
The main idea behind this change is that where previously I tried to
have a purely data driven approach, a set of tables one for each
expected feature, and then a single generic function that would
validate a feature given a table, I have created a new class for each
feature. Each class has its own check member function which allows
the logic for how to check each feature to be different. I think the
new scheme is much easier to follow.
There are some other changes that I made to the validation code as
part of this commit.
I've relaxed some of the checks related to the floating point CSRs.
Previously the 3 CSRs fflags, frm, and fcsr all had to be present in
either the fpu feature or the csr feature. This requirement is now
relaxed, if the CSRs are not present then gdb will not reject the
target description. My thinking here is that there's no gdb
functionality that specifically requires these registers, and so, if a
target offers a description without these registers nothing else in
gdb should stop working.
And as part of the rv32e support targets now only have to provide the
first 16 x-registers and $pc. The second half of the x-registers (x16
-> x31) are now optional.
gdb/ChangeLog:
* arch/riscv.c: Include 'rv32e-xregs.c'.
(riscv_create_target_description): Update to handle rv32e.
* arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New
member variable.
<operator==>: Update to account for new field.
<hash>: Likewise.
* features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml.
* features/riscv/rv32e-xregs.c: Generated.
* features/riscv/rv32e-xregs.xml: New file.
* riscv-tdep.c (riscv_debug_breakpoints): Move from later in the
file.
(riscv_debug_infcall): Likewise.
(riscv_debug_unwinder): Likewise.
(riscv_debug_gdbarch): Likewise.
(enum riscv_register_required_status): Delete.
(struct riscv_register_feature): Add constructor, delete default
constructor, copy, and assign constructors.
(struct riscv_register_feature::register_info) <required>: Delete.
<check>: Update comment and arguments.
(struct riscv_register_feature) <name>: Change to member function.
<prefer_first_name>: Delete.
<tdesc_feature>: New member function.
<registers>: Rename to...
<m_registers>: ...this.
<m_feature_name>: New member variable.
(riscv_register_feature::register_info::check): Update arguments.
(riscv_xreg_feature): Rewrite as class, create a single static
instance of the class.
(riscv_freg_feature): Likewise.
(riscv_virtual_feature): Likewise.
(riscv_csr_feature): Likewise.
(riscv_create_csr_aliases): Has become a member function inside
riscv_csr_feature class.
(riscv_abi_embedded): New function definition.
(riscv_register_name): Adjust to use new feature objects.
(struct riscv_call_info) <riscv_call_info>: Check for rv32e abi,
and adjust available argument registers.
(riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag.
(riscv_check_tdesc_feature): Delete.
(riscv_tdesc_unknown_reg): Adjust to use new feature objects.
(riscv_gdbarch_init): Delete target description checking code, and
instead call to the new feature objects to perform the checks.
Reorder handling of no abi information case, allows small code
simplification.
(_initialize_riscv_tdep): Remove call, this is now done in the
riscv_csr_feature constructor.
* riscv-tdep.h (riscv_abi_embedded): Declare.
This patch updates FPCR (Floating-point Control Register) and FPSR
(Floating-point Status Register) named fields in AArch64. For detailed
description of named register FPCR and FPSR bit fields see [1] and [2].
Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
FPCR are defined starting from Armv8.7 architecture.
[1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
[2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr
Example:
>>> info all-registers fpsr
fpsr 0x10 [ IXC ]
>>> info all-registers fpcr
fpcr 0x0 [ RMode=0 ]
GDB has two approaches to generating the target descriptions found in
gdb/features/, the whole description approach, where the XML file
contains a complete target description which is then used to generate
a single C file that builds that target description. Or, the split
feature approach, where the XML files contain a single target feature,
each feature results in a single C file to create that one feature,
and then a manually written C file is used to build a complete target
description from individual features.
There's a Makefile, gdb/features/Makefile, which is responsible for
managing the regeneration of the C files from the XML files.
However, some of the logic that selects between the whole description
approach, or the split feature approach, is actually hard-coded into
GDB, inside target-descriptions.c:maint_print_c_tdesc_cmd we check the
path to the incoming XML file and use this to choose which type of C
file we should generate.
This commit removes this hard coding from GDB, and makes the Makefile
entirely responsible for choosing the approach. This makes sense as
the Makefile already has the XML files partitioned based on which
approach they should use.
In order to allow this change the 'maint print c-tdesc' command is
given a new command option '-single-feature', which tells GDB which
type of C file should be created. The makefile now supplies this flag
to GDB.
This did reveal a bug in features/Makefile, the rx.xml file was in the
wrong list, this didn't matter previously as the actual choice of
which approach to use was done in GDB. Now the Makefile decides, so
placing each XML file in the correct list is critical.
Tested this by doing 'make GDB=/path/to/gdb clean-cfiles cfiles' to
regenerate all the C files from their XML source. There are no
changes after this commit.
gdb/ChangeLog:
* features/Makefile (XMLTOC): Add rx.xml.
(FEATURE_XMLFILES): Remove rx.xml.
(FEATURE_CFILES rule): Pass '-single-feature' flag.
* features/rx.c: Regenerate.
* features/rx.xml: Wrap in `target` tags, and reindent.
* target-descriptions.c (struct maint_print_c_tdesc_options): New
structure.
(maint_print_c_tdesc_opt_def): New typedef.
(maint_print_c_tdesc_opt_defs): New static global.
(make_maint_print_c_tdesc_options_def_group): New function.
(maint_print_c_tdesc_cmd): Make use of command line flags, only
print single feature C file for target descriptions containing a
single feature.
(maint_print_c_tdesc_cmd_completer): New function.
(_initialize_target_descriptions): Update call to register command
completer, and include command line flag in help text.
gdb/doc/ChangeLog:
* gdb.texinfo (Maintenance Commands): Update description of 'maint
print c-tdesc'.
This adds support for the bfloat16 datatype, which can be seen as a short
version of FP32, skipping the least significant 16 bits of the mantissa.
Since the datatype is currently only supported by the AVX512 registers,
the printing of bfloat16 values is only supported for xmm, ymm and zmm
registers.
gdb/ChangeLog:
2020-09-11 Moritz Riesterer <moritz.riesterer@intel.com>
Felix Willgerodt <Felix.Willgerodt@intel.com>
* gdbarch.sh: Added bfloat16 type.
* gdbarch.c: Regenerated.
* gdbarch.h: Regenerated.
* gdbtypes.c (floatformats_bfloat16): New struct.
(gdbtypes_post_init): Add builtin_bfloat16.
* gdbtypes.h (struct builtin_type) <builtin_bfloat16>: New member.
(floatformats_bfloat16): New struct.
* i386-tdep.c (i386_zmm_type): Add field "v32_bfloat16"
(i386_ymm_type): Add field "v16_bfloat16"
(i386_gdbarch_init): Add set_gdbarch_bfloat16_format.
* target-descriptions.c (make_gdb_type): Add case TDESC_TYPE_BFLOAT16.
* gdbsupport/tdesc.cc (tdesc_predefined_types): New member bfloat16.
* gdbsupport/tdesc.h (tdesc_type_kind): New member TDESC_TYPE_BFLOAT16.
* features/i386/64bit-avx512.xml: Add bfloat16 type.
* features/i386/64bit-avx512.c: Regenerated.
* features/i386/64bit-sse.xml: Add bfloat16 type.
* features/i386/64bit-sse.c: Regenerated.
gdb/testsuite/ChangeLog:
2020-09-11 Moritz Riesterer <moritz.riesterer@intel.com>
Felix Willgerodt <Felix.Willgerodt@intel.com>
* x86-avx512bf16.c: New file.
* x86-avx512bf16.exp: Likewise.
* lib/gdb.exp (skip_avx512bf16_tests): New function.
A few changes have been made to make the register support simpler,
more flexible and extendible. The trigger for most of these changes
are the remarks [1] made earlier for v2 of this patch. The noticeable
improvements are:
- The arc XML target features are placed under gdb/features/arc
- There are two cores (based on ISA) and one auxiliary feature:
v1-core: ARC600, ARC601, ARC700
v2-core: ARC EM, ARC HS
aux: common in both
- The XML target features represent a minimalistic sane set of
registers irrespective of application (baremetal or linux).
- A concept of "feature" class has been introduced in the code.
The "feature" object is constructed from BFD and GDBARCH data.
It contains necessary information (ISA and register size) to
determine which XML target feature to use.
- A new structure (ARC_REGISTER_FEATURE) is added that allows
providing index, names, and the necessity of registers. This
simplifies the sanity checks and future extendibility.
- Documnetation has been updated to reflect ARC features better.
- Although the feature names has changed, there still exists
backward compatibility with older names through
find_obsolete_[core,aux]_names() functions.
The last two points were inspired from RiscV port.
[1]
https://sourceware.org/pipermail/gdb-patches/2020-May/168511.html
gdb/ChangeLog:
* arch/arc.h
(arc_gdbarch_features): New class to stir the selection of target XML.
(arc_create_target_description): Use FEATURES to choose XML target.
(arc_lookup_target_description): Use arc_create_target_description
to create _new_ target descriptions or return the already created
ones if the FEATURES is the same.
* arch/arc.c: Implementation of prototypes described above.
* gdb/arc-tdep.h (arc_regnum enum): Add more registers.
(arc_gdbarch_features_init): Initialize the FEATURES struct.
* arc-tdep.c (*_feature_name): Make feature names consistent.
(arc_register_feature): A new struct to hold information about
registers of a particular target/feature.
(arc_check_tdesc_feature): Check if XML provides registers in
compliance with ARC_REGISTER_FEATURE structs.
(arc_update_acc_reg_names): Add aliases for r58 and r59.
(determine_*_reg_feature_set): Which feature name to look for.
(arc_gdbarch_features_init): Given MACH and ABFD, initialize FEATURES.
(mach_type_to_arc_isa): Convert from a set of binutils machine types
to expected ISA enums to be used in arc_gdbarch_features structs.
* features/Makefile (FEATURE_XMLFILES): Add new files.
* gdb/features/arc/v1-aux.c: New file.
* gdb/features/arc/v1-aux.xml: Likewise.
* gdb/features/arc/v1-core.c: Likewise.
* gdb/features/arc/v1-core.xml: Likewise.
* gdb/features/arc/v2-aux.c: Likewise.
* gdb/features/arc/v2-aux.xml: Likewise.
* gdb/features/arc/v2-core.c: Likewise.
* gdb/features/arc/v2-core.xml: Likewise.
* NEWS (Changes since GDB 9): Announce obsolence of old feature names.
gdb/doc/ChangeLog:
* gdb.texinfo (Synopsys ARC): Update the documentation for ARC
Features.
gdb/testsuite/ChangeLog:
* gdb.arch/arc-tdesc-cpu.xml: Use new feature names.
There is currently a bug in the RISC-V CSR/FPU feature files. The
CSRs containing the FPU status registers are mentioned in both the FPU
feature file and the CSR feature file.
My original thinking when adding the FPU feature file was that it made
more sense to group the FPU status registers with the other FPU
state. This opened up the possibility of debugging very
simple (possibly simulator only) targets that had little more than CPU
and FPU available for GDB to access.
When I then added code to automatically generate the CSR XML file I
forgot to filter out the FPU status CSRs, so these registers were
mentioned twice.
Now for GDB's default RISC-V target descriptions this doesn't actually
matter. I did consider adding the CSRs to the default target
description, but in the end I didn't bother. The reasoning again was
simplicity; the default target description is only to be used when the
target doesn't supply its own description, and NOT supplying the CSRs
actually serves to encourage targets to supply an accurate
description. Combine this with the fact that the CSRs change from
revision to revision, sometimes in non-backward compatible ways, then
having a "default" set of CSRs just feels like a path to confusion and
complaints.
However, having a broken CSR XML file in the GDB source tree has had
one negative effect, QEMU has copied this file into its source tree,
and is using this as its description that it passes to GDB. That is
QEMU announces the FPU status registers twice, once in the FPU
feature, and once in the CSR feature.
This commit starts along the path back to sanity by deleting the
default CSR XML files from within GDB. These files were not used in
any way by current GDB, so there is absolutely no loss of
functionality with this change.
gdb/ChangeLog:
* features/Makefile: Remove all references to the deleted files
below.
* features/riscv/32bit-csr.c: Deleted.
* features/riscv/32bit-csr.xml: Deleted.
* features/riscv/64bit-csr.c: Deleted.
* features/riscv/64bit-csr.xml: Deleted.
* features/riscv/rebuild-csr-xml.sh: Deleted.
This patch removes the leftover regformats .dat files for the arm
architecture. There are no longer relevant, since the arm architecture
has been converted to use feature-based target-descriptions. These .dat
files are used by GDBserver ports that still use static target
descriptions.
These .dat files are generated from corresponding .xml files in the
features directory. And since the corresponding .xml files for these
arm .dat files don't exist anymore, it is impossible to re-generated
them. If you delete these .dat files and type "make" in the features
directory, you'll get:
make: *** No rule to make target '../regformats/arm/arm-with-iwmmxt.dat', needed by 'all'. Stop.
So it removes the entries in the `WHICH` variable of
gdb/features/Makefile.
Finally, it removes the rule in gdbserver/Makefile to generate .cc files
from `../gdb/regformats/arm/%.dat`.
gdb/ChangeLog:
* features/Makefile (WHICH): Remove arm files.
* regformats/arm/arm-with-iwmmxt.dat: Remove.
* regformats/arm/arm-with-neon.dat: Remove.
* regformats/arm/arm-with-vfpv2.dat: Remove.
* regformats/arm/arm-with-vfpv3.dat: Remove.
gdbserver/ChangeLog:
* Makefile.in (%-generated.cc: ../gdb/regformats/arm/%.dat):
Remove.
Change-Id: I3b7d989c50e2cb92235c1f7c7071a26839d84c78
When trying to run `make` in the features directory, in a clean repo, we
get:
Makefile:254: warning: overriding recipe for target 'rx.c'
Makefile:250: warning: ignoring old recipe for target 'rx.c'
make: Nothing to be done for 'all'.
The warnings come from the fact that `rx.xml` is present in two lists,
causing two `rx.c` targets to be defined. It is ok for it to be in the
FEATURES_XMLFILES list, as this architecture uses the "feature-based"
target-descriptions. It shouldn't be in the XMLTOC list, as this is for
architectures that define complete/static target descriptions as XML
files.
gdb/ChangeLog:
* features/Makefile (XMLTOC): Remove rx.xml.
Change-Id: Iada4ab54b3d4542588fac543d16ee35a92537319
We add new arguments defined and aborted verisons for DECLARE_CSR to
support privileged versions controling in binutils. Therefore, the
rebuild-csr-xml.sh should be updated, too.
gdb/
* features/riscv/rebuild-csr-xml.sh: Updated.
This patch replaces usage of target descriptions in ARC, where the whole
description is fixed in XML, with new target descriptions where XML describes
individual features, and GDB assembles those features into actual target
description.
v2:
Removed arc.c from ALLDEPFILES in gdb/Makefile.in.
Removed vim modeline from arc-tdep.c to have it in a separate patch.
Removed braces from one line "if/else".
Undid the type change for "jb_pc" (kept it as "int").
Joined the unnecessary line breaks into one line.
No more moving around arm targets in gdb/features/Makefile.
Changed pattern checking for ARC features from "arc/{aux,core}" to "arc/".
v3:
Added include gaurds to arc.h.
Added arc_read_description to _create_ target descriptions less.
v4:
Got rid of ARC_SYS_TYPE_NONE.
Renamed ARC_SYS_TYPE_INVALID to ARC_SYS_TYPE_NUM.
Fixed a few indentations/curly braces.
Converted arc_sys_type_to_str from a macro to an inline function.
gdb/ChangeLog:
2020-03-16 Anton Kolesov <anton.kolesov@synopsys.com>
Shahab Vahedi <shahab@synopsys.com>
* Makefile.in: Add arch/arc.o
* configure.tgt: Likewise.
* arc-tdep.c (arc_tdesc_init): Use arc_read_description.
(_initialize_arc_tdep): Don't initialize old target descriptions.
(arc_read_description): New function to cache target descriptions.
* arc-tdep.h (arc_read_description): Add proto type.
* arch/arc.c: New file.
* arch/arc.h: Likewise.
* features/Makefile: Replace old target descriptions with new.
* features/arc-arcompact.c: Remove.
* features/arc-arcompact.xml: Likewise.
* features/arc-v2.c: Likewise
* features/arc-v2.xml: Likewise
* features/arc/aux-arcompact.xml: New file.
* features/arc/aux-v2.xml: Likewise.
* features/arc/core-arcompact.xml: Likewise.
* features/arc/core-v2.xml: Likewise.
* features/arc/aux-arcompact.c: Generate.
* features/arc/aux-v2.c: Likewise.
* features/arc/core-arcompact.c: Likewise.
* features/arc/core-v2.c: Likewise.
* target-descriptions (maint_print_c_tdesc_cmd): Support ARC features.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information. We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option. Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(struct riscv_csr_extra): New structure to hold all extra information
of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the csr_extra_hash.
(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
not a boolean. This is same as riscv_init_csr_hash, so keep the
consistent usage.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
xml-builtin.c only has character arrays and no dependencies, so this
creates a simple header file for that purpose so that gdbserver
can include that instead of re-declaring xml_builtin.
Despite the name, feature_to_c.sh is already specific to xml_builtins
(it hardcodes the variable name), so making it always output the
include for xml-builtin.h seems fine.
gdb/ChangeLog:
2019-10-16 Christian Biesinger <cbiesinger@google.com>
* Makefile.in: Add xml-builtin.h.
* features/feature_to_c.sh: Add an include for xml-builtin.h
to ensure that the compiler checks that the types match.
* xml-builtin.h: New file.
* xml-support.c (fetch_xml_builtin): Add missing const.
* xml-support.h: Remove declaration of xml_builtins.
gdb/gdbserver/ChangeLog:
2019-10-16 Christian Biesinger <cbiesinger@google.com>
* server.c: Include xml-builtin.h.
(get_xml_features): Don't declare xml_builtins here.
Change-Id: I806ef0851c43ead90b545a11794e41f5e5178436
Remove the xml tests. Now that it has been proven the new descriptions
are identical, there is no need to keep testing that. Also, it would
prevent the old xml files from being removed.
Remove the old xml files from gdbserver and delete them.
gdb/ChangeLog:
* arm-tdep.c (_initialize_arm_tdep): Remove xml tests.
* features/arm/arm-with-iwmmxt.c: Remove.
* features/arm/arm-with-iwmmxt.xml: Remove.
* features/arm/arm-with-m-fpa-layout.c: Remove.
* features/arm/arm-with-m-fpa-layout.xml: Remove.
* features/arm/arm-with-m-vfp-d16.c: Remove.
* features/arm/arm-with-m-vfp-d16.xml: Remove.
* features/arm/arm-with-m.c: Remove.
* features/arm/arm-with-m.xml: Remove.
* features/arm/arm-with-neon.c: Remove.
* features/arm/arm-with-neon.xml: Remove.
* features/arm/arm-with-vfpv2.c: Remove.
* features/arm/arm-with-vfpv2.xml: Remove.
* features/arm/arm-with-vfpv3.c: Remove.
* features/arm/arm-with-vfpv3.xml: Remove.
gdb/gdbserver/ChangeLog:
2019-07-05 Alan Hayward <alan.hayward@arm.com>
* configure.srv: Remove Arm xml files.
Add Arm to the list of feature target description targets and generate the
relevant C files.
Add arm-m-profile-with-fpa.xml as the feature version of the exisiting
arm-with-m-fpa-layout.xml.
Add extra comments to the Makefile for readability.
New files are not yet used.
gdb/ChangeLog:
* features/Makefile: Use feature target descriptions for Arm.
* features/arm/arm-core.c: Generate new file.
* features/arm/arm-fpa.c: Likewise.
* features/arm/arm-m-profile-with-fpa.xml: Likewise.
* features/arm/arm-m-profile.c: Likewise.
* features/arm/arm-vfpv2.c: Likewise.
* features/arm/arm-vfpv3.c: Likewise.
* features/arm/xscale-iwmmxt.c: Likewise.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add Arm.
Add all the CPSR flags for Armv8.1-A through to Armv8.4-A.
In addition, document all the existing flags, and remove
the superfluous empty spaces.
gdb/ChangeLog:
* features/aarch64-core.c (create_feature_aarch64_core):
Regenerate.
* features/aarch64-core.xml: Add cpsr flags.
SVE can view Z registers as 128bit values using .q prefix.
Add this view to the SVE feature.
gdb/ChangeLog:
* features/aarch64-sve.c (create_feature_aarch64_sve): Add q view.
Pointer Authentication is a new feature in AArch64 v8.3-a. When enabled in
the compiler, function return addresses will be mangled by the kernel.
Add register description xml and wire up to aarch64_linux_read_description.
This description includes the two pauth user registers.
Nothing yet uses the feature - that is added in later patches.
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Add pauth param.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (struct target_desc): Add in pauth.
(aarch64_read_description): Add pauth param.
(aarch64_gdbarch_init): Likewise.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/Makefile: Add new files.
* features/aarch64-pauth.c: New file.
* features/aarch64-pauth.xml: New file.
gdb/doc/ChangeLog:
* gdb.texinfo: Describe pauth feature.
gdb/gdbserver/ChangeLog:
* linux-aarch64-ipa.c (get_ipa_tdesc): Add pauth param.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.c (aarch64_arch_setup): Likewise.
* linux-aarch64-tdesc-selftest.c (aarch64_tdesc_test): Likewise.
* linux-aarch64-tdesc.c (struct target_desc): Likewise.
(aarch64_linux_read_description): Likewise.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Likewise.
As on amd64, these registers hold the base address of the fs and gs
segments, respectively. For i386 these two registers are 32 bits.
gdb/ChangeLog:
* amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description):
Update calls to i386_target_description to add 'segments'
parameter.
* amd64-tdep.c (amd64_init_abi): Set tdep->fsbase_regnum. Don't
add segment base registers.
* arch/i386.c (i386_create_target_description): Add 'segments'
parameter to enable segment base registers.
* arch/i386.h (i386_create_target_description): Likewise.
* features/i386/32bit-segments.xml: New file.
* features/i386/32bit-segments.c: Generate.
* i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Update
call to i386_target_description to add 'segments' parameter.
* i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise.
* i386-go32-tdep.c (i386_go32_init_abi): Likewise.
* i386-linux-tdep.c (i386_linux_read_description): Likewise.
* i386-tdep.c (i386_validate_tdesc_p): Add segment base registers
if feature is present.
(i386_gdbarch_init): Pass I386_NUM_REGS to set_gdbarch_num_regs.
Add 'segments' parameter to call to i386_target_description.
(i386_target_description): Add 'segments' parameter to enable
segment base registers.
(_initialize_i386_tdep) [GDB_SELF_TEST]: Add 'segments' parameter
to call to i386_target_description.
* i386-tdep.h (struct gdbarch_tdep): Add 'fsbase_regnum'.
(enum i386_regnum): Add I386_FSBASE_REGNUM and I386_GSBASE_REGNUM.
Define I386_NUM_REGS.
(i386_target_description): Add 'segments' parameter to enable
segment base registers.
gdb/gdbserver/ChangeLog:
* linux-x86-tdesc.c (i386_linux_read_description): Update call to
i386_create_target_description for 'segments' parameter.
* lynx-i386-low.c (lynx_i386_arch_setup): Likewise.
* nto-x86-low.c (nto_x86_arch_setup): Likewise.
* win32-i386-low.c (i386_arch_setup): Likewise.
When the target description support was added to RISC-V, the register
numbers assigned to the fflags, frm, and fcsr control registers in the
default target descriptions didn't match the register numbers used by
GDB before the target description support was added.
What this means is that if a tools exists in the wild that is using
hard-coded register number, setup to match GDB's old numbering, then
this will have been broken (for fflags, frm, and fcsr) by the move to
target descriptions. QEMU is such a tool.
There are a couple of solutions that could be used to work around this
issue:
- The user can create their own xml description file with the
register numbers setup to match their old tool, then load this by
telling GDB 'set tdesc filename FILENAME'.
- Update their old tool to use the newer default numbering scheme, or
better yet add proper target description support to their tool.
- We could have RISC-V GDB change to maintain the old defaults.
This patch changes GDB back to using the old numbering scheme.
This change is only visible to remote targets that don't supply their
own xml description file and instead rely on GDB's default numbering.
Note that even though 32bit-cpu.xml and 64bit-cpu.xml have changed,
the corresponding .c file has not, this is because the numbering added
to the registers in the xml files is number 0, this doesn't result in
any new C code being generated .
gdb/ChangeLog:
* features/riscv/32bit-cpu.xml: Add register numbers.
* features/riscv/32bit-fpu.c: Regenerate.
* features/riscv/32bit-fpu.xml: Add register numbers.
* features/riscv/64bit-cpu.xml: Add register numbers.
* features/riscv/64bit-fpu.c: Regenerate.
* features/riscv/64bit-fpu.xml: Add register numbers.
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
