Break i386-dis-evex.h into small files such that each file is included
just once.
* i386-dis-evex.h: Break into ...
* i386-dis-evex-len.h: New file.
* i386-dis-evex-mod.h: Likewise.
* i386-dis-evex-prefix.h: Likewise.
* i386-dis-evex-reg.h: Likewise.
* i386-dis-evex-w.h: Likewise.
* i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
i386-dis-evex-mod.h.
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are
all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv
when disassembling VEX and EVEX instructions.
gas/
PR binutils/24626
* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
and EVEX.vvvv.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24626
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
EVEX.vvvv when disassembling VEX and EVEX instructions.
(OP_VEX): Set vex.register_specifier to 0 after readding
vex.register_specifier.
(OP_Vex_2src_1): Likewise.
(OP_Vex_2src_2): Likewise.
(OP_LWP_E): Likewise.
(OP_EX_Vex): Don't check vex.register_specifier.
(OP_XMM_Vex): Likewise.
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.
gas/
PR gas/24625
* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
instructions with invalid broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
opcodes/
PR gas/24625
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
Disp8ShiftVL.
* i386-tbl.h: Regenerated.
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
This patch adds support for the Linux kernel eBPF architecture to the
opcodes. The port is based on CGEN.
opcodes/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
* configure: Regenerated.
* Makefile.am: Add rules for the files generated from cpu/bpf.cpu
and cpu/bpf.opc.
(HFILES): Add bpf-desc.h and bpf-opc.h.
(TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
bpf-ibld.c and bpf-opc.c.
(BPF_DEPS): Define.
* Makefile.in: Regenerated.
* disassemble.c (ARCH_bpf): Define.
(disassembler): Add case for bfd_arch_bpf.
(disassemble_init_for_target): Likewise.
(enum epbf_isa_attr): Define.
* disassemble.h: extern print_insn_bpf.
* bpf-asm.c: Generated.
* bpf-opc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-ibld.c: Likewise.
* bpf-dis.c: Likewise.
* bpf-desc.h: Likewise.
* bpf-desc.c: Likewise.
This patch makes changes to the <spec_reg> operand for VMRS and VMSR
instructions as per the Armv8.1-M Mainline.
New <spec_reg> options to support are:
0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags.
0b1100: VPR, privileged only access to the VPR register.
0b1101: P0, access to VPR.P0 predicate fields
0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating
point context.
0b1111: FPCXT_S, enables saving and restoring of Secure floating point
context
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
The MIPS64R6 TRM requires that the source register for DAUI
not be r0.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 67-68.
gas/
* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.s: this and add test
case for DAUI.
* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.l: this and add test
for DAUI.
* testsuite/gas/mips/mips.exp: Rename test from
r6-branch-constraints to r6-reg-constraints.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Change source register
constraint for DAUI.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (thumb32_opcodes): Add new instructions.
(print_insn_thumb32): Handle new instructions.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_unpredictable): Likewise.
(mve_opcodes): Add new instructions.
(print_mve_unpredictable): Handle new reasons.
(print_mve_register_blocks): New print function.
(print_mve_size): Handle new instructions.
(print_insn_mve): Likewise.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new values.
(mve_opcodes): Add new instructions.
(vec_condnames): New array with vector conditions.
(mve_predicatenames): New array with predicate suffixes.
(mve_vec_sizename): New array with vector sizes.
(enum vpt_pred_state): New enum with vector predication states.
(struct vpt_block): New struct type for vpt blocks.
(vpt_block_state): Global struct to keep track of state.
(mve_extract_pred_mask): New helper function.
(num_instructions_vpt_block): Likewise.
(mark_outside_vpt_block): Likewise.
(mark_inside_vpt_block): Likewise.
(invert_next_predicate_state): Likewise.
(update_next_predicate_state): Likewise.
(update_vpt_block_state): Likewise.
(is_vpt_instruction): Likewise.
(is_mve_encoding_conflict): Add entries for new instructions.
(is_mve_unpredictable): Likewise.
(print_mve_unpredictable): Handle new cases.
(print_instruction_predicate): Likewise.
(print_mve_size): New function.
(print_vec_condition): New function.
(print_insn_mve): Handle vpt blocks and new print operands.
opcodes/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
8, 14 and 15 for Armv8.1-M Mainline.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
This patch adds all the SVE2 instructions and their associated qualifier
sets.
Ok for trunk?
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
(OP_SVE_BBB): New variant set.
(OP_SVE_DDDD): New variant set.
(OP_SVE_HHH): New variant set.
(OP_SVE_HHHU): New variant set.
(OP_SVE_SSS): New variant set.
(OP_SVE_SSSU): New variant set.
(OP_SVE_SHH): New variant set.
(OP_SVE_SBBU): New variant set.
(OP_SVE_DSS): New variant set.
(OP_SVE_DHHU): New variant set.
(OP_SVE_VMV_HSD_BHS): New variant set.
(OP_SVE_VVU_HSD_BHS): New variant set.
(OP_SVE_VVVU_SD_BH): New variant set.
(OP_SVE_VVVU_BHSD): New variant set.
(OP_SVE_VVV_QHD_DBS): New variant set.
(OP_SVE_VVV_HSD_BHS): New variant set.
(OP_SVE_VVV_HSD_BHS2): New variant set.
(OP_SVE_VVV_BHS_HSD): New variant set.
(OP_SVE_VV_BHS_HSD): New variant set.
(OP_SVE_VVV_SD): New variant set.
(OP_SVE_VVU_BHS_HSD): New variant set.
(OP_SVE_VZVV_SD): New variant set.
(OP_SVE_VZVV_BH): New variant set.
(OP_SVE_VZV_SD): New variant set.
(aarch64_opcode_table): Add sve2 instructions.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
