Commit Graph

118883 Commits

Author SHA1 Message Date
Johan Sternerup
61e608693b DAP: Handle "stepOut" request in outermost frame
Previously a "stepOut" request when in the outermost frame would result
in a sucessful response even though gdb internally would reject the
associated "finish" request, which means no stoppedEvent would ever be
sent back to the client. Thus the client would believe the inferior was
still running and as a consequence reject subsequent "next" and "stepIn"
requests from the user.

The solution is to execute the underlying finish command as a background
command, i.e. `finish &`. If we're in the outermost frame an exception
will be raised immediately, which we can now capture and report back to
the client as success=False so then the absence of a `stopped` event is
no longer a problem.

We also make use of the `defer_stop_event` option to prevent a stop
event from reaching the client until the response has been sent.

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-06 10:25:19 -06:00
Johan Sternerup
42dc1b7f62 DAP: Allow gdb exception in exec_and_log to propagate
This allows a request to specify that any gdb exception raised in
exec_and_log within the gdb thread to be propagated back to the DAP
thread (using the Canceller object as the orchestrator).

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-06 10:25:19 -06:00
Johan Sternerup
584dc32c59 DAP: Allow for deferring stop events from gdb thread
The existing `send_event_later()` method allows commands processed on
the DAP thread to queue an event for execution until after the response
has been sent to the client.

We now introduce a corresponding method for use by the gdb thread. This
method `send_event_maybe_later()` will queue the event just like
`send_event_later()`, but only if it has been configured to do so by a
new @request option `defer_stop_events`. As the name implies the
functionality is currently only used for handling stop events.

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-06 10:25:19 -06:00
Richard Earnshaw
01469ac03e arm: fix testsuite fallout on arm-elf and arm-nto from FPA removal
Removing FPA means that in some cases we default to 'no-fpu' in the
assembler when previously we would have picked FPA-format floating
numbers.  This patch fixes the testsuite fallout on a couple of
targets that are affected by this change.  Where possible we do this
by adding an option to set the floating-point format, but for bad-bss
we just skip the test.
2024-06-06 15:55:16 +01:00
Nick Clifton
6ba0721931 Updated Spanish translation for the bfd/ directory 2024-06-06 12:10:29 +01:00
Andrew Burgess
5ccd31931e opcodes/riscv: prevent future use of disassemble_info::fprintf_func
The previous commit removed a use of disassemble_info::fprintf_func
which had been added to the RISC-V disassembler after the disassembler
had been switched to use ::fprintf_styled_func, for styled output.

To prevent future mistakes, I propose adding a #define to rename
fprintf_func to something which does not exist.  If this had been in
place then the before the previous commit libopcodes would have failed
to compile, like this:

  ../../src/opcodes/riscv-dis.c: In function ‘print_reg_list’:
  ../../src/opcodes/riscv-dis.c:229:7: error: ‘disassemble_info’ {aka ‘struct disassemble_info’} has no member named ‘please_use_fprintf_styled_func_instead’
    229 |   info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]);
        |       ^~

If this commit is accepted then I'll follow up with another commit
that adds the same #define to every disassembler that has been
converted to use styled output.

As the RISC-V disassembler is now fully styled, this commit should
make no difference at all.
2024-06-06 10:33:33 +01:00
Andrew Burgess
47277edc32 opcodes/riscv: add styling support to print_reg_list
I noticed that some unstyled output had crept into the risc-v
disassembler in this commit:

  commit 9132c8152b
  Date:   Tue Feb 27 11:48:11 2024 +0800

      RISC-V: Support Zcmp push/pop instructions.

this commit adds styling support.  The risc-v disassembler is now once
again, fully styled.
2024-06-06 10:17:04 +01:00
Xiao Zeng
0b4595be3f RISC-V: Add support for Zvfbfwma extension
This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>

1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
  1.1 In Embedded    Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
  1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
  1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin

2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfwma.d: New test.
	* testsuite/gas/riscv/zvfbfwma.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
	(MASK_VFWMACCBF16_VF): Ditto.
	(MATCH_VFWMACCBF16_VV): Ditto.
	(MASK_VFWMACCBF16_VV): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfwma.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFWMA

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06 16:10:53 +08:00
Xiao Zeng
d9c14a8744 RISC-V: Add support for Zvfbfmin extension
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>

Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfmin.d: New test.
	* testsuite/gas/riscv/zvfbfmin.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
	(MASK_VFNCVTBF16_F_F_W): Ditto.
	(MATCH_VFWCVTBF16_F_F_V): Ditto.
	(MASK_VFWCVTBF16_F_F_V): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfmin.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFMIN

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfmin instructions.
2024-06-06 16:10:51 +08:00
Xiao Zeng
af38c6367f RISC-V: Add support for Zfbfmin extension
This implements the Zfbfmin extension, as of version 1.0.

View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts>

1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
  FMV.H.X instructions as defined in the Zfh extension.

2 The Zfhmin extension includes the following instructions from the Zfh
  extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
  <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>

3 Zfhmin extension depend on 'F'.

4 Simply put, just make Zfbfmin dependent on Zfhmin.

Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.

5 For relevant information in gcc, please refer to:
  <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zfbfmin.d: New test.
	* testsuite/gas/riscv/zfbfmin.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
	(MASK_FCVT_BF16_S): Ditto.
	(MATCH_FCVT_S_BF16): Ditto.
	(MASK_FCVT_S_BF16): Ditto.
	(DECLARE_INSN): New declarations for Zfbfmin.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zfbfmin instructions.
2024-06-06 16:10:48 +08:00
Alan Modra
4287833613 Re: aarch64: Add some DT_RELR ld tests
aarch64-elf fails these tests due to .rela.dyn being at a different
address to that expected, and due to the symbol table being different.
Unexpected symbol numbering results in a mismatch of reloc r_info
field, but these are shown decoded so the raw field doesn't really add
anything to the test.

	* testsuite/ld-aarch64/relr-align.d: Accept any address for
	.relr.dyn section.  Don't match raw r_info field.
	* testsuite/ld-aarch64/relr-data-shared.d: Likewise.
	* testsuite/ld-aarch64/relr-got-shared.d: Likewise.
	* testsuite/ld-aarch64/relr-text-shared.d: Likewise.
2024-06-06 10:37:02 +09:30
GDB Administrator
761ed07709 Automatic date update in version.in 2024-06-06 00:00:27 +00:00
Richard Earnshaw
ecc5fed791 NEWS: arm: note that FPA support has been removed 2024-06-05 17:45:45 +01:00
Richard Earnshaw
298bc2ea2e arm: minor documentation cleanup given removal of FPA
The use in the documentation of .save for an FPA instruction is no-longer
relevant, so remove it.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
7917156599 arm: remove disassembly support for the FPA co-processor
Remove the FPA support from the disassembler.  This entails a couple
of testsuite fixes where we were (probably incorrectly) disassembling
a generic co-processor instruction using the legacy FPA opcodes.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
01613db787 arm: remove FPA instructions from assembler
These can no-longer be generated as the options to reach them have now
gone.  So remove the parsing support for FPA instructions.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
44d174bcb6 arm: remove options to select the FPA
Remove the command-line options to choose the FPA (or FPE - an
emulated FPA).  From this point on it should be impossible to assemble
the old FPA instructions.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
c27b73c525 arm: change default FPUs from FPA to none
Change the cases where the default FPU was FPA to none.  This should
ensure that any code that used settings to pick the floating-point
order will not silently produce a different output.  The options that
explicitly set the FPA remain for the moment.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
e8cf93739c arm: redirect fp constant data directives through a wrapper
Assembler directives such as .float, or .double are handled by generic
code, but on Arm, their output can vary depeding on the type of FPU
begin targetted.  When we remove FPA support we don't want to silently
generate different code for processors that previously defaulted to
the FPA, so redirect these directives through a wrapper function that
checks the FPU is enabled; we use the legacy -mno-fpu in the test to
catch this.

Also fix a few tests so that they won't start to fail on targets (eg
arm-wince-pe) where there is no default format for the FPU and we pick
this from the default processor type.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
be9943151a arm: adjust FPU selection logic
The logic here seems to be overly complex, so simplify it a bit.  One
particular problem was that using the legacy -mno-fpu option was not
working properly, as this has all the feature bits set to zero causing
the code to then pick a different FPU as the default.  Fix this by
only selecting an FPU as a fallback if the code has not otherwise
selected one: there was only one route by which this could happen.

This patch is really a pre-cursor to the following one where we want
to make no-fpu internally a fall-back position for some legacy
processors where previously we would have dropped back to the FPA.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
d3a79e2833 arm: default to softvfp on armv6 or later cores
From armv6 onwards a lot of cores started to come with a physical VFP
implementation; but many still did not and in some cases there are
both variants.  For the cores that lacked a physical VFP we would fall
back to FPU_NONE if the platform/ABI did not mandate something else.
To make matters worse, FPU_NONE is internal state used to imply
soft-fpa (ie a mixed-endian double format), so any use of .double in
hand-written assembly is almost certainly generating incorrect output.

That's undesirable, all these cores should really default to a softvfp
model.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
51c2c0f62b arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP
FPU_ARCH_VFP has always meant VFP floating-point format (natural FP
word order) but without any VFP instructions.  But the name
FPU_ARCH_VFP is potentially confusing.  This patch just changes the
name to make the meaning clearer.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
7ea20ae702 arm: remove FPA related tests
Remove various tests of the FPA instruction set and relocation support.
2024-06-05 17:45:44 +01:00
Nick Clifton
2db414c36b Fix illegal memory access when bfd_get_section_contents is called with a NULL section pointer.
PR 31843
2024-06-05 13:30:27 +01:00
Nelson Chu
3d7627c2d0 RISC-V: Tidy vendor core-v extension gas testcases
1. Combined testcases into one if they use same extention name.
2. Likewise for the fail testcases.
3. Renamed with x-cv prefix, just like what other vendors did.

gas/
	* testsuite/gas/riscv/cv-alu-*: Combined and renamed to
	x-cv-alu.  Likewise for fail testcases, to x-cv-alu-fail*.
	* testsuite/gas/riscv/cv-bi-*: Likewise, but renamed to
	x-cv-bi and x-cv-bi-fail.
	* testsuite/gas/riscv/cv-elw-*: Likewise, but renamed to
	x-cv-elw and x-cv-elw-fail.
	* testsuite/gas/riscv/cv-mac-*: Likewise, but renamed to
	x-cv-mac and x-cv-mac-fail.
	* testsuite/gas/riscv/cv-mem-*: Likewise, but renamed to
	x-cv-mem and x-cv-mem-fail.
2024-06-05 18:10:16 +08:00
Mary Bennett
29de80758f RISC-V: Add support for XCVmem extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvmem`
	instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:
	* doc/c-riscv.texi: Note XCVmem as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/cv-mem-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-mem-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-mem-lbpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lbrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lbrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lbrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lbupost.d: New test.
	* testsuite/gas/riscv/cv-mem-lbupost.s: New test.
	* testsuite/gas/riscv/cv-mem-lburr.d: New test.
	* testsuite/gas/riscv/cv-mem-lburr.s: New test.
	* testsuite/gas/riscv/cv-mem-lburrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lburrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lhrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lhrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhupost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhupost.s: New test.
	* testsuite/gas/riscv/cv-mem-lhurr.d: New test.
	* testsuite/gas/riscv/cv-mem-lhurr.s: New test.
	* testsuite/gas/riscv/cv-mem-lhurrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lhurrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lwpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lwpost.s: New test.
	* testsuite/gas/riscv/cv-mem-lwrr.d: New test.
	* testsuite/gas/riscv/cv-mem-lwrr.s: New test.
	* testsuite/gas/riscv/cv-mem-lwrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-lwrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-sbpost.d: New test.
	* testsuite/gas/riscv/cv-mem-sbpost.s: New test.
	* testsuite/gas/riscv/cv-mem-sbrr.d: New test.
	* testsuite/gas/riscv/cv-mem-sbrr.s: New test.
	* testsuite/gas/riscv/cv-mem-sbrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-sbrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-shpost.d: New test.
	* testsuite/gas/riscv/cv-mem-shpost.s: New test.
	* testsuite/gas/riscv/cv-mem-shrr.d: New test.
	* testsuite/gas/riscv/cv-mem-shrr.s: New test.
	* testsuite/gas/riscv/cv-mem-shrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-shrrpost.s: New test.
	* testsuite/gas/riscv/cv-mem-swpost.d: New test.
	* testsuite/gas/riscv/cv-mem-swpost.s: New test.
	* testsuite/gas/riscv/cv-mem-swrr.d: New test.
	* testsuite/gas/riscv/cv-mem-swrr.s: New test.
	* testsuite/gas/riscv/cv-mem-swrrpost.d: New test.
	* testsuite/gas/riscv/cv-mem-swrrpost.s: New test.
	* testsuite/gas/riscv/march-help.l: Add xcvmem string.

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK macros
	for XCVmem.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
	for XCVmem.
	(enum riscv_insn_class): Add the XCVmem instruction class.

opcodes/ChangeLog:

	* riscv-opc.c: Add XCVmem instructions.
2024-06-05 18:09:27 +08:00
Mary Bennett
b0f266f38b RISC-V: Add support for XCVbi extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>
  Nazareno Bruschi <nazareno.bruschi@embecosm.com>
  Lin Sinan

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
	for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add the necessary
	operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
	* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.
	* testsuite/gas/riscv/march-help.l: Add xcvbi string.

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
	for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add disassembly for new operand.
	* riscv-opc.c: Add XCVbi instructions.
2024-06-05 18:09:22 +08:00
Mary Bennett
940da069b4 RISC-V: Add support for XCVelw extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction
	class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi: Note XCVelw as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/cv-elw-fail.d: New test.
	* testsuite/gas/riscv/cv-elw-fail.l: New test.
	* testsuite/gas/riscv/cv-elw-fail.s: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.d: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.s: New test.
	* testsuite/gas/riscv/cv-elw-pass.d: New test.
	* testsuite/gas/riscv/cv-elw-pass.s: New test.
	* testsuite/gas/riscv/march-help.l: Add xcvelw string.

opcodes/ChangeLog:

	* riscv-opc.c: (riscv_opcode) Add event load instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	instruction opcode macros.
	* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.
2024-06-05 18:09:09 +08:00
Andrew Burgess
f95540d91f gdb/testsuite: remove trailing \r from rust_llvm_version result
I noticed that the value returned by rust_llvm_version had a trailing
carriage return.  I don't think this is causing any problems right
now, but looking at the code I don't think this was the desired
behaviour.

The current code runs 'rustc --version --verbose', splits the output
at each '\n' and then loops over every line looking for the line that
contains the LLVM version.

There are two problems here.  First, at the end of each captured line
we have '\r\n', so when we split the lines on '\n', each of the lines
will still end with a '\r' character.

Second, though we loop over the lines, when we try to compare the line
contents we actually compare the unsplit full output.  Luckily this
still finds the match, but this renders the loop over lines redundant.

This commit makes two fixes:

 1. I use regsub to convert all '\r\n' sequences to '\n'; now when we
    split on '\n' the lines will not end in '\r'.

 2. Within the loop over lines block I now check the line contents
    rather than the unsplit full output; now we capture a value
    without a trailing '\r'.

There's only one test (gdb.rust/simple.exp) that uses
rust_llvm_version, and it doesn't care if there's a trailing '\r' or
not, so this change should make no difference there.

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-05 10:19:35 +01:00
Andrew Burgess
5260dcf0c6 gdb: more filename styling in remote.c and target.c
I spotted a few more places where we could apply filename styling in
remote.c and target.c.  Other than the styling, there should be no
user visible changes after this commit.

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-05 10:18:03 +01:00
GDB Administrator
7b9cfd7f3d Automatic date update in version.in 2024-06-05 00:00:21 +00:00
Tom Tromey
d856ef4fc2 Return global scope from DAP scopes request
A co-worker requested that the DAP code emit a scope for global
variables.  It's not really practical to do this for all globals, but
it seemed reasonable to do this for globals coming from the frame's
compilation unit.  For Ada in particular, this is convenient as it
exposes package-scoped variables.

Reviewed-By: Eli Zaretskii <eliz@gnu.org>
2024-06-04 11:12:42 -06:00
Tom Tromey
4dd38c3983 Convert DAP disassemble code to use Block hashing
This changes the DAP disassemble code to use the new Block hashing,
storing the already-visited blocks in a set rather than a list.
2024-06-04 10:54:18 -06:00
Tom Tromey
aac3cc8258 Memoize gdb.Block and make them hashable
In subsequent patches, it's handy if gdb.Block is hashable, so it can
be stored in a set or a dictionary.  However, doing this in a
straightforward way is not really possible, because a block isn't
truly immutable -- it can be invalidated.  And, while this isn't a
real problem for my use case (in DAP the maps are only used during a
single stop), it seemed error-prone.

This patch instead takes the approach of using the gdb.Block's own
object identity to allow hashing.  This seems fine because the
contents don't affect the hashing.  In order for this to work, though,
the blocks have to be memoized -- two requests for the same block must
return the same object.

This also allows (actually, requires) the simplification of the
rich-compare method for blocks.

Reviewed-By: Alexandra Petlanova Hajkova <ahajkova@redhat.com>
2024-06-04 10:54:18 -06:00
Tom Tromey
ea54f7806b Put "source" into DAP scope
I noticed a FIXME comment in the DAP code about adding a "source"
field to a scope.  This is easy to implement; I don't know why I
didn't do this originally.
2024-06-04 10:36:34 -06:00
Tom Tromey
57ab1952fc Remove a couple unnecessary casts
After the previous bcache change, a couple of casts in objfiles.h are
now redundant.
2024-06-04 10:13:17 -06:00
Tom Tromey
7149dfe819 Make bcache more type-safe
The bcache uses memcpy to make copies of the data passed to it.  In
C++, this is only safe for trivially-copyable types.

This patch changes bcache to require this property, and slightly
changes the API to make it easier to use when copying a single object.
It also makes the new 'insert' template methods return the correct
type.
2024-06-04 10:13:17 -06:00
Tom Tromey
56fefe83f7 Some constification in psymtab
This patch changes some spots in psymtab.[ch] to use 'const'.  This is
just preparation for a subsequent patch.  Note that psymbols are
conceptually const, and since they were changed to be
objfile-indepdendent, they are truly never modified -- which is what
makes this patch reasonably short.
2024-06-04 10:13:17 -06:00
Tom Tromey
c12221171b Rely on std::uncaught_exceptions
std::uncaught_exceptions is a C++17 feature, so I think we can remove
this conditional code from inferior.h.
2024-06-04 09:49:27 -06:00
Dmitry Neverov
d3f6bbc48d Add myself to gdb/MAINTAINERS 2024-06-04 17:34:49 +02:00
Rostislav Krasny
333cf8e4d6 src-release.sh: fix adjusting files permissions and cleaning
PR 31800
2024-06-04 14:59:08 +01:00
Andrew Burgess
3e35b4deae gdb/testsuite: tests for debug lookup within the sysroot
Add tests for looking up debug information within the sysroot via both
build-id and gnu_debuglink.

I wanted to ensure that the gnu_debuglink test couldn't make use of
build-ids, so I added the 'no-build-id' flag to gdb_compile.

As these tests rely on setting the sysroot, if I'm running a
dynamically linked executable, GDB will try to find all shared
libraries within the sysroot.  This would mean I'd have to figure out
and copy all shared libraries the executable uses, certainly possible,
but a bit of a pain.

So instead, I've just compiled the test executable as a static binary.
Now there are no shared library dependencies.

I can now split the debug information out from the test binary, and
place it within the sysroot.  When GDB is started and the executable
loaded, we can check that GDB is finding the debug information within
the sysroot.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31804

Approved-By: Tom de Vries <tdevries@suse.de>
2024-06-04 13:33:31 +01:00
Andrew Burgess
9543c37620 gdb/testsuite: make gdb_gnu_strip_debug consistent
While writing a test I realised that the default behaviour of
gdb_gnu_strip_debug doesn't match its comment.

The comment says that the function takes a FILENAME, and splits the
file into FILENAME.stripped and FILENAME.debug, leaving FILENAME
unchanged.  The comment says that a .gnu_debuglink will be added to
FILENAME.stripped.

However, this is not true, FILENAME.stripped is created, with no debug
information.  FILENAME.debug is created containing the debug
information.

But, when adding the .gnu_debuglink we take FILENAME.stripped as the
input, and then overwrite FILENAME with the output.  As a result,
FILENAME.stripped does not include a .gnu_debuglink, while FILENAME
contains the .gnu_debuglink and no debug information!

The users of gdb_gnu_strip_debug can be split into two groups, those
who are using the .gnu_debuglink, these tests are all written assuming
that FILENAME is updated.

Then there are some tests that only rely on gdb_gnu_strip_debug's
ability to split out the debug information, these tests are then going
to do a lookup based on the build-id, these tests don't require the
.gnu_debuglink.  These tests use the FILENAME.stripped output file.

This all seems too confused to me.

As most uses of gdb_gnu_strip_debug assume that FILENAME is updated, I
propose that we just make that the actual, advertised behaviour of
this proc.

So now, gdb_gnu_strip_debug will take FILENAME, and will split the
debug information out into FILENAME.debug.  The debug information will
then be stripped from FILENAME, and by default a .gnu_debuglink will
be added to FILENAME pointing to FILENAME.debug.

I've updated the two tests that actually relied on FILENAME.stripped
to instead just use FILENAME.

One of the tests was doing a build-id based lookup, but was still
allowing the .gnu_debuglink to be added to FILENAME, I've updated this
test to pass the no-debuglink flag to gdb_gnu_strip_debug, which stops
the .gnu_debuglink from being added.

All of the tests that call gdb_gnu_strip_debug still pass for me.

Acked-By: Tom de Vries <tdevries@suse.de>
2024-06-04 13:33:31 +01:00
Andrew Burgess
92a89ee1d9 gdb/Makefile.in: silence recipe for creating .deps/ directories
When building in a fresh directory we'll see some output like this:

  /bin/sh ../../src/gdb/../mkinstalldirs arch/.deps
  mkdir -p -- arch/.deps
  /bin/sh ../../src/gdb/../mkinstalldirs cli/.deps
  mkdir -p -- cli/.deps
  /bin/sh ../../src/gdb/../mkinstalldirs dwarf2/.deps
  mkdir -p -- dwarf2/.deps
  ... etc ...

this commit uses silent-rules.mk to silence this output, now we'll
see:

  GEN    arch/.deps
  GEN    cli/.deps
  GEN    dwarf2/.deps
  ... etc ...

The recipe that currently generates these directories uses
mkinstalldirs, as I mention in commit 032e5e0c0c, mkinstalldirs
is deprecated and 'install-sh -d' should be used instead.  This
silences the 'mkdir -p -- ...' part of the output.

There should be no change in what is actually built after this commit.

Approved-By: Tom Tromey <tom@tromey.com>
2024-06-04 13:24:01 +01:00
mengqinggang
07284e5ee0 LoongArch: Disable linker relaxation if set the address of section or segment
If set the address of section or segment, the offset from pc to symbol
may become bigger and cause overflow.
2024-06-04 19:47:27 +08:00
mengqinggang
5f4fa40e4d LoongArch: Make align symbol be in same section with alignment directive
R_LARCH_ALIGN (psABI v2.30) requires a symbol index. The symbol is only
created at the first time to handle alignment directive. This means that
all other sections may use this symbol. If the section of this symbol is
discarded, there may be problems. Search it in its own section.

Remove elf_backend_data.is_rela_normal() function added at commit daeda14191.

Co-authored-by: Jinyang He <hejinyang@loongson.cn>
Reported-by: WANG Xuerui <git@xen0n.name>
Link: https://lore.kernel.org/loongarch/2abbb633-a10e-71cc-a5e1-4d9e39074066@loongson.cn/T/#t
2024-06-04 19:47:20 +08:00
Richard Earnshaw
b472e4cfd6 arm: testsuite: fix msdos line endings in tests
A couple of the tests in the testsuite were at some point in the past
committed with DOS-style CRLF line endings.  This potentially causes
email problems if the tests are touched in the middle of a large patch
series so convert them to standard Un*x line endings.
2024-06-04 11:52:35 +01:00
GDB Administrator
d806bf43d0 Automatic date update in version.in 2024-06-04 00:00:27 +00:00
Vladimir Mezentsev
9af067bfcd gprofng: add hardware counters for AMD Zen4
ChangeLog
2024-06-01  Vladimir Mezentsev  <vladimir.mezentsev@oracle.com>

	* common/hwctable.c: Add the hwc table for AMD Zen4.
	* src/hwc_amd_zen4.h: New file.
	* src/hwc_amd_zen3.h: Define _HWC_AMD_ZEN3_H.
2024-06-03 11:38:58 -07:00
Tom Tromey
7c493aa7e7 Remove one call to can_box from TUI
This removes a call to can_box from
tui_source_window_base::show_source_content.  can_box will always
return true here.

Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-06-03 11:22:53 -06:00