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31 Commits

Author SHA1 Message Date
Nelson Chu
d3ffd7f776 RISC-V: Support new .option arch directive. 
https://github.com/riscv/riscv-asm-manual/pull/67

Format:
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, =<ISA string>

The new direcitve is used to enable/disable extensions for the specific
code region.  For example,

.attribute arch, "rv64ic"   # arch = rv64i2p0_c2p0
.option push
.option arch, +d2p0, -c     # arch = rv64i2p0_f2p0_d2p0, f is added implied
.option arch, =rv32gc       # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
.option pop                 # arch = rv64i2p0_c2p0

Note that,
1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c".
2. ".option arch -i" is illegal, since we cannot remove base i extension.
3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version
   from 2.0 to 3.0.
4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version
   from 2.0 to the default one according to the chosen isa spec.

bfd/
	* elfxx-riscv.c (riscv_add_subset): If the subset is already added,
	and the new versions are not RISCV_UNKNOWN_VERSION, then update the
	versions to the subset list.
	(riscv_copy_subset): New function.  Copy the subset from list.
	(riscv_copy_subset_list): New function.  Return the new copyed list.
	(riscv_update_subset): Updated to make .option arch directives workable.
	* elfxx-riscv.h: Updated.
gas/
	* config/tc-riscv.c (riscv_subsets): Defined as a pointer.
	(riscv_rps_as): Init the subset_list to NULL, we will set it later
	once riscv_opts_stack is created or updated.
	(struct riscv_option_stack, riscv_opts_stack): Moved forward.
	(riscv_set_arch): Updated.
	(s_riscv_option): Support new .option arch directive, to add, remove
	or update subsets for the specific code region.
	(riscv_write_out_attrs): Updated.
	* doc/c-riscv.texi: Added document for new .option arch directive.
	* testsuite/gas/riscv/option-arch-01a.d: New testcase.
	* testsuite/gas/riscv/option-arch-01b.d: Likewise.
	* testsuite/gas/riscv/option-arch-01.s: Likewise..
	* testsuite/gas/riscv/option-arch-02.d: Likewise.
	* testsuite/gas/riscv/option-arch-02.s: Likewise.
	* testsuite/gas/riscv/option-arch-fail.d: Likewise.
	* testsuite/gas/riscv/option-arch-fail.l: Likewise.
	* testsuite/gas/riscv/option-arch-fail.s: Likewise.
 2021-11-19 18:50:27 +08:00
Nelson Chu
f786c359c1 RISC-V: Dump objects according to the elf architecture attribute. 
For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string.  This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed.  Consider the following case,

nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add     a0, a0, a0
.byte   0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    nop
   8:   00000013                nop
   c:   00000013                nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"

The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong.  After
applying this patch, I get the following result,

nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    .2byte  0x1
   8:   00000013                nop
   c:   00000013                nop

For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions.  Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.

However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes.  We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized.  Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.

This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains.  Also, tested by --enable-targets=all and can build
riscv-gdb successfully.

bfd/
	* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
	codes for riscv_parse_subset_t setting.
	* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
	(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	* elfxx-riscv.h: Added extern for riscv_subset_supports and
	riscv_multi_subset_supports.
gas/
	* config/tc-riscv.c (riscv_subset_supports): Moved to
	bfd/elfxx-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	(riscv_rps_as): Defined for architectrue parser.
	(riscv_set_arch): Updated.
	(riscv_set_abi_by_arch): Likewise.
	(riscv_csr_address): Likewise.
	(reg_lookup_internal): Likewise.
	(riscv_ip): Likewise.
	(s_riscv_option): Updated.
	* testsuite/gas/riscv/mapping-04b.d: Updated.
	* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
	* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
	* riscv-dis.c: Include elfxx-riscv.h since we need the
	architecture parser.  Also removed the cpu-riscv.h, it
	is already included in elfxx-riscv.h.
	(default_isa_spec): Defined since the parser need this
	to set the default architecture string.
	(xlen): Moved out from riscv_disassemble_insn as a global
	variable, it is more convenient to initialize riscv_rps_dis.
	(riscv_subsets): Defined to recoed the supported
	extensions.
	(riscv_rps_dis): Defined for architectrue parser.
	(riscv_disassemble_insn): Call riscv_multi_subset_supports
	to make sure if the instructions are valid or not.
	(print_insn_riscv): Initialize the riscv_subsets by parsing
	the elf architectrue attribute.  Otherwise, set the default
	architectrue string to rv64gc.
 2021-11-11 16:59:13 +08:00
Nelson Chu
edc77c591a RISC-V: Clarify the behavior of .option rvc or norvc. 
Add/Remove the rvc extension to/from the riscv_subsets once the
.option rvc/norvc is set.  So that we don't need to always check
the riscv_opts.rvc in the riscv_subset_supports, just call the
riscv_lookup_subset to search the subset list is enough.

Besides, we will need to dump the instructions according to the
elf architecture attributes.  That means the dis-assembler needs
to parse the architecture string from the elf attribute before
dumping any instructions, and also needs to recognized the
INSN_CLASS* classes from riscv_opcodes.  Therefore, I suppose
some functions will need to be moved from gas/config/tc-riscv.c
to bfd/elfxx-riscv.c, including riscv_multi_subset_supports and
riscv_subset_supports.  This is one of the reasons why we need
this patch.

This patch passes the gcc/binutils regressions of rv32emc-elf,
rv32i-elf, rv64gc-elf and rv64gc-linux toolchains.

bfd/
	* elfxx-riscv.c (riscv_remove_subset): Remove the extension
	from the subset list.
	(riscv_update_subset): Add/Remove an extension to/from the
	subset list.  This is used for the .option rvc or norvc.
	* elfxx-riscv.h: Added the extern bool riscv_update_subset.
gas/
	* config/tc-riscv.c (riscv_set_options): Removed the unused
	rve flag.
	(riscv_opts): Likewise.
	(riscv_set_rve): Removed.
	(riscv_subset_supports): Removed the riscv_opts.rvc check.
	(riscv_set_arch): Don't need to call riscv_set_rve.
	(reg_lookup_internal): Call riscv_subset_supports to check
	whether the rve is supported.
	(s_riscv_option): Add/Remove the rvc extension to/from the
	subset list once the .option rvc/norvc is set.
 2021-11-04 17:46:09 +08:00
Lewis Revill
9abcdc10b2 RISC-V: Don't separate pcgp relaxation to another relax pass. 
Commit abd20cb637 and
ebdcad3fdd introduced additional
complexity into the paths run by the RISC-V relaxation pass in order to
resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo
pairs. The first commit split up relaxation of these relocs into a pass
which occurred after other relaxations in order to prevent the situation
where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting
our ability to find the corresponding pcrel_hi relocation from the
address attached to the pcrel_lo.

Since the relaxation was split into two passes the 'again' parameter
could not be used to perform the entire relaxation process again and so
the second commit added a way to restart ldelf_map_segments, thus
starting the whole process again.

Unfortunately this process could not account for the fact that we were
not finished with the relaxation process so in some cases - such as the
case where code would not fit in a memory region before the
R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code
would fail.

This patch fixes all three of these concerns by reverting back to a
system of having only one target relax pass but updating entries in the
table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus
we can keep track of the pairs accurately, and we can use the 'again'
parameter to restart the entire target relax pass, behaving in the way
that generic code expects. Unfortunately we must still have an
additional pass to delay deleting AUIPC bytes to avoid ambiguity between
pcrel_hi relocs stored in the table after deletion. This pass can only
be run once so we may potentially miss out on relaxation opportunities
but this is likely to be rare.

https://sourceware.org/bugzilla/show_bug.cgi?id=28410

bfd/
	* elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax.
	(riscv_elf_link_hash_table_create): Updated.
	(riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs.
	Update the pcgp_relocs table whenever bytes are deleted.
	(riscv_update_pcgp_relocs): Add function to update the section
	offset of pcrel_hi and pcrel_lo, and also update the symbol value
	of pcrel_hi.
	(_bfd_riscv_relax_call): Need to update the pcgp_relocs table
	when deleting codes.
	(_bfd_riscv_relax_lui): Likewise.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN,
	we can't relax anything else, so set the sec->sec_flg0 to true.
	Besides, we don't need to update the pcgp_relocs table at this
	stage, so just pass NULL pointer as the pcgp_relocs table for
	riscv_relax_delete_bytes.
	(_bfd_riscv_relax_section): Use only one pass for all target
	relaxations.
	(_bfd_riscv_relax_delete): Likewise, we don't need to update
	the pcgp_relocs table at this stage, and don't need to set
	the `again' since restart_relax mechanism is abandoned.
	(bfd_elfNN_riscv_restart_relax_sections): Removed.
	(_bfd_riscv_relax_section): Updated.
	* elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed.
	(bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
	* emultempl/riscvelf.em: Revert restart_relax changes and set
	relax_pass to 3.
	* testsuite/ld-riscv-elf/align-small-region.d: New testcase.
	* testsuite/ld-riscv-elf/align-small-region.ld: Likewise.
	* testsuite/ld-riscv-elf/align-small-region.s: Likewise.
	* testsuite/ld-riscv-elf/restart-relax.d: Removed sine the
	restart_relax mechanism is abandoned.
	* testsuite/ld-riscv-elf/restart-relax.s: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2021-10-22 16:44:37 +08:00
Nelson Chu
c9f2799101 RISC-V: Merged extension string tables and their version tables into one. 
There are two main reasons for this patch,

* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c.  It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table.  Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.

* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default.  For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set.  In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.

The elf/linux regression tests of riscv-gnu-toolchain are passed.

bfd/
	* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
	bfd/elfxx-riscv.h.
	(riscv_merge_std_ext): Updated since the field of rpe is changed.
	* elfxx-riscv.c (cpu-riscv.h): Removed.
	(riscv_implicit_subsets): Added implicit extensions for g.
	(struct riscv_supported_ext): Used to be riscv_ext_version.  Moved
	from gas/config/tc-riscv.c, and added new field `default_enable' to
	decide if the extension should be enabled by default.
	(EXT_DEFAULT): Defined for `default_enable' field.
	(riscv_supported_std_ext): It used to return the supported standard
	architecture string, but now we move ext_version_table from
	gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
	Currently we not only use the table to initialize riscv_ext_order, but
	also get the default versions of extensions, and decide if the extensions
	should be enbaled by default.
	(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
	(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
	(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
	(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
	(riscv_all_supported_ext): Includes all supported extension tables.
	(riscv_known_prefixed_ext): Updated.
	(riscv_valid_prefixed_ext): Updated.
	(riscv_init_ext_order): Init the riscv_ext_order table according to
	riscv_supported_std_ext.
	(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
	Get the versions of extensions from riscv_supported_std* tables.
	(riscv_parse_add_subset): Updated.
	(riscv_parse_std_ext): Updated.
	(riscv_set_default_arch): Set the default subset list according to
	the default_enable field of riscv_supported_*ext tables.
	(riscv_parse_subset): If the input ARCH is NULL, then we call
	riscv_set_default_arch to set the default subset list.
	* elfxx-riscv.h (cpu-riscv.h): Included.
	(riscv_parse_subset_t): Removed get_default_version field, and added
	isa_spec field to replace it.
	(extern riscv_supported_std_ext): Removed.
gas/
	* (bfd/cpu-riscv.h): Removed.
	(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
	(ext_version_table): Likewise.
	(riscv_get_default_ext_version): Likewise.
	(ext_version_hash): Removed.
	(init_ext_version_hash): Removed.
	(riscv_set_arch): Updated since the field of rps is changed.  Besides,
	report error when the architecture string is empty.
	(riscv_after_parse_args): Updated.
 2021-09-17 16:33:54 +08:00
Nelson Chu
ef9d256562 RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 
2021-05-31  Nelson Chu  <nelson.chu@sifive.com>
            Lifang Xia  <lifang_xia@c-sky.com>

The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro.  It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.

One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations.  I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.

For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:

(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o

After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.

bfd/
    PR 27566
    * elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
    to monitor the data segment phase.
    (bfd_elfNN_riscv_set_data_segment_info): New function called by
    after_allocation, to set the data_segment_phase from expld.dataseg.
    (_bfd_riscv_relax_section): Don't relax when data_segment_phase is
    exp_seg_relro_adjust (0x4).
    * elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
    (bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
    PR 27566
    * emultempl/riscvelf.em (after_allocation): Call
    riscv_set_data_segment_info to set data segment phase before relaxing.
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
    * testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
    * testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
    * testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
    * testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
 2021-05-31 11:29:26 +08:00
Nelson Chu
fe1f847d9a RISC-V: Allow to link the objects with unknown prefixed extensions. 
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, ....  The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.

The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.

bfd/
    * elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
    prefixed extension name if check_unknown_prefixed_ext is false.
    * elfnn-riscv.c (riscv_merge_arch_attr_info): Set
    check_unknown_prefixed_ext to false for linker.
gas/
    * config/tc-riscv.c (riscv_set_arch): Set
    check_unknown_prefixed_ext to true for assembler.
 2021-05-26 11:02:29 +08:00
Nelson Chu
e3839c100f RISC-V: Don't report the mismatched version warning for the implicit extensions. 
bfd/
    * elfnn-riscv.c (riscv_version_mismatch): Do not report the warning
    when the version of input or output is RISCV_UNKNOWN_VERSION, since
    the extension is added implicitly.
    * elfxx-riscv.c: Updated the obsolete comments.
    (RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h.
    * elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
 2021-04-13 12:49:51 +08:00
Nelson Chu
e601909a32 RISC-V: Support to parse the multi-letter prefix in the architecture string. 
The original discussion is as follows,
https://github.com/riscv/riscv-isa-manual/issues/637

I never considered the prefixes may have multiple letters, like zxm.
But the ISA spec has been updated for a long time that I haven't noticed.
This patch rewrites the part of architecture parser to support parsing
the multi-letter prefixes.  Besides, I also improve the parser to report
errors in details.  One of the most obvious improvement is - Do not parse
the prefixed extensions according to the orders in the parse_config.
If we do so, then we used to get "unexpected ISA string at end" errors,
but the message is a little bit  hard to know what is happening.  I Remove
the confused message, and let riscv_parse_prefixed_ext to report the details.

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward.
    (riscv_std_s_ext_strtab): Likewise.
    (riscv_std_h_ext_strtab): Likewise.
    (riscv_std_zxm_ext_strtab): Added for the zxm prefix.
    (enum riscv_prefix_ext_class): Moved forward and renamed from
    riscv_isa_ext_class.  Reorder them according to the parsing order,
    since the enum values are used to check the orders in the
    riscv_compare_subsets.
    (struct riscv_parse_prefix_config): Moved forward and renamed from
    riscv_parse_config_t.  Also removed the ext_valid_p field, the
    related functions are replaced by riscv_valid_prefixed_ext.
    (parse_config): Moved forward and updated.  The more letters of the
    prefix string, the more forward it must be defined.  Otherwise, we
    will get the wrong mapping when using strncmp in riscv_get_prefix_class.
    (riscv_get_prefix_class): Moved forward.  Support to parse the
    multi-letter prefix, like zxm.
    (riscv_known_prefixed_ext): New function, check if the prefixed
    extension is supported according to the right riscv_std_*_ext_strtab.
    (riscv_valid_prefixed_ext): New function, used to replace the
    riscv_ext_*_valid_p functions.
    (riscv_init_ext_order): Do not set the values for prefix keywords
    since they may have multiple letters for now.
    (riscv_compare_subsets): Set the order values of prefix keywords
    to negative numbers according to the riscv_prefix_ext_class.
    (riscv_parse_std_ext): Call riscv_get_prefix_class to see if we
    have parsed the prefixed extensions.
    (riscv_parse_prefixed_ext): Updated and removed the parameter config.
    Report error when the prefix is unknown.
    (riscv_parse_subset): Do not parse the prefixed extensions according
    to the orders in the parse_config.  Remove the confused message and
    let riscv_parse_prefixed_ext to report the details.
    * elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c.
    (riscv_get_prefix_class): Removed to static.
gas/
    * testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from
    march-fail-porder-x-std.d.
    * testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from
    march-fail-porder-z-std.d.
    * testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from
    march-fail-porder-x-z.d.
    * testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace
    march-fail-porder.l.
    * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
    * testsuite/gas/riscv/march-fail-order-x.l: Updated.
    * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
    * testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from
    march-fail-single-char-h.d.
    * testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from
    march-fail-single-char-s.d.
    * testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from
    march-fail-single-char-x.d.
    * testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from
    march-fail-single-char-z.d.
    * testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added.
    * testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace
    march-fail-single-prefix.l.
    * testsuite/gas/riscv/march-fail-unknown-zxm.d: Added.
    * testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
    * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
 2021-04-12 10:05:37 +08:00
Alan Modra
0a1b45a20e Use bool in bfd 
* sysdep.h: POISON_BFD_BOOLEAN: Define.
	* aix5ppc-core.c, * aout-cris.c, * aout-ns32k.c, * aout-target.h,
	* aoutx.h, * arc-got.h, * archive.c, * archive64.c, * archures.c,
	* bfd-in.h, * bfd.c, * bfdwin.c, * binary.c, * cache.c,
	* coff-alpha.c, * coff-arm.c, * coff-arm.h, * coff-bfd.c,
	* coff-bfd.h, * coff-go32.c, * coff-i386.c, * coff-ia64.c,
	* coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c,
	* coff-stgo32.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c,
	* coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c,
	* coffcode.h, * coffgen.c, * cofflink.c, * compress.c,
	* corefile.c, * cpu-aarch64.c, * cpu-aarch64.h, * cpu-alpha.c,
	* cpu-arc.c, * cpu-arm.c, * cpu-arm.h, * cpu-avr.c, * cpu-bfin.c,
	* cpu-bpf.c, * cpu-cr16.c, * cpu-cris.c, * cpu-crx.c,
	* cpu-csky.c, * cpu-d10v.c, * cpu-d30v.c, * cpu-dlx.c,
	* cpu-epiphany.c, * cpu-fr30.c, * cpu-frv.c, * cpu-ft32.c,
	* cpu-h8300.c, * cpu-hppa.c, * cpu-i386.c, * cpu-ia64.c,
	* cpu-iamcu.c, * cpu-ip2k.c, * cpu-iq2000.c, * cpu-k1om.c,
	* cpu-l1om.c, * cpu-lm32.c, * cpu-m10200.c, * cpu-m10300.c,
	* cpu-m32c.c, * cpu-m32r.c, * cpu-m68hc11.c, * cpu-m68hc12.c,
	* cpu-m68k.c, * cpu-m9s12x.c, * cpu-m9s12xg.c, * cpu-mcore.c,
	* cpu-mep.c, * cpu-metag.c, * cpu-microblaze.c, * cpu-mips.c,
	* cpu-mmix.c, * cpu-moxie.c, * cpu-msp430.c, * cpu-mt.c,
	* cpu-nds32.c, * cpu-nfp.c, * cpu-nios2.c, * cpu-ns32k.c,
	* cpu-or1k.c, * cpu-pdp11.c, * cpu-pj.c, * cpu-powerpc.c,
	* cpu-pru.c, * cpu-riscv.c, * cpu-rl78.c, * cpu-rs6000.c,
	* cpu-rx.c, * cpu-s12z.c, * cpu-s390.c, * cpu-score.c,
	* cpu-sh.c, * cpu-sparc.c, * cpu-spu.c, * cpu-tic30.c,
	* cpu-tic4x.c, * cpu-tic54x.c, * cpu-tic6x.c, * cpu-tilegx.c,
	* cpu-tilepro.c, * cpu-v850.c, * cpu-v850_rh850.c, * cpu-vax.c,
	* cpu-visium.c, * cpu-wasm32.c, * cpu-xc16x.c, * cpu-xgate.c,
	* cpu-xstormy16.c, * cpu-xtensa.c, * cpu-z80.c, * cpu-z8k.c,
	* dwarf1.c, * dwarf2.c, * ecoff-bfd.h, * ecoff.c, * ecofflink.c,
	* elf-attrs.c, * elf-bfd.h, * elf-eh-frame.c, * elf-hppa.h,
	* elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-nacl.c,
	* elf-nacl.h, * elf-properties.c, * elf-s390-common.c,
	* elf-s390.h, * elf-strtab.c, * elf-vxworks.c, * elf-vxworks.h,
	* elf.c, * elf32-am33lin.c, * elf32-arc.c, * elf32-arm.c,
	* elf32-arm.h, * elf32-avr.c, * elf32-avr.h, * elf32-bfin.c,
	* elf32-bfin.h, * elf32-cr16.c, * elf32-cr16.h, * elf32-cris.c,
	* elf32-crx.c, * elf32-csky.c, * elf32-csky.h, * elf32-d10v.c,
	* elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
	* elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c,
	* elf32-h8300.c, * elf32-hppa.c, * elf32-hppa.h, * elf32-i386.c,
	* elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c,
	* elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
	* elf32-m68hc1x.c, * elf32-m68hc1x.h, * elf32-m68k.c,
	* elf32-m68k.h, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
	* elf32-metag.h, * elf32-microblaze.c, * elf32-mips.c,
	* elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c,
	* elf32-nios2.c, * elf32-nios2.h, * elf32-or1k.c, * elf32-pj.c,
	* elf32-ppc.c, * elf32-ppc.h, * elf32-pru.c, * elf32-rl78.c,
	* elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c,
	* elf32-score.h, * elf32-score7.c, * elf32-sh-relocs.h,
	* elf32-sh.c, * elf32-sparc.c, * elf32-spu.c, * elf32-spu.h,
	* elf32-tic6x.c, * elf32-tic6x.h, * elf32-tilegx.c,
	* elf32-tilepro.c, * elf32-v850.c, * elf32-v850.h,
	* elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
	* elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c,
	* elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c,
	* elf64-gen.c, * elf64-hppa.c, * elf64-ia64-vms.c,
	* elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c,
	* elf64-ppc.h, * elf64-s390.c, * elf64-sparc.c,
	* elf64-tilegx.c, * elf64-x86-64.c, * elfcode.h,
	* elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c,
	* elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c,
	* elfxx-aarch64.h, * elfxx-ia64.c, * elfxx-ia64.h,
	* elfxx-mips.c, * elfxx-mips.h, * elfxx-riscv.c, * elfxx-riscv.h,
	* elfxx-sparc.c, * elfxx-sparc.h, * elfxx-target.h,
	* elfxx-tilegx.c, * elfxx-tilegx.h, * elfxx-x86.c, * elfxx-x86.h,
	* format.c, * genlink.h, * hash.c, * i386aout.c, * i386lynx.c,
	* i386msdos.c, * ihex.c, * libaout.h, * libbfd-in.h,
	* libbfd.c, * libcoff-in.h, * libecoff.h, * libpei.h,
	* libxcoff.h, * linker.c, * mach-o-aarch64.c, * mach-o-arm.c,
	* mach-o-i386.c, * mach-o-x86-64.c, * mach-o.c, * mach-o.h,
	* merge.c, * mmo.c, * netbsd.h, * opncls.c, * pc532-mach.c,
	* pdp11.c, * pe-arm.c, * pe-i386.c, * pe-mcore.c, * pe-sh.c,
	* pe-x86_64.c, * peXXigen.c, * pef.c, * pei-arm.c, * pei-i386.c,
	* pei-ia64.c, * pei-mcore.c, * pei-sh.c, * pei-x86_64.c,
	* peicode.h, * plugin.c, * plugin.h, * ppcboot.c, * reloc.c,
	* reloc16.c, * rs6000-core.c, * section.c, * simple.c, * som.c,
	* som.h, * srec.c, * stabs.c, * syms.c, * targets.c, * tekhex.c,
	* verilog.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * vms.h,
	* wasm-module.c, * xcofflink.c, * xcofflink.h, * xsym.c,
	* xsym.h: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* libcoff.h: Regenerate.
 2021-03-31 10:49:23 +10:30
Nelson Chu
ebdcad3fdd RISC-V: Improve multiple relax passes problem. 
According to the commit abd20cb637, an
intersting thing is that - the more relax passes, the more chances of
relaxations are reduced [1].  Originally, we set the boolean `again`
to TRUE once the code is actually deleted, and then we run the relaxations
repeatedly if `again` is still TRUE.  But `again` only works for the
relax pass itself, and won't affect others.  That is - we can not use
`again` to re-run the relax pass when we already enter into the following
passes (can not run the relax passes backwards).  Besides, we must seperate
the PCREL relaxations into two relax passes for some reasons [2], it make
us lose some relax opportunities.

This patch try to fix the problem, and the basic idea was come from Jim
Wilson - we use a new boolean, restart_relax, to determine if we need to
run the whole relax passes again from 0 to 2.  Once we have deleted the
code between relax pass 0 to 2, the restart_relax will be set to TRUE,
we should run the whole relaxations again to give them more chances to
shorten the code.  We will only enter into the relax pass 3 when the
restart_relax is FALSE, since we can't relax anything else once we start
to handle the alignments.

I have passed the gcc/binutils regressions by riscv-gnu-toolchain, and
looks fine for now.

[1] https://sourceware.org/pipermail/binutils/2020-November/114223.html
[2] https://sourceware.org/pipermail/binutils/2020-November/114235.html

bfd/
    * elfnn-riscv.c (riscv_elf_link_hash_table): New boolean restart_relax,
    used to check if we need to run the whole relaxations from relax pass 0
    to 2 again.
    (riscv_elf_link_hash_table_create): Init restart_relax to FALSE.
    (_bfd_riscv_relax_align): Remove obsolete sec_flg0 set.
    (_bfd_riscv_relax_delete): Set again to TRUE if we do delete the code.
    (bfd_elfNN_riscv_restart_relax_sections): New function.  Called by
    after_allocation to check if we need to run the whole relaxations again.
    (_bfd_riscv_relax_section): We will only enter into the relax pass 3 when
    the restart_relax is FALSE; At last set restart_relax to TRUE if again is
    TRUE, too.
    * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Declaration.
    (bfd_elf64_riscv_restart_relax_sections): Likewise.
ld/
    * emultempl/riscvelf.em (after_allocation): Run ldelf_map_segments many
    times if riscv_restart_relax_sections returns TRUE.
    * testsuite/ld-riscv-elf/restart-relax.d: New testcase.  Before applying
    this patch, the call won't be relaxed to jal; But now we have more chances
    to do relaxations.
    * testsuite/ld-riscv-elf/restart-relax.s: Likewise.
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2021-03-11 17:27:13 +08:00
Nelson Chu
3d73d29e4e RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. 
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h.  Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use.  To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros.  Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.

bfd/
    * Makefile.am: Added cpu-riscv.h.
    * Makefile.in: Regenerated.
    * po/SRC-POTFILES.in: Regenerated.
    * cpu-riscv.h: Added to support spec versions controlling.
    Also added extern arrays and functions for cpu-riscv.c.
    (enum riscv_spec_class): Define all spec classes here uniformly.
    (struct riscv_spec): Added for all specs.
    (RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
    (RISCV_GET_SPEC_NAME): Likewise.
    (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
    (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
    (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
    * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
    (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
    (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
    (riscv_priv_specs): Moved below.
    (riscv_get_priv_spec_class_from_numbers): Likewise, updated.
    (riscv_isa_specs): Moved from include/opcode/riscv.h.
    * elfnn-riscv.c: Included cpu-riscv.h.
    (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
    * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
    (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
    * elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
    * config/tc-riscv.c: Included cpu-riscv.h.
    (enum riscv_csr_clas): Moved from include/opcode/riscv.h.
    (struct riscv_csr_extra): Likewise.
    (struct riscv_ext_version): Likewise.
    (ext_version_table): Moved from opcodes/riscv-opc.c.
    (default_isa_spec): Updated type to riscv_spec_class.
    (default_priv_spec): Likewise.
    (riscv_set_default_isa_spec): Updated.
    (init_ext_version_hash): Likewise.
    (riscv_init_csr_hash): Likewise, also fixed indent.
include/
    * opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
    * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
    (default_priv_spec): Updated type to riscv_spec_class.
    (parse_riscv_dis_option): Updated.
    * riscv-opc.c: Moved stuff and make the file tidy.
 2021-02-18 15:09:16 +08:00
Nelson Chu
dcd709e056 RISC-V: Comments tidy and improvement. 
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces.  But sometimes it should be more
cleaner when the comments only include a word or codes.  Therefore, I made
the following changes after referring to other target/generic codes,

* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.

Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.

bfd/
    * elfnn-riscv.c: Comments tidy and improvement.
    * elfxx-riscv.c: Likewise.
    * elfxx-riscv.h: Likewise.
gas/
    * config/tc-riscv.c: Comments tidy and improvement.  Also update
    comment "fallthru" to "Fall through" that end with a period and
    two spaces.
include/
    * elf/riscv.h: Comments tidy and improvement.
    * opcode/riscv-opc.h: Likewise.
    * opcode/riscv.h: Likewise.
opcodes/
    * riscv-dis.c: Comments tidy and improvement.
    * riscv-opc.c: Likewise.
 2021-01-15 17:28:07 +08:00
Nelson Chu
4c0e540e47 RISC-V: Fix the merged orders of Z* extension for linker. 
Similar to the commit 6729e2c2af,
we have to check the first char of the Z* extensions, to make
sure that they follow the order of the standard extensions.

bfd/
    * elfxx-riscv.c (riscv_compare_subsets): Removed static.
    * elfxx-riscv.h: Add declaration.
    * elfnn-riscv.c (riscv_merge_multi_letter_ext): Use
    riscv_compare_subsets to check the orders.
    (riscv_skip_prefix): Removed.
    (riscv_prefix_cmp): Removed.
 2021-01-04 11:17:33 +08:00
Alan Modra
250d07de5c Update year range in copyright notice of binutils files 2021-01-01 10:31:05 +10:30
Nelson Chu
00d4d1b0a3 RISC-V: Support to add implicit extensions for G. 
G is a special case, consider the ISA spec github issue as follows,
https://github.com/riscv/riscv-isa-manual/issues/575

My understand is that - i, m, a, f and d extensions are not g's implicit
extensions, they are g's expansions.  The zifencei is the implicit extension
of g, and so is zicsr, since it is implicited by f (or i2p1).  However,
we add the g with the RISCV_UNKNOWN_VERSION to the subset list, and it
will not output to the arch string, it is only used to check what implicit
extensions are need to be added.

	bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow to add g with
	RISCV_UNKNOWN_VERSION versions.
	(riscv_parse_std_ext): Add g to the subset list, we only use it
	to add the implicit extensions, but won't output it to arch string.
	(riscv_parse_add_implicit_subsets): Add implicit zicsr and zifencei
	for g extension.
	(riscv_arch_str1): Do not output g to the arch string.
	* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Moved to include/opcode/riscv.h.

	gas/
	* testsuite/gas/riscv/attribute-10.d: Updated.
	* testsuite/gas/riscv/march-imply-g.d: New testcase for g.
	* testsuite/gas/riscv/march-imply-unsupported.d: The zicsr and zifencei
	are not supported in the ISA spec v2.2, so don't add and output them.

	include/
	* opcode/riscv.h (RISCV_UNKNOWN_VERSION): added.
 2020-12-01 15:23:02 +08:00
Nelson Chu
dfe9249667 RISC-V: Support to add implicit extensions. 
We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions.  That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions.  For now we
follow the following rules to add the implicit extensions,

* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.

Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.

	bfd/
	* elfnn-riscv.c (riscv_merge_std_ext): Updated since
	riscv_lookup_subset is changed.
	* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
	extensions' order quickly.
	(riscv_init_ext_order): New function.  Init the riscv_ext_order
	according to the riscv_supported_std_ext and parse_config[i].class
	automatically.
	(riscv_compare_subsets): New function.  Similar to the strcmp, but
	compare the subsets with the specific order.
	(riscv_lookup_subset): Return TRUE and set `current` to the subset
	if it is found.  Otherwise, return FALSE and set `current` to the
	place where we should insert the subset.
	(riscv_add_implicit_subset): New function.  Search the list first,
	and then find the right place to add the implicit_subset.
	(riscv_parse_add_subset): Since We have to add all arch string
	extensions first, and then start to add their implicit extensions.
	We can add arch string extensions in order by the original
	riscv_add_subset, and then add the implicit subsets by the
	riscv_add_implicit_subset.  Besides, do not add the implicit
	extensions if we failed to find their default versions.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_add_implicit_subsets): New function.  Add all implicit
	extensions according to the arch string extensions.
	(riscv_parse_subset): Call riscv_init_ext_order and
	riscv_parse_add_implicit_subsets, before and after parsing the
	arch string.  Remove parts of the ISA conflict checking since
	the implicit extensions are added.
	* elfxx-riscv.h (riscv_lookup_subset): Updated.

	gas/
	* config/tc-riscv.c (riscv_subset_supports): Updated.
	* testsuite/gas/riscv/march-imply-i2p0.d: New testcase.  Need to
	add the implicit zicsr and zifencei when i's version less than 2.1.
	* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
	* testsuite/gas/riscv/march-imply-d.d: Likewise.
	* testsuite/gas/riscv/march-imply-f.d: Likewise.
	* testsuite/gas/riscv/march-imply-q.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
	* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
 2020-12-01 15:18:48 +08:00
Nelson Chu
7ef19aa616 RISC-V: Improve the version parsing for arch string. 
Keep the riscv_add_subset to do the same thing, and use a new
function, riscv_parse_add_subset, to cover most of the things
when parsing, including find the default versions for extensions,
and check whether the versions are valid.  The version 0p0 should
be an invalid version, that is the mistake I made before.  This
patch clarify the version rules as follows,

* We accept any version of extensions set by users, except 0p0.
* The non-standard x extensions must be set with versions in arch string.
* If user don't set the versions, or set 0p0 for the extensions, then try
  to find the supported versions according to the chosen ISA spec.
  Otherwise, report errors rather than output 0p0 for them.

Besides, we use as_bad rather than as_fatal to report more errors
for assembler.

	bfd/
	* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
	(riscv_add_subset): Likewise.
	(riscv_release_subset_list): Likewise.
	(riscv_parse_add_subset): New function.  Find and check the
	versions before adding them by riscv_add_subset.
	(riscv_parsing_subset_version): Remove use_default_version
	and change the version type from unsigned to int.  Set the
	versions to RISCV_UNKNOWN_VERSION if we can not find them
	in the arch string.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_prefixed_ext): Updated.  Since we use as_bad
	rather than as_fatal to report more errors, return NULL
	string if the parsed end_of_version is NULL, too.
	(riscv_parse_subset): Use a new boolean, no_conflict, to
	report more errors when we have more than one ISA conflicts.

	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
	RISCV_UNKNOWN_VERSION.
	(riscv_lookup_subset_version): Removed.
	(riscv_parse_subset_t): Updated.

	gas/
	* config/tc-riscv.c (riscv_get_default_ext_version):
	Change the version type from unsigned to int.
	(riscv_set_arch): Use as_bad rather than as_fatal to
	report more errors.

	* testsuite/gas/riscv/attribute-02.d: Updated since x must be
	set with versions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
	in the spec 2.2, so choose the newer spec.
	* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
	* testsuite/gas/riscv/march-fail-version.l: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.

	include/
	* opcode/riscv.h (riscv_ext_version):
	Change the version type from unsigned to int.
 2020-12-01 15:16:25 +08:00
Nelson Chu
5a1b31e1e1 RISC-V: Add zifencei and prefixed h class extensions. 
bfd/
	* elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard
	extensions when parsed h keyword.
	(riscv_get_prefix_class): Support prefixed h class.
	(riscv_std_h_ext_strtab): Likewise.
	(riscv_ext_h_valid_p): Likewise.
	(parse_config): Likewise.
	(riscv_std_z_ext_strtab): Add zifencei.
	* elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H.

	gas/
	* testsuite/gas/riscv/march-fail-order-z.d: New testcase, check
	orders of prefixed z extensions.
	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
	* testsuite/gas/riscv/march-fail-single-char-h.d: New testcase.
	* testsuite/gas/riscv/march-fail-single-char.l: Updated.
	* testsuite/gas/riscv/march-fail-unknown-h.d: New testcase.
	* testsuite/gas/riscv/march-fail-unknown.l: Updated.

	opcodes/
	* riscv-opc.c (riscv_ext_version_table): Add zifencei.
 2020-12-01 15:11:30 +08:00
Nelson Chu
d541518bec RISC-V: Minor cleanup and testcases improvement for arch string parser. 
Re-indent the related codes, unify and improve the related error messages
and comments.  Besies, also re-write the testcases to cover more cases.

	bfd/
	* elfxx-riscv.c: Re-indent codes, unify and improve the error
	messages and comments.
	(riscv_parse_prefixed_ext): Stop parsing the prefixed class
	extensions if the class is RV_ISA_CLASS_UNKNOWN, I get internal
	errors before adding this check for march-fail-porder* testcases.
	(riscv_parse_subset): Move the rv32 with q checking in front.
	* elfxx-riscv.h: Likewise.

	gas/
	(These are new testcases that cover more cases)
	* testsuite/gas/riscv/march-fail-base-01.d: The first extension must
	be e, i or g.
	* testsuite/gas/riscv/march-fail-base-01.l: Likewise.
	* testsuite/gas/riscv/march-fail-base-02.d: rv64e is an invalid base ISA.
	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-std.d: Check orders of standard
	extensions.
	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-x.d: Check orders of prefixed
	x extensions.
	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
	* testsuite/gas/riscv/march-fail-porder-x-std.d: Check orders when
	standard and prefixed extensions are set at the same time.
	* testsuite/gas/riscv/march-fail-porder-x-z.d: Likewise.
	* testsuite/gas/riscv/march-fail-porder-z-std.d: Likewise.
	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
	* testsuite/gas/riscv/march-fail-single-char-s.d: Only standard
	extensions can use single char.
	* testsuite/gas/riscv/march-fail-single-char-x.d: Likewise.
	* testsuite/gas/riscv/march-fail-single-char-z.d: Likewise.
	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-s.d: All extensions
	should be known, except the non-standard x extensions.
	* testsuite/gas/riscv/march-fail-unknown-std.d: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-z.d: Likewise.
	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase-base.d: Do not
	allow any uppercase in the arch string.
	* testsuite/gas/riscv/march-fail-uppercase-std.d: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase-z.d: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
	* testsuite/gas/riscv/march-fail-version-x.d: Failed to set versions.
	* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
	* testsuite/gas/riscv/march-fail-version.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Updated.
	* testsuite/gas/riscv/march-fail-rv32id.d: Need f-ext.
	* testsuite/gas/riscv/march-fail-rv32iq.d: Should be rv64.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.d: Need d-ext and f-ext.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.

	(The following testcases are removed and covered by new testcases)
	* testsuite/gas/riscv/march-fail-rv32i.d: march-fail-uppercase-base.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: march-fail-order-std.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: march-fail-uppercase-std.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: march-fail-version-x.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: march-fail-order-std.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: march-fail-uppercase-std.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: march-fail-base-02.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-fail-s-with-version.d: march-fail-unknown-s.
	* testsuite/gas/riscv/march-fail-s-with-version.l: Likewise.
	* testsuite/gas/riscv/march-fail-s.d: march-fail-unknown-s.
	* testsuite/gas/riscv/march-fail-s.l: Likewise.
	* testsuite/gas/riscv/march-fail-sx.d: march-fail-unknown-s.
	* testsuite/gas/riscv/march-fail-sx.l: Likewise.
 2020-12-01 15:04:03 +08:00
Nelson Chu
39ff0b8123 RISC-V: Report warning when linking the objects with different priv specs. 
We do know some conflicts among different privileged specs.  For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts.  But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems.  But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs.  But the option
is still under discussion.

Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs.  This not only makes the linker more flexible,
but also warns people that the conflicts may happen.  We also need to update
the output priv spec version once the input priv spec is newer.

	bfd/
	* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
	opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
	(riscv_get_priv_spec_class): Likewise.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New function, convert
	the version numbers into string, then call riscv_get_priv_spec_class
	to get the priv spec class.
	* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
	from include/opcode/riscv.h to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New forward declaration.
	(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
	* elfnn-riscv.c (riscv_merge_attributes):  Get the priv spec classes
	of input and output objects form their priv spec attributes by
	riscv_get_priv_spec_class_from_numbers.  Report warning rather than
	errors when linking objects with differnet priv spec versions.  We do
	know v1.9.1 may have conflicts to other versions, so report the
	warning, too.  After that, update the output priv spec version to the
	newest one so far.

	gas/
	* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
	(riscv_set_default_priv_spec): Get the priv spec version from the
	priv spec attributes by riscv_get_priv_spec_class_from_numbers.

	include/
	* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
	forward declarations to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.

	opcodes/
	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
 2020-06-22 10:01:14 +08:00
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
 2020-05-20 17:22:48 +01:00
Jim Wilson
403d1bd91d RISC-V: Change -march parsing. 
bfd/
	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
	* bfd/elfnn-riscv.c (riscv_skip_prefix): New.
	(riscv_prefix_cmp): Likewise.
	(riscv_non_std_ext_p): Deleted.
	(riscv_std_sv_ext_p): Likewise.
	(riscv_non_std_sv_ext_p): Likewise.
	(riscv_merge_non_std_and_sv_ext): Rename to...
	(riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp.
	(riscv_merge_arch_attr_info): Replace 3 calls to
	riscv_merge_non_std_and_sv_ext with single call to
	riscv_merge_multi_letter_ext.
	* bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we
	encounter a 'z' prefix.
	(riscv_get_prefix_class): New function, return prefix class based
	on first few characters of input string.
	(riscv_parse_config): New structure to factor out minor differences
	in extension class parsing behaviour.
	(riscv_parse_sv_or_non_std_ext): Rename to...
	(riscv_parse_prefixed_ext): and parameterise with
	riscv_parse_config.
	(riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New.
	(riscv_multi_letter_ext_valid_p): New.
	(riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New.
	(riscv_parse_subset): Delegate all non-single-letter parsing work
	to riscv_parse_prefixed_ext.
	* bfd/elfxx-riscv.h (riscv_isa_ext_class): New type.
	(riscv_get_prefix_class): Declare.

	gas/
	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
	* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
	s exts must be known, so rename *ok* to *fail*.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
	* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
	above change.
	* testsuite/gas/riscv/march-fail-sx.l: Likewise.
	* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.

Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
 2020-01-22 16:45:04 -08:00
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Jim Wilson
2dc8dd17cd RISC-V: Support ELF attribute for gas and readelf. 
2019-01-16  Kito Cheng  <kito@andestech.com>
		    Nelson Chu  <nelson@andestech.com>

	bfd/
	* elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Define as
	riscv_elf_obj_attrs_arg_type.
	* elfxx-riscv.c (riscv_estimate_digit): New.
	(riscv_estimate_arch_strlen1): Likewise.
	(riscv_estimate_arch_strlen): Likewise.
	(riscv_arch_str1): Likewise.
	(riscv_arch_str): Likewise.
	* elfxx-riscv.h (riscv_arch_str): Declare.
	binutils/
	* readelf.c (get_riscv_section_type_name): New function.
	(get_section_type_name): Add handler for RISC-V.
	(riscv_attr_tag_t): Declare.
	(riscv_attr_tag): New.
	(display_riscv_attribute): New function.
	(process_attributes): Add handler for RISC-V.
	* testsuite/binutils-all/strip-3.d: Remove .riscv.attribute
	section.
	gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
	(riscv_set_options): Add `arch_attr` field.
	(riscv_opts): Set default value for arch_attr.
	(riscv_write_out_arch_attr): New.
	(riscv_set_public_attributes): Likewise.
	(riscv_md_end): Likewise.
	(riscv_convert_symbolic_attribute): Likewise.
	(s_riscv_attribute): Likewise.
	(explicit_arch_attr): Likewise.
	(riscv_pseudo_table): Add .attribute to the table.
	(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
	enumeration constants.
	(md_longopts): Add `march-attr' and `mno-arch-attr' options.
	(md_parse_option): Handle the new options.
	(md_show_usage): Document the `march-attr' option.
	* config/tc-riscv.h (md_end): Define as riscv_md_end
	(riscv_md_end): Declare.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
	riscv_convert_symbolic_attribute.
	(riscv_convert_symbolic_attribute): Declare.
	(start_assemble): Declare.
	* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
	* testsuite/gas/elf/section2.e-riscv: New.
	* testsuite/gas/riscv/attribute-01.d: New test
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-04.s: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-06.s: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-07.s: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-08.s: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.s: Likewise.
	* testsuite/gas/riscv/empty.l: Likewise.
	* doc/c-riscv.texi (.attribute): Add documentation.
	* configure.ac (--enable-default-riscv-attribute): New options.
	* configure: Re-generate.
	* config.in: Re-generate.
	include/
	* elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
	(Tag_RISCV_arch): Likewise.
	(Tag_RISCV_priv_spec): Likewise.
	(Tag_RISCV_priv_spec_minor): Likewise.
	(Tag_RISCV_priv_spec_revision): Likewise.
	(Tag_RISCV_unaligned_access): Likewise.
	(Tag_RISCV_stack_align): Likewise.
 2019-01-16 13:14:59 -08:00
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Jim Wilson
1080bf78c0 RISC-V: Accept version, supervisor ext and more than one NSE for -march. 
This patch moves all -march parsing logic into bfd, because we will use this
code in ELF attributes.

	bfd/
	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro.
	(struct riscv_subset_t): New structure.
	(riscv_subset_t): New typedef.
	(riscv_subset_list_t): New structure.
	(riscv_release_subset_list): New prototype.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	* elfxx-riscv.c: Include safe-ctype.h.
	(riscv_parsing_subset_version): New function.
	(riscv_supported_std_ext): Likewise.
	(riscv_parse_std_ext): Likewise.
	(riscv_parse_sv_or_non_std_ext): Likewise.
	(riscv_parse_subset): Likewise.
	(riscv_add_subset): Likewise.
	(riscv_lookup_subset): Likewise.
	(riscv_lookup_subset_version): Likewise.
	(riscv_release_subset_list): Likewise.
	gas/
	* config/tc-riscv.c: Include elfxx-riscv.h.
	(struct riscv_subset): Removed.
	(riscv_subsets): Change type to riscv_subset_list_t.
	(riscv_subset_supports): Removed argument: xlen_required and move
	logic into libbfd.
	(riscv_multi_subset_supports): Removed argument: xlen_required.
	(riscv_clear_subsets): Removed.
	(riscv_add_subset): Ditto.
	(riscv_set_arch): Extract parsing logic into libbfd.
	(riscv_ip): Update argument for riscv_multi_subset_supports and
	riscv_subset_supports. Update riscv_subsets due to struct definition
	changed.
	(riscv_after_parse_args): Update riscv_subsets due to struct
	definition changed, update and argument for riscv_subset_supports.
	* testsuite/gas/riscv/empty.s: New.
	* testsuite/gas/riscv/march-fail-rv32ef.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32i.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iam.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ic.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32imc.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64I.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64e.l: Likewise.
	* testsuite/gas/riscv/march-ok-g2.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
	* testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d
	* testsuite/gas/riscv/march-ok-s-with-version.d: Likewise.
	* testsuite/gas/riscv/march-ok-s.d: Likewise.
	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
	* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
	include/
	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
	unsigned.
	opcodes/
	* riscv-opc.c: Change the type of xlen, because type of
	xlen_requirement changed.
 2018-12-03 14:05:17 -08:00
Alan Modra
0aa13feeeb unrecognized/unsupported reloc message 
It must get boring translating all the variants we have of
unrecognized/unsupported/invalid/unexpected reloc number.  This patch
cuts down on the number of variations.

	* aoutx.h, * coff-alpha.c, * coff-i860.c, * coff-m68k.c,
	* coff-mcore.c, * coff-ppc.c, * coff-rs6000.c, * coff-sh.c,
	* coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c, * coff-w65.c,
	* elf-bfd.h, * elf-m10300.c, * elf.c, * elf32-avr.c, * elf32-bfin.c,
	* elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c,
	* elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c,
	* elf32-fr30.c, * elf32-frv.c, * elf32-i370.c, * elf32-i386.c,
	* elf32-i960.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c,
	* elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c,
	* elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c,
	* elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c,
	* elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-or1k.c,
	* elf32-pj.c, * elf32-ppc.c, * elf32-rl78.c, * elf32-rx.c,
	* elf32-s390.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c,
	* elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c,
	* elf32-xgate.c, * elf32-xtensa.c, * elf64-alpha.c,
	* elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c,
	* elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c,
	* elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c,
	* elfnn-riscv.c, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-riscv.h,
	* elfxx-sparc.c, * elfxx-sparc.h, * reloc.c: Standardize
	unrecognized/unsupported reloc message.
 2018-02-26 09:28:27 +10:30
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Nick Clifton
e23eba971d Add support for RISC-V architecture. 
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
 2016-11-01 16:45:57 +00:00