Commit Graph

5780 Commits

Author SHA1 Message Date
Alan Modra
badf836a0c nds32: __builtin_strncpy bound equals destination size
* config/tc-nds32.c (do_pseudo_push_bhwd, do_pseudo_pop_bhwd),
	(do_pseudo_pusha, do_pseudo_pushi): Avoid fortify strncpy bound
	error.
2021-05-27 10:44:31 +09:30
H.J. Lu
50c95a739c x86: Propery check PC16 reloc overflow in 16-bit mode instructions
commit a7664973b2
Author: Jan Beulich <jbeulich@suse.com>
Date:   Mon Apr 26 10:41:35 2021 +0200

    x86: correct overflow checking for 16-bit PC-relative relocs

caused linker failure when building 16-bit program in a 32-bit ELF
container.  Update GNU_PROPERTY_X86_FEATURE_2_USED with

 #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12)

to indicate that 16-bit mode instructions are used in the input object:

https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA

to indicate that 16-bit mode instructions are used in the object to
allow linker to properly perform relocation overflow check for 16-bit
PC-relative relocations in 16-bit mode instructions.

1. Update x86 assembler to always generate the GNU property note with
GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object.
2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if
input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16.

bfd/

	PR ld/27905
	* elf32-i386.c: Include "libiberty.h".
	(elf_howto_table): Add 16-bit R_386_PC16 entry.
	(elf_i386_rtype_to_howto): Add a BFD argument.  Use 16-bit
	R_386_PC16 if input has 16-bit mode instructions.
	(elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto
	call.
	(elf_i386_tls_transition): Likewise.
	(elf_i386_relocate_section): Likewise.
	* elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit
	R_X86_64_PC16 entry.
	(elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input
	has 16-bit mode instructions.
	* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set
	elf_x86_has_code16 if relocatable input is marked with
	GNU_PROPERTY_X86_FEATURE_2_CODE16.
	* elfxx-x86.h (elf_x86_obj_tdata): Add has_code16.
	(elf_x86_has_code16): New.

binutils/

	PR ld/27905
	* readelf.c (decode_x86_feature_2): Support
	GNU_PROPERTY_X86_FEATURE_2_CODE16.

gas/

	PR ld/27905
	* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
	with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
	object.
	(set_16bit_gcc_code_flag): Likewise.
	(x86_cleanup): Always generate the GNU property note if
	x86_feature_2_used isn't 0.
	* testsuite/gas/i386/code16-2.d: New file.
	* testsuite/gas/i386/code16-2.s: Likewise.
	* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.

include/

	PR ld/27905
	* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New.

ld/

	PR ld/27905
	* testsuite/ld-i386/code16.d: New file.
	* testsuite/ld-i386/code16.t: Likewise.
	* testsuite/ld-x86-64/code16.d: Likewise.
	* testsuite/ld-x86-64/code16.t: Likewise.
	* testsuite/ld-i386/i386.exp: Run code16.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-26 12:13:24 -07:00
Nelson Chu
fe1f847d9a RISC-V: Allow to link the objects with unknown prefixed extensions.
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, ....  The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.

The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.

bfd/
    * elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
    prefixed extension name if check_unknown_prefixed_ext is false.
    * elfnn-riscv.c (riscv_merge_arch_attr_info): Set
    check_unknown_prefixed_ext to false for linker.
gas/
    * config/tc-riscv.c (riscv_set_arch): Set
    check_unknown_prefixed_ext to true for assembler.
2021-05-26 11:02:29 +08:00
Tamar Christina
d3e52e120b Arm: Fix forward thumb references [PR gas/25235]
When assembling a forward reference the symbol will be unknown and so during
do_t_adr we cannot set the thumb bit.  The bit it set so early to prevent
relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the
symbol is Thumb.

But because it's done so early we miss the case for forward references.
This patch changes it so that we additionally check the thumb bit during the
internal relocation processing.

In principle we should be able to only set the bit during reloc processing but
that would require changes to the other relocations that the instruction could
be relaxed to.

This approach still allows early relaxations (which means that we have less
iteration of internal reloc processing) while still fixing the forward reference
case.

gas/ChangeLog:

2021-05-24  Tamar Christina  <tamar.christina@arm.com>

	PR gas/25235
	* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
	(relax_adr): Thumb symbols 4 bytes.
	* testsuite/gas/arm/pr25235.d: New test.
	* testsuite/gas/arm/pr25235.s: New test.
2021-05-25 16:04:52 +01:00
Nelson Chu
5d0ed830d3 RISC-V: PR25212, Report errors for invalid march and mabi combinations.
This patch clarify the following invalid combinations of march and mabi,
* ilp32f/lp64f abi without f extension.
* ilp32d/lp64d abi without d extension.
* ilp32q/lp64q abi without q extension.
* e extension with any abi except ilp32e

GNU assembler reports errors when finding the above invalid combinations.
But LLVM-MC reports warnings and ignores these invalid cases.  It help to
set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve.  This
looks good and convenient, so perhaps we can do the same things.  However,
if you don't set the mabi, GNU assembler also try to set the suitable
ABI according to march/elf-attribute.  Compared to LLVM-MC, we will choose
double/quad abi if d/f extension is set.

gas/
    PR 25212
    * config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
    will choose ilp32e abi for rv32e.  Besides, report errors for the
    invalid march and mabi combinations.
    * testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase.  Only accept
    ilp32e abi for rve extension.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    Renamed all mabi testcases to their march-mabi settings.
2021-05-24 11:47:18 +08:00
Alan Modra
d71893802f Re: Fix offset for ia64 PCREL60B relocation on HP-UX
PR 25599
	* config/tc-ia64.c (emit_one_bundle): Expand comment for HP-UX
	adjustment.  Add assertion.
	* testsuite/gas/ia64/reloc-mlx.d: Pass when slot 2 specified
	for PCREL60B.
2021-05-22 17:23:24 +09:30
Sergey Belyashov
9a01ec4c03 Fix overflow detection in the Z80 assembler.
* config/tc-z80.c (emit_data_val): Warn on constant overflow.
 (signed_overflow): New function.
 (unsigned_overflow): New function.
 (is_overflow): Use new functions.
 (md_apply_fix): Use signed_overflow.
 * testsuite/gas/z80/ez80_adl_suf.d: Fix test.
 * testsuite/gas/z80/ez80_isuf.s: Likewise.
 * testsuite/gas/z80/ez80_z80_suf.d: Likewise.
2021-05-20 16:14:10 +01:00
John David Anglin
ee22a1a31d Fix offset for ia64 PCREL60B relocation on HP-UX
gas/ChangeLog:
2021-05-19  John Buddery  <jvb@cyberscience.com>
	PR 25599
	* config/tc-ia64.c (emit_one_bundle): Increment fixup offset
	by one for PCREL60B relocation on HP-UX.
2021-05-19 15:27:28 +00:00
Alex Coplan
e683cb4120 arm: Fix bugs with MVE vmov from two GPRs to vector lanes
The initial problem I wanted to fix here is that GAS was rejecting MVE
instructions such as:

vmov q3[2], q3[0], r2, r2

with:

Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2'

which is incorrect; such instructions are valid. Note that for moves in
the other direction, e.g.:

vmov r2, r2, q3[2], q3[0]

GAS is correct in rejecting this as it does not make sense to move both
lanes into the same register (the Arm ARM says this is CONSTRAINED
UNPREDICTABLE).

After fixing this issue, I added assembly/disassembly tests for these
vmovs. This revealed several disassembly issues, including incorrectly
marking the moves into vector lanes as UNPREDICTABLE, and disassembling
many of the vmovs as vector loads. These are now fixed.

gas/ChangeLog:

	* config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving
	into the same GPR twice.
	* testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message.
	* testsuite/gas/arm/mve-vmov-3.d: New test.
	* testsuite/gas/arm/mve-vmov-3.s: New test.

opcodes/ChangeLog:

	* arm-dis.c (mve_opcodes): Fix disassembly of
	MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
	(is_mve_encoding_conflict): MVE vector loads should not match
	when P = W = 0.
	(is_mve_unpredictable): It's not unpredictable to use the same
	source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-17 15:12:39 +01:00
Sergey Belyashov
cfe7a19169 Report illegal Z80 load instructions.
PR 27823
	* config/tc-z80.c (emit_ld_r_m): Report an illegal load
	instruction.
	* testsuite/gas/z80/ill_ops.s: New test source file.
	* testsuite/gas/z80/ill_ops.d: New test driver.
	* testsuite/gas/z80/ill_ops.l: New test error output.
2021-05-11 10:57:04 +01:00
Sergey Belyashov
e4b1ab2062 Add support for 8-bit and 24-bit shifts in the z80 assembler.
PR 27415
	* config/tc-z80.c (emit_data_val): Add support for 8-bit and
	24-bit shifts.
	* testsuite/gas/z80/z80_reloc.a: Update tests.
	* testsuite/gas/z80/z80_reloc.d: Update expected disassembly.
2021-05-10 13:36:08 +01:00
Nick Clifton
476654beae Add a generic .bss directive for ELF based targets.
PR 3136
	* config/obj-elf.c (elf_pseudo_table): Add entry for .bss.
	(obj_elf_bss): New function.  Change to the .bss section.
	Support an optional subsection number.
	(obj_elf_change_section): Call obj_elf_section_change_hook.
	(obj_elf_section): Likewise.
	(obj_elf_data): Likewise.
	(obj_elf_text): Likewise.
	(obj_elf_struct): Likewise.
	(obj_elf_subsection): Likewise.
	(obj_elf_previous): Likewise.
	* config/obj-elf.h (obj_elf_bss): Prototype.
	* doc/as.texi (Bss): New node.
2021-05-07 17:08:48 +01:00
Cl?ment Chigot
97834047e1 Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on XCOFF.
gas	* config/tc-ppc.c (ppc_function): Update comment for
	fifth argument.
	(ppc_frob_symbol): Remove ppc_last_function check.
	Make sure coff_last_function is reset.
	Correctly set fsize when not provided in .function.
	* testsuite/gas/ppc/aix.exp: New tests.
	* testsuite/gas/ppc/xcoff-function-1-32.d: New test.
	* testsuite/gas/ppc/xcoff-function-1-64.d: New test.
	* testsuite/gas/ppc/xcoff-function-1.s: New test.

bfd	* coff-rs6000.c (xcoff_dwsect_names): Add new DWARF
	sections.
	* coffgen.c (coff_pointerize_aux): Handle C_DWARF.
	(coff_print_symbol): Likewise.
	* libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update.

gas	* config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF.
	(coff_adjust_section_syms): Use corrext auxent for C_DWARF.
	(coff_frob_section): Likewise.
	* config/obj-coff.h (SA_GET_SECT_SCNLEN,
	SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN,
	SA_SET_SECT_NRELOC) New defines.
	(SET_SECTION_RELOCS): Adjust for C_DWARF.
	* config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF.
	(ppc_adjust_symtab): Reorder C_DWARF symbols.
	* testsuite/gas/ppc/aix.exp: New tests.
	* testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test.
	* testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test.
	* testsuite/gas/ppc/xcoff-dwsect-2.s: New test.

include	* coff/internal.h (C_DWARF): New define.
	* coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME,
	SSUBTYP_DWMAC): New defines.
2021-05-07 15:29:49 +01:00
Jan Beulich
98da05bf26 x86: don't mix disp and imm processing
Surely disp processing should access the disp operand, not an imm one.
This is not an active issue only because imms and disps are, at the
moment, overlapping fields of the same union.
2021-05-07 12:03:12 +02:00
Jan Beulich
9aac24b1a8 x86: move register check in immediate operand parsing
i386_finalize_immediate() is used for both AT&T and Intel immediate
operand handling. Move an AT&T-only check to i386_immediate(), which at
the same time allows it to cover other cases as well, giving an overall
better / more consistent diagnostic.
2021-05-07 12:02:40 +02:00
Jan Beulich
87ed972dc3 x86: minor improvements to optimize_imm()
- Drop a pointless & where just before it was checked that the
  respective bits are clear already anyway.
- Avoid a not really necessary operand_type_set() and a redundant
  operand_type_or() / operand_type_and() pair.
2021-05-07 12:02:07 +02:00
Jan Beulich
5e0a033bd2 x86: allow @secrel32 also in data definitions
Now that lex_got() is uniform for all targets using it, permit COFF
targets to also use @secrel32 with, in particular, .long. This is more
natural than the custom .secrel32 directive, and also allows more
flexibility (the "+six" form of the two added test lines doesn't work
with a .secrel32 equivalent, in that it silently produces an unintended
relocation type).

As an extra benefit this also makes sure that data definitions in Intel
syntax mode would get treated like they do for e.g. ELF targets.
2021-05-03 13:28:30 +02:00
Jan Beulich
deea497309 x86: fold both instances of lex_got()
I see no reason at all for us to carry two copies of almost identical
code. The differences, apart from the table entries, are benign. And
the #ifdef-ary doesn't really get any worse.
2021-05-03 13:26:41 +02:00
Jan Beulich
3abbafc2aa x86: relax when/how @size can be used
Allow a few more expression forms when the entire expression can be
resolved at assembly time. For this, i386_validate_fix() needs to
arrange for all processing of the relocation to be deferred to
tc_gen_reloc().
2021-04-29 11:45:10 +02:00
Jan Beulich
44f871628c x86: allow @size to also (sensibly) apply to sections
So far this (counter-intuitively) produced the size as recorded in the
(section) symbol. Obtain the section's size instead for section symbols.
(I wonder whether STT_SECTION symbols couldn't properly hold the
section's size in their st_size field, which in turn would likely mean
the internal symbol would also have its size properly updated.)

Note that this is not the same as the .sizeof.() pseudo-operator: @size
yields the local file's contribution to a section, while .sizeof.() gets
resolved by the linker to produce the final full section's size.

As to the 3rd each of the expected output lines in the changed testcase:
I can't find justification for zzz to come after yyy despite them being
defined in the opposite order in source. Therefore I think it's better
to permit both possible outcomes.
2021-04-29 11:43:53 +02:00
Jan Beulich
eb19308f2d x86: honor signedness of PC-relative relocations
PR gas/27763

While the comment in output_jump() was basically correct prior to the
introduction of 64-bit mode, both that and the not-JMP-like behavior of
XBEGIN require adjustments: Branches with 32-bit displacement do not
wrap at 4G in 64-bit mode, and XBEGIN with 16-bit operand size doesn't
wrap at 64k. Similarly %rip-relative addressing doesn't wrap at 4G.

The new testcase points out that for PE/COFF object_64bit didn't get
set so far, preventing in particular the check at the end of
md_convert_frag() to take effect.

For Mach-O the new testcase fails (bogusly), in that only the first two
of the expected errors get raised. Since for Mach-O many testcases
already fail, and since an x86_64-darwin target can't even be configured
for, I didn't think I need to bother.

Note that there are further issues in this area, in particular for
branches with operand size overrides. Such branches, which truncate
%rip / %eip, can't be correctly expressed with ordinary PC-relative
relocations. It's not really clear what to do with them - perhaps the
best we can do is to carry through all associated relocations, leaving
it to the linker (or even loader) to decide (once the final address
layout is known). Same perhaps goes for relocations associated with
32-bit addressing in 64-bit mode.
2021-04-28 10:53:00 +02:00
H.J. Lu
60cfa10c36 x86: Add () to silence GCC 5
Add () to !i.prefix[ADDR_PREFIX] to silence GCC 5:

gas/config/tc-i386.c:4152:31: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses]
     && !i.prefix[ADDR_PREFIX] != (flag_code == CODE_32BIT))
                               ^

	* config/tc-i386.c (optimize_encoding): Add () to silence GCC 5.
2021-04-27 08:16:55 -07:00
Jan Beulich
8fb8824599 x86: add IS_ELF to check whether to resolve @size reloc
This may not be strictly needed, as BFD_RELOC_SIZE* shouldn't appear
from elsewhere for non-ELF, but let's be on the safe side.
2021-04-26 10:39:45 +02:00
Jan Beulich
d965814fb6 x86: limit 32-bit @size overflow checks to 64-bit objects
For 32-bit objects the behavior should not be dependent upon the build
being a BFD64 one.
2021-04-26 10:39:11 +02:00
Jan Beulich
fe134c6569 x86: optimize LEA
Over the years I've seen a number of instances where people used

    lea     (%reg1), %reg2

or

    lea     symbol, %reg

despite the same thing being expressable via MOV. Since additionally
LEA often has restrictions towards the ports it can be issued to, while
MOV typically gets dealt with simply by register renaming, transform to
MOV when possible (without growing opcode size and without altering
involved relocation types).

Note that for Mach-O the new 64-bit testcases would fail (for
BFD_RELOC_X86_64_32S not having a representation), and hence get skipped
there.
2021-04-26 10:37:30 +02:00
Jan Beulich
b818855549 x86-64: have value properly checked when resolving fixup
Constants not known at the time an individual insn gets assembled and
going into a sign-extended field still shouldn't be silently truncated
at the time the respective fixup gets resolved.
2021-04-26 10:35:51 +02:00
J?r?me Gardou
d039200a7e Allow .seh_pushframe to take an optional [code] parameter
* config/obj-coff-seh.c (obj_coff_seh_pushframe): Allow an
	optional "code" argument.
2021-04-23 16:33:47 +01:00
Jan Beulich
a9aabc23ef x86-64: special case LEA when determining signedness of displacement
LEA behavior without a 64-bit destination is independent of address size
- in particular LEA with 32-bit addressing and 64-bit destination is the
same as LEA with 64-bit addressing and 32-bit destination. IOW checking
merely i.prefix[ADDR_PREFIX] is insufficient. This also means wrong
relocation types (R_X86_64_32S when R_X86_64_32 is needed) were used so
far in such cases.

Note that in one case in build_modrm_byte() the 64-bit check came too
early altogether, and hence gets dropped in favor of the one included in
the new helper. This is benign to non-64-bit code from all I can tell,
but the failure to clear disp16 could have been a latent problem.
2021-04-23 09:18:06 +02:00
Jan Beulich
cce08655c6 x86-64: defer 32-bit signed displacement check
In preparation for extending the conditions here defer this check until
operands have been parsed, as certain further attributes will need to
be known for determinig applicability of this check to be correct to
LEA.
2021-04-23 09:17:33 +02:00
Jan Beulich
28a167a406 x86: re-order optimize_disp()
While I can't point out any specific case where things break, it looks
wrong to have the consumer of a flag before its producer. Set .disp32
first, then do the possible conversion to signed 32-bit, and finally
check whether the value fits in a signed long.
2021-04-23 09:16:57 +02:00
Jan Beulich
7b025ee8c8 x86: don't truncate values in diagnostics and alike
Truncating an expression's X_add_number to just "long" can result in
confusing output (e.g. an apparently in-range number claimed to be out
of range). Use the abstraction that bfd provides for this.

Take the opportunity and also insert a missing "of".
2021-04-23 09:15:45 +02:00
Cl?ment Chigot
c5df7e442e Rework the R_NEG support on both gas and ld for the PowerPC AIX targets, in order to manage C++ exceptions built with GCC.
bfd	PR binutils/21700
	* reloc.c (BFD_RELOC_PPC_NEG): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* coff-rs6000.c (_bfd_xcoff_reloc_type_lookup): Add
	BFD_RELOC_PPC_NEG handler.
	(xcoff_reloc_type_neg): Correctly substract addend.
	* coff64-rs6000.c (xcoff64_howto_table): Add R_NEG_32
	howto.
	(xcoff64_rtype2howto): Add handler for R_NEG_32.
	(xcoff64_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler.
	* xcofflink.c (xcoff_need_ldrel_p): Check output section
	for R_POS-like relocations. New argument added.
	(xcoff_mark): Adapt to new xcoff_need_ldrel_p argument.
	(xcoff_link_input_bfd): Likewise.

gas	* config/tc-ppc.c (ppc_get_csect_to_adjust): New function.
	(ppc_fix_adjustable): Manage fx_subsy part.
	(tc_gen_reloc): Create second relocation when both
	fx_addsy and fx_subsy are provided.
	* config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define.
	(MAX_RELOC_EXPANSION): Likewise.
	(TC_FORCE_RELOCATION_SUB_SAME): Likewise
	(UNDEFINED_DIFFERENCE_OK): Likewise
	* testsuite/gas/all/gas.exp: Skip difference between two
	undefined symbols test.

ld	* testsuite/ld-powerpc/aix52.exp: Add new test.
	* testsuite/ld-powerpc/aix-neg-reloc-32.d: New test.
	* testsuite/ld-powerpc/aix-neg-reloc-64.d: New test.
	* testsuite/ld-powerpc/aix-neg-reloc.ex: New test.
	* testsuite/ld-powerpc/aix-neg-reloc.s: New test.
2021-04-20 14:40:43 +01:00
Jan Beulich
9a8041fd94 gas: drop sprint_value()
Its (documented) behavior is unhelpful in particular in 64-bit build
environments: While printing large 32-bit numbers in decimal already
isn't very meaningful to most people, this even more so goes for yet
larger 64-bit numbers. bfd_sprintf_vma() still tries to limit the number
of digits printed (without depending on a build system property), but
uniformly produces hex output.
2021-04-19 13:28:35 +02:00
Nelson Chu
768589d180 RISC-V: PR27436, make operand C> work the same as >.
gas/
    PR 27436
    * config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
    * testsuite/gas/riscv/shamt-32.d: New testcase.
    * testsuite/gas/riscv/shamt-32.l: Likewise.
    * testsuite/gas/riscv/shamt-32.s: Likewise.
    * testsuite/gas/riscv/shamt-64.d: Likewise.
    * testsuite/gas/riscv/shamt-64.l: Likewise.
    * testsuite/gas/riscv/shamt-64.s: Likewise.
2021-04-16 17:03:29 +08:00
Alan Modra
32d715691a Power10 bignum operands
When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux
and other 32-bit powerpc targeted binutils fail to assemble some
power10 prefixed instructions with 34-bit fields.  A typical error
seen when running the testsuite is
.../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid
In practice this doesn't matter for addresses:  32-bit programs don't
need or use the top 2 bits of a d34 field when calculating addresses.
However it may matter when loading or adding 64-bit constants with
paddi.  A power10 processor in 32-bit mode still has 64-bit wide GPRs.
So this patch enables limited support for O_big PowerPC operands, and
corrects sign extension of 32-bit constants using X_extrabit.

	* config/tc-ppc.c (insn_validate): Use uint64_t for operand values.
	(md_assemble): Likewise.  Handle bignum operands.
	(ppc_elf_suffix): Handle O_big.  Remove unnecessary input_line_pointer
	check.
	* expr.c: Delete unnecessary forward declarations.
	(generic_bignum_to_int32): Return uint32_t.
	(generic_bignum_to_int64): Return uint64_t.  Compile always.
	(operand): Twiddle X_extrabit for unary '~'.  Set X_unsigned and
	clear X_extrabit for unary '!'.
	* expr.h (generic_bignum_to_int32): Declare.
	(generic_bignum_to_int64): Declare.
	* testsuite/gas/ppc/prefix-pcrel.s,
	* testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 11:57:03 +09:30
Tejas Belagod
dd17020328 AArch64: Fix Diagnostic messaging for LD/ST Exclusive.
A summary of what this patch set fixes:

For instructions

	STXR w0,x2,[x0]
	STLXR w0,x2,[x0]

The warning we emit currently is misleading:

Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]'

it ought to be:

Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]'

For instructions:

	ldaxp x0,x0,[x0]
	ldxp x0,x0,[x0]

The warning we emit is incorrect

Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]'
Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]'

it ought to be:

Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]'
Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]'

For instructions

	stlxp   w0, x2, x2, [x0]
	stxp    w0, x2, x2, [x0]

We don't emit any warning when it ought to be:

Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]'

gas/ChangeLog:

2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>

	* config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages
	for LD/ST Exclusive instructions.
	* testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
	* testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09 12:32:00 +01:00
Nick Clifton
eac4eb8ecb Fix a problem assembling AArch64 sources when a relocation is generated against a symbol that has a defined value.
PR 27217
	* config/tc-aarch64.c (my_get_expression): Rename to
	aarch64_get_expression.  Add a fifth argument to enable deferring
	of expression resolution.
	(parse_typed_reg): Update calls to my_get_expression.
	(parse_vector_reg_list): Likewise.
	(parse_immediate_expression): Likewise.
	(parse_big_immediate): Likewise.
	(parse_shift): Likewise.
	(parse_shifter_operand_imm): Likewise.
	(parse_operands): Likewise.
	(parse_shifter_operand_reloc): Update calls to my_get_expression
	and call aarch64_force_reloc to determine the value of the new
	fifth argument.
	(parse_address_main): Likewise.
	(parse_half): Likewise.
	(parse_adrp): Likewise.
	(aarch64_force_reloc): New function.  Contains code extracted from...
	(aarch64_force_relocation): ... here.
	* testsuite/gas/aarch64/pr27217.s: New test case.
	* testsuite/gas/aarch64/pr27217.d: New test driver.
2021-04-06 13:27:50 +01:00
Alan Modra
23d613801d C99 gas configury
Also remove alloca stuff since we don't use alloca in gas nowadays.

	* configure.ac: Don't check for string.h, strings.h, stdlib.h,
	errno.h, limits.h, locale.h or time.h.  Don't check for unlink,
	remove, sbrk (unused) or setlocale.  Adjust gas_test_headers.
	Don't check for errno, free, malloc, realoc, sbrk, strstr, getenv
	strstr, or vsnprintf declarations.
	(AC_ISC_POSIX, AC_FUNC_ALLOCA, AC_C_INLINE): Don't invoke.
	* as.h: Don't include alloca-conf.h, include config.h instead.
	Include string.h, stdlib.h, errno.h unconditionally.  Remove
	various fallback declarations.
	* asintl.h: Don't test HAVE_LOCALE_H.
	* as.c: Don't test HAVE_SETLOCALE.
	* dwarf2dbg.c: Include limits.h unconditionally.
	* expr.c: Likewise.
	* sb.c: Likewise.
	* symbols.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-tic54x.c (tic54x_mlib): Call remove rather than unlink.
	* config.in: Regenerate.
	* configure: Regenerate.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
2021-04-05 15:31:25 +09:30
Martin Liska
e9b095a538 Remove strneq macro and use startswith.
bfd/ChangeLog:

	* ecoff.c (strneq): Remove strneq and use startswith.
	(_bfd_ecoff_slurp_armap): Likewise.

binutils/ChangeLog:

	* elfcomm.h (strneq): Remove strneq and use startswith.
	* readelf.c (ia64_process_unwind): Likewise.
	(process_note): Likewise.

gas/ChangeLog:

	* config/obj-coff.c (strneq): Remove strneq and use startswith.
	(weak_is_altname): Likewise.
	(obj_coff_section): Likewise.
	* config/tc-cr16.c (process_label_constant): Likewise.
	* config/tc-crx.c (strneq): Likewise.

include/ChangeLog:

	* opcode/cr16.h (strneq): Remove strneq and use startswith.

ld/ChangeLog:

	* ldbuildid.c (strneq): Remove strneq and use startswith.
	(validate_build_id_style): Likewise.
	(compute_build_id_size): Likewise.

opcodes/ChangeLog:

	* arm-dis.c (strneq): Remove strneq and use startswith.
	* cr16-dis.c (print_insn_cr16): Likewise.
	* score-dis.c (streq): Likewise.
	(strneq): Likewise.
	* score7-dis.c (strneq): Likewise.
2021-04-01 15:00:56 +02:00
Martin Liska
d34049e8bb Use startswith in gas subfolder.
gas/ChangeLog:

	* as.c (select_emulation_mode): Use startswith.
	* config/m68k-parse.y: Likewise.
	* config/obj-aout.c (obj_aout_type): Likewise.
	* config/obj-elf.c (elf_common_parse): Likewise.
	(obj_elf_section_type): Likewise.
	(obj_elf_section_word): Likewise.
	(obj_elf_section): Likewise.
	(obj_elf_symver): Likewise.
	(adjust_stab_sections): Likewise.
	* config/obj-evax.c (evax_shorten_name): Likewise.
	* config/obj-macho.c (obj_mach_o_is_frame_section): Likewise.
	* config/tc-aarch64.c (parse_aarch64_imm_float): Likewise.
	(aarch64_parse_features): Likewise.
	(create_register_alias): Likewise.
	(aarch64_data_in_code): Likewise.
	(md_parse_option): Likewise.
	* config/tc-alpha.c (s_alpha_section_word): Likewise.
	(s_alpha_pdesc): Likewise.
	* config/tc-arc.c (tokenize_extregister): Likewise.
	* config/tc-arm.c (create_register_alias): Likewise.
	(create_neon_reg_alias): Likewise.
	(parse_ifimm_zero): Likewise.
	(parse_qfloat_immediate): Likewise.
	(arm_elf_section_type): Likewise.
	(arm_parse_extension): Likewise.
	(aeabi_set_public_attributes): Likewise.
	(s_arm_arch_extension): Likewise.
	(arm_data_in_code): Likewise.
	(start_unwind_section): Likewise.
	* config/tc-avr.c (avr_ldi_expression): Likewise.
	* config/tc-csky.c (is_freglist_legal): Likewise.
	(csky_s_section): Likewise.
	* config/tc-d30v.c (do_assemble): Likewise.
	* config/tc-dlx.c (parse_operand): Likewise.
	* config/tc-epiphany.c (md_assemble): Likewise.
	* config/tc-h8300.c (h8300_elf_section): Likewise.
	(get_operand): Likewise.
	* config/tc-hppa.c (pa_ip): Likewise.
	(pa_level): Likewise.
	(pa_space): Likewise.
	* config/tc-i386.c (i386_mach): Likewise.
	(md_assemble): Likewise.
	(check_VecOperations): Likewise.
	(i386_target_format): Likewise.
	(i386_elf_section_type): Likewise.
	* config/tc-ia64.c (start_unwind_section): Likewise.
	(md_parse_option): Likewise.
	(is_taken_branch): Likewise.
	(idesc->name,): Likewise.
	(note_register_values): Likewise.
	(do_alias): Likewise.
	* config/tc-m32c.c (insn_to_subtype): Likewise.
	* config/tc-m68hc11.c (get_operand): Likewise.
	(md_assemble): Likewise.
	* config/tc-m68k.c (m68k_ip): Likewise.
	(m68k_elf_suffix): Likewise.
	* config/tc-mcore.c (mcore_s_section): Likewise.
	* config/tc-metag.c (parse_get_set): Likewise.
	(md_parse_option): Likewise.
	* config/tc-microblaze.c (parse_imm): Likewise.
	(check_got): Likewise.
	(md_apply_fix): Likewise.
	* config/tc-mips.c (CPU_HAS_MIPS16): Likewise.
	(md_begin): Likewise.
	(s_is_linkonce): Likewise.
	(check_regno): Likewise.
	(match_float_constant): Likewise.
	(classify_vr4120_insn): Likewise.
	(match_insn): Likewise.
	(mips_after_parse_args): Likewise.
	(s_change_sec): Likewise.
	(s_option): Likewise.
	(parse_code_option): Likewise.
	(md_section_align): Likewise.
	(nopic_need_relax): Likewise.
	* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
	* config/tc-mn10300.c (mn10300_fix_adjustable): Likewise.
	(mn10300_end_of_match): Likewise.
	* config/tc-msp430.c (msp430_make_init_symbols): Likewise.
	* config/tc-nds32.c (nds32_parse_option): Likewise.
	* config/tc-nds32.h (md_do_align): Likewise.
	* config/tc-nios2.c (strprefix): Likewise.
	(nios2_special_relocation_p): Likewise.
	(nios2_parse_base_register): Likewise.
	(nios2_cons): Likewise.
	* config/tc-ns32k.c (addr_mode): Likewise.
	* config/tc-pdp11.c (set_option): Likewise.
	(parse_reg): Likewise.
	(parse_ac5): Likewise.
	(parse_op_no_deferred): Likewise.
	(set_cpu_model): Likewise.
	(set_machine_model): Likewise.
	* config/tc-pj.c (md_operand): Likewise.
	* config/tc-ppc.c (ppc_set_cpu): Likewise.
	(ppc_arch): Likewise.
	(ppc_section_type): Likewise.
	* config/tc-s12z.c (tb_reg_rel): Likewise.
	(tb_opr_rel): Likewise.
	* config/tc-s390.c (s390_parse_cpu): Likewise.
	(md_parse_option): Likewise.
	* config/tc-score.c (s3_nopic_need_relax): Likewise.
	(s3_pic_need_relax): Likewise.
	* config/tc-score7.c (s7_nopic_need_relax): Likewise.
	(s7_pic_need_relax): Likewise.
	* config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise.
	* config/tc-sparc.c (md_parse_option): Likewise.
	(sparc_ip): Likewise.
	(s_reserve): Likewise.
	(s_common): Likewise.
	(s_seg): Likewise.
	(sparc_cons): Likewise.
	* config/tc-tic54x.c (stag_add_field): Likewise.
	(tic54x_endstruct): Likewise.
	* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
	* config/tc-v850.c (v850_comm): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-vax.c (vax_cons): Likewise.
	* config/tc-wasm32.c (wasm32_leb128): Likewise.
	* config/tc-xstormy16.c (md_operand): Likewise.
	* config/tc-xtensa.c (get_directive): Likewise.
	(xg_instruction_matches_option_term): Likewise.
	(is_unaligned_label): Likewise.
	(cache_literal_section): Likewise.
	* config/xtensa-relax.c (parse_precond): Likewise.
	(parse_option_cond): Likewise.
	(transition_applies): Likewise.
	(wide_branch_opcode): Likewise.
	* dw2gencfi.c: Likewise.
	* dwarf2dbg.c (dwarf2_directive_filename): Likewise.
	* ehopt.c (get_cie_info): Likewise.
	* input-file.c (input_file_open): Likewise.
	* listing.c (listing_newline): Likewise.
	(debugging_pseudo): Likewise.
	* read.c (read_a_source_file): Likewise.
	* write.c (adjust_reloc_syms): Likewise.
	(compress_debug): Likewise.
	(maybe_generate_build_notes): Likewise.
2021-04-01 15:00:08 +02:00
Alan Modra
fdb21288ca Don't include bfd/sysdep.h for gas files
* itbl-lex-wrapper.c: Include as.h not sysdep.h.
	* config/bfin-lex-wrapper.c: Likewise.
	* itbl-lex.l: Don't include as.h.
	* config/bfin-lex.l: Likewise.
2021-03-31 23:07:51 +10:30
Alan Modra
5b7c81bd8c Use bool in gas
* as.h (POISON_BFD_BOOLEAN): Define.
	* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
	* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
	* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
	* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
	* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
	* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
	* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
	* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
	* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
	* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
	* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
	* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
	* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
	* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
	* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
	* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
	* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
	* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
	* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
	* config/tc-metag.c, * config/tc-metag.h,
	* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
	* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
	* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
	* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
	* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
	* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
	* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
	* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
	* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
	* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
	* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
	* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
	* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
	* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
	* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
	* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
	* config/tc-xstormy16.c, * config/tc-xstormy16.h,
	* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
	* config/tc-z8k.c, * config/xtensa-istack.h,
	* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
	* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
	* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
	* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
	with bool, FALSE with false, and TRUE with true.
2021-03-31 10:49:23 +10:30
Alan Modra
3dfb1b6d34 Remove bfd_stdint.h
If we require C99 for binutils then stdint.h is available.

bfd/
	* .gitignore: Delete bfd_stdint.h entry.
	* Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h.
	(BUILD_HFILES, LOCAL_H_DEPS): Likewise.
	* bfd-in.h: Include stdint.h in place of bfd_stdint.h.
	* configure.ac: Don't invoke GCC_HEADER_STDINT.
	* configure.com: Don't create bfd_stdint.h.
	* Makefile.in: Regenerate.
	* aclocal.m4: Regenerate.
	* bfd-in2.h: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
binutils/
	* coffdump.c: Include stdint.h in place of bfd_stdint.h.
	* dwarf.c: Likewise.
gas/
	* config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h.
	* config/tc-crx.c: Likewise.
	* config/tc-nds32.h: Likewise.
include/
	* cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h.
	* elf/nfp.h: Likewise.
	* opcode/aarch64.h: Likewise.
	* opcode/cgen.h: Likewise.
	* opcode/nfp.h: Likewise.
	* opcode/ppc.h: Likewise.
ld/
	* elf-hints-local.h: Include stdint.h in place of bfd_stdint.h.
	* emultempl/nds32elf.em: Likewise.
	* testsuite/ld-elf/mbind2b.c: Likewise.
	* testsuite/ld-elf/pr18718.c: Likewise.
	* testsuite/ld-elf/pr18720a.c: Likewise.
	* testsuite/ld-elf/pr25749-1.c: Likewise.
	* testsuite/ld-elf/pr25749-1a.c: Likewise.
	* testsuite/ld-elf/pr25749-1b.c: Likewise.
	* testsuite/ld-elf/pr25749-1c.c: Likewise.
	* testsuite/ld-elf/pr25749-1d.c: Likewise.
	* testsuite/ld-elf/pr25749-2.c: Likewise.
	* testsuite/ld-elf/pr25754-1a.c: Likewise.
	* testsuite/ld-elf/pr25754-2a.c: Likewise.
	* testsuite/ld-elf/pr25754-3a.c: Likewise.
	* testsuite/ld-elf/pr25754-4a.c: Likewise.
	* testsuite/ld-elf/pr25754-5a.c: Likewise.
	* testsuite/ld-elf/pr25754-6a.c: Likewise.
opcodes/
	* aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
	* aarch64-dis.h: Likewise.
	* aarch64-opc.c: Likewise.
	* avr-dis.c: Likewise.
	* csky-dis.c: Likewise.
	* nds32-asm.c: Likewise.
	* nds32-dis.c: Likewise.
	* nfp-dis.c: Likewise.
	* riscv-dis.c: Likewise.
	* s12z-dis.c: Likewise.
	* wasm32-dis.c: Likewise.
2021-03-31 10:49:23 +10:30
Jan Beulich
5e0423804a x86: drop seg_entry
Use struct reg_entry instead for most purposes, with a separate array
holding just the respective opcode prefix bytes.
2021-03-30 14:09:41 +02:00
Jan Beulich
3468486226 x86: drop REGNAM_{AL,AX,EAX}
The former two are unused anyway. And having such constants isn't very
helpful either, when they live in a place where updating the register
table wouldn't even allow noticing the need to adjust these constants.
2021-03-30 14:08:48 +02:00
Jan Beulich
6288d05f11 x86: adjust st(<N>) parsing
st(1) ... st(7) will never be looked up in the hash table, so there's no
point inserting the entries. It's also not really necessary to do a 2nd
hash lookup after parsing the register number, nor is there a real
reason for having both st and st(0) entries. Plus we can easily do away
with the need for st to be first in the table.
2021-03-30 14:08:11 +02:00
Jan Beulich
ca5312a241 x86: integrate rc_op into struct _i386_insn
There's no need for the extra level of indirection and the extra storage
needed for the pointer, pointing from one piece of static data to
another. Key checking of rounding being in effect off of the type field
of the structure instead.
2021-03-30 14:06:37 +02:00
Jan Beulich
5273a3cd48 x86: integrate broadcast_op into struct _i386_insn
There's no need for the extra level of indirection and the extra storage
needed for the pointer, pointing from one piece of static data to
another. Key checking of broadcast being in effect off of the type field
of the structure instead.
2021-03-30 14:06:09 +02:00
Jan Beulich
6225c532b4 x86: integrate mask_op into struct _i386_insn
There's no need for the extra level of indirection and the extra storage
needed for the pointer, pointing from one piece of static data to
another. Key checking of masking being in effect off of the register
field of the structure instead.
2021-03-30 14:05:42 +02:00
Jan Beulich
783c187b8c x86: make swap_2_operands() have unsigned parameters
All callers pass unsigned values (in some cases by virtue of passing
non-negative literal numbers).

This in turn requires struct {Mask,RC,Broadcast}_Operation's "operand"
fields to become unsigned, in turn allowing to reduce the amount of
casting needed (the two new casts that are necessary cast _to_
"unsigned" instead of _from_, as that's the form that'll never case
undefined behavior).
2021-03-30 14:05:10 +02:00