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132 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Pedro Alves
|
f34652de0b |
internal_error: remove need to pass __FILE__/__LINE__
Currently, every internal_error call must be passed __FILE__/__LINE__
explicitly, like:
internal_error (__FILE__, __LINE__, "foo %d", var);
The need to pass in explicit __FILE__/__LINE__ is there probably
because the function predates widespread and portable variadic macros
availability. We can use variadic macros nowadays, and in fact, we
already use them in several places, including the related
gdb_assert_not_reached.
So this patch renames the internal_error function to something else,
and then reimplements internal_error as a variadic macro that expands
__FILE__/__LINE__ itself.
The result is that we now should call internal_error like so:
internal_error ("foo %d", var);
Likewise for internal_warning.
The patch adjusts all calls sites. 99% of the adjustments were done
with a perl/sed script.
The non-mechanical changes are in gdbsupport/errors.h,
gdbsupport/gdb_assert.h, and gdb/gdbarch.py.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Change-Id: Ia6f372c11550ca876829e8fd85048f4502bdcf06
|
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Torbjörn SVENSSON
|
60c90d8c6d |
gdb/arm: Handle lazy FPU state preservation
Read LSPEN, ASPEN and LSPACT bits from FPCCR and use them together with FPCAR to identify if lazy FPU state preservation is active for the current frame. See "Lazy context save of FP state", in B1.5.7, also ARM AN298, supported by Cortex-M4F architecture for details on lazy FPU register stacking. The same conditions are valid for other Cortex-M cores with FPU. This patch has been verified on a STM32F4-Discovery board by: a) writing a non-zero value (lets use 0x1122334455667788 as an example) to all the D-registers in the main function b) configured the SysTick to fire c) in the SysTick_Handler, write some other value (lets use 0x0022446688aaccee as an example) to one of the D-registers (D0 as an example) and then do "SVC #0" d) in the SVC_Handler, write some other value (lets use 0x0099aabbccddeeff) to one of the D-registers (D0 as an example) In GDB, suspend the execution in the SVC_Handler function and compare the value of the D-registers for the SVC_handler frame and the SysTick_Handler frame. With the patch, the value of the modified D-register (D0) should be the new value (0x009..eff) on the SVC_Handler frame, and the intermediate value (0x002..cee) for the SysTick_Handler frame. Now compare the D-register value for the SysTick_Handler frame and the main frame. The main frame should have the initial value (0x112..788). Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> Signed-off-by: Yvan ROUX <yvan.roux@foss.st.com> |
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Keith Seitz
|
ac9b8c676e |
Constify target_desc declarations
This patch changes various global target_desc declarations to const, thereby correcting a prominent source of ODR violations in PowerPC-related target code. The majority of files/changes are mechanical const-ifications accomplished by regenerating the C files in features/. This also required manually updating mips-linux-tdep.h, s390-linux-tdep.h, nios2-tdep.h, s390-tdep.h, arch/ppc-linux-tdesc.h, arch/ppc-linux-common.c, and rs6000-tdep.c. Patch tested against the sourceware trybot, and fully regression tested against our (Red Hat's) internal test infrastructure on Rawhide aarch64, s390x, x86_64, and powerpcle. With this patch, I can finally enable LTO in our GDB package builds. [Tested with a rawhide scratch build containing this patch.] Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=22395 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=24835 |
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Jiangshuai Li
|
8e037eae68 |
gdb/csky add cskyv2-linux.xml for cskyv2-linux.c
Add cskyv2-linux.xml for re-generating cskyv2-linux.c if needed. Also update cskyv2-linux.c. |
||
|
Jiangshuai Li
|
02cd1b4e97 |
gdbserver/csky add csky gdbserver support
Add new files:
gdb/arch/csky.c
gdb/arch/csky.h
gdb/features/cskyv2-linux.c
gdbserver/linux-csky-low.cc
1. In gdb/arch/csky.c file, add function "csky_create_target_description()"
for csky_target::low_arch_setup(). later, it can be used for csky native gdb.
2. In gdb/features/cskyv2-linux.c file, create target_tdesc for csky, include
gprs, pc, hi, lo, float, vector and float control registers.
3. In gdbserver/linux-csky-low.cc file, using PTRACE_GET/SET_RGESET to
get/set registers. The main data structures in asm/ptrace.h are:
struct pt_regs {
unsigned long tls;
unsigned long lr;
unsigned long pc;
unsigned long sr;
unsigned long usp;
/*
* a0, a1, a2, a3:
* r0, r1, r2, r3
*/
unsigned long orig_a0;
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
/*
* r4 ~ r13
*/
unsigned long regs[10];
/* r16 ~ r30 */
unsigned long exregs[15];
unsigned long rhi;
unsigned long rlo;
unsigned long dcsr;
};
struct user_fp {
unsigned long vr[96];
unsigned long fcr;
unsigned long fesr;
unsigned long fid;
unsigned long reserved;
};
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Andrew Burgess
|
4749b84b51 |
gdb/riscv: better support for fflags and frm registers
First, some background on the RISC-V registers fflags, frm, and fcsr. These three registers all relate to the floating-point status and control mechanism on RISC-V. The fcsr is the floatint-point control status register, and consists of two parts, the flags (bits 0 to 4) and the rounding-mode (bits 5 to 7). The fcsr register is just one of many control/status registers (or CSRs) available on RISC-V. The fflags and frm registers are also CSRs. These CSRs are aliases for the relevant parts of the fcsr register. So fflags is an alias for bits 0 to 4 of fcsr, and frm is an alias for bits 5 to 7 of fcsr. This means that a user can change the floating-point rounding mode either, by writing a complete new value into fcsr, or by writing just the rounding mode into frm. How this impacts on GDB is like this: a target description could, legitimately include all three registers, fcsr, fflags, and frm. The QEMU target currently does this, and this makes sense. The target is emulating the complete system, and has all three CSRs available, so why not tell GDB about this. In contrast, the RISC-V native Linux target only has access to the fcsr. This is because the ptrace data structure that the kernel uses for reading and writing floating point state only contains a copy of the fcsr, after all, this one field really contains both the fflags and frm fields, so why carry around duplicate data. So, we might expect that the target description for the RISC-V native Linux GDB would only contain the fcsr register. Unfortunately, this is not the case. The RISC-V native Linux target uses GDB's builtin target descriptions by calling riscv_lookup_target_description, this will then add an fpu feature from gdb/features/riscv, either 32bit-fpu.xml or 64bit-fpu.xml. The problem, is that these features include an entry for fcsr, fflags, and frm. This means that GDB expects the target to handle reading and writing these registers. And the RISC-V native Linux target currently doesn't. In riscv_linux_nat_target::store_registers and riscv_linux_nat_target::fetch_registers only the fcsr register is handled, this means that, for RISC-V native Linux, the fflags and frm registers always show up as <unavailable> - they are present in the target description, but the target doesn't know how to access the registers. A final complication relating to these floating pointer CSRs is which target description feature the registers appear in. These registers are CSRs, so it would seem sensible that these registers should appear in the CSR target description feature. However, when I first added RISC-V target description support, I was using a RISC-V simulator that didn't support any CSRs other than the floating point related ones. This simulator bundled all the float related CSRs into the fpu target feature. This didn't feel completely unreasonable to me, and so I had GDB check for these registers in either target feature. In this commit I make some changes relating to how GDB handles the three floating point CSR: 1. Remove fflags and frm from 32bit-fpu.xml and 64bit-fpu.xml. This means that the default RISC-V target description (which RISC-V native FreeBSD), and the target descriptions created for RISC-V native Linux, will not include these registers. There's nothing stopping some other target (e.g. QEMU) from continuing to include all three of these CSRs, the code in riscv-tdep.c continues to check for all three of these registers, and will handle them correctly if they are present. 2. If a target supplied fcsr, but does not supply fflags and/or frm, then RISC-V GDB will now create two pseudo registers in order to emulate the two missing CSRs. These new pseudo-registers do the obvious thing of just reading and writing the fcsr register. 3. With the new pseudo-registers we can no longer make use of the GDB register numbers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM. These will be the numbers used if the target supplies the registers in its target description, but, if GDB falls back to using pseudo-registers, then new, unique numbers will be used. To handle this I've added riscv_gdbarch_tdep::fflags_regnum and riscv_gdbarch_tdep::frm_regnum, I've then updated the RISC-V code to compare against these fields. When adding the pseudo-register support, it is important that the pseudo-register numbers are calculated after the call to tdesc_use_registers. This is because we don't know the total number of physical registers until after this call, and the psuedo-register numbers must follow on from the real (target supplied) registers. I've updated some tests to include more testing of the fflags and frm registers, as well as adding a new test. |
||
Feiyang Chen
|
ea3352172e |
gdb/gdbserver: LoongArch: Improve implementation of fcc registers
The current implementation of the fcc register is referenced to the
user_fp_state structure of the kernel uapi [1].
struct user_fp_state {
uint64_t fpr[32];
uint64_t fcc;
uint32_t fcsr;
};
But it is mistakenly defined as a 64-bit fputype register, resulting
in a confusing output of "info register".
(gdb) info register
...
fcc {f = 0x0, d = 0x0} {f = 0, d = 0}
...
According to "Condition Flag Register" in "LoongArch Reference Manual"
[2], there are 8 condition flag registers of size 1. Use 8 registers of
uint8 to make it easier for users to view the fcc register groups.
(gdb) info register
...
fcc0 0x1 1
fcc1 0x0 0
fcc2 0x0 0
fcc3 0x0 0
fcc4 0x0 0
fcc5 0x0 0
fcc6 0x0 0
fcc7 0x0 0
...
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/uapi/asm/ptrace.h
[2] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_condition_flag_register
Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
|
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Luis Machado
|
68cffbbd44 |
[AArch64] MTE corefile support
Teach GDB how to dump memory tags for AArch64 when using the gcore command and how to read memory tag data back from a core file generated by GDB (via gcore) or by the Linux kernel. The format is documented in the Linux Kernel documentation [1]. Each tagged memory range (listed in /proc/<pid>/smaps) gets dumped to its own PT_AARCH64_MEMTAG_MTE segment. A section named ".memtag" is created for each of those segments when reading the core file back. To save a little bit of space, given MTE tags only take 4 bits, the memory tags are stored packed as 2 tags per byte. When reading the data back, the tags are unpacked. I've added a new testcase to exercise the feature. Build-tested with --enable-targets=all and regression tested on aarch64-linux Ubuntu 20.04. [1] Documentation/arm64/memory-tagging-extension.rst (Core Dump Support) |
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Tiezhu Yang
|
657a50227b |
gdb: LoongArch: Add floating-point support
This commit adds floating-point support for LoongArch gdb. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> |
||
|
Luis Machado
|
0556ff7376 |
Fix include guard naming for arch/aarch64-mte-linux.h
It should be ARCH_AARCH64_MTE_LINUX_H as opposed to ARCH_AARCH64_LINUX_H. |
||
Youling Tang
|
3eba483364 |
gdbserver: LoongArch: Simplify code with register number macros
Move "enum loongarch_regnum" to gdb/arch/loongarch.h so that the macro definitions can be used in gdbserver/linux-loongarch-low.cc to simplify the code. Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> |
||
Yvan Roux
|
69b46464ba |
gdb/arm: Only stack S16..S31 when FPU registers are secure
The FPCCR.TS bit is used to identify if FPU registers are considered non-secure or secure. If they are secure, then callee saved registers (S16 to S31) are stacked on exception entry or otherwise skipped. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> Signed-off-by: Yvan Roux <yvan.roux@foss.st.com> |
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|
Youling Tang
|
e5ab6af52d |
gdbserver: Add LoongArch/Linux support
Implement LoongArch/Linux support, including XML target description handling based on features determined, GPR regset support, and software breakpoint handling. In the Linux kernel code of LoongArch, ptrace implements PTRACE_POKEUSR and PTRACE_PEEKUSR in the arch_ptrace function, so srv_linux_usrregs is set to yes. With this patch on LoongArch: $ make check-gdb TESTS="gdb.server/server-connect.exp" [...] # of expected passes 18 [...] Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> |
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John Baldwin
|
e8123c847f |
Tweak the std::hash<> specialization for aarch64_features.
Move the specialization into an explicit std namespace to workaround a bug in older compilers. GCC 6.4.1 at least fails to compile the previous version with the following error: gdb/arch/aarch64.h:48:13: error: specialization of 'template<class _Tp> struct std::hash' in different namespace [-fpermissive] struct std::hash<aarch64_features> |
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|
John Baldwin
|
0ee6b1c511 |
Use aarch64_features to describe register features in target descriptions.
Replace the sve bool member of aarch64_features with a vq member that holds the vector quotient. It is zero if SVE is not present. Add std::hash<> specialization and operator== so that aarch64_features can be used as a key with std::unordered_map<>. Change the various functions that create or lookup aarch64 target descriptions to accept a const aarch64_features object rather than a growing number of arguments. Replace the multi-dimension tdesc_aarch64_list arrays used to cache target descriptions with unordered_maps indexed by aarch64_feature. |
||
|
John Baldwin
|
414d5848bb | Add an aarch64-tls feature which includes the tpidr register. | ||
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John Baldwin
|
92d48a1e4e | Add an arm-tls feature which includes the tpidruro register from CP15. | ||
Christophe Lyon
|
9074667a85 |
gdb/arm: Define MSP and PSP registers for M-Profile
This patch removes the hardcoded access to PSP in arm_m_exception_cache() and relies on the definition with the XML descriptions. Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com> Signed-off-by: Christophe Lyon <christophe.lyon@arm.com> |
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Luis Machado
|
a01567f4f7 |
Enable ARMv8.1-m PACBTI support
This set of changes enable support for the ARMv8.1-m PACBTI extensions [1]. The goal of the PACBTI extensions is similar in scope to that of a-profile PAC/BTI (aarch64 only), but the underlying implementation is different. One important difference is that the pointer authentication code is stored in a separate register, thus we don't need to mask/unmask the return address from a function in order to produce a correct backtrace. The patch introduces the following modifications: - Extend the prologue analyser for 32-bit ARM to handle some instructions from ARMv8.1-m PACBTI: pac, aut, pacg, autg and bti. Also keep track of return address signing/authentication instructions. - Adds code to identify object file attributes that indicate the presence of ARMv8.1-m PACBTI (Tag_PAC_extension, Tag_BTI_extension, Tag_PACRET_use and Tag_BTI_use). - Adds support for DWARF pseudo-register RA_AUTH_CODE, as described in the aadwarf32 [2]. - Extends the dwarf unwinder to track the value of RA_AUTH_CODE. - Decorates backtraces with the "[PAC]" identifier when a frame has signed the return address. - Makes GDB aware of a new XML feature "org.gnu.gdb.arm.m-profile-pacbti". This feature is not included as an XML file on GDB's side because it is only supported for bare metal targets. - Additional documentation. [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension [2] https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst |
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H.J. Lu
|
0653f01479 |
gdb: Consolidate 32bit-pkeys.xml and 64bit-pkeys.xml
1. Since 32bit-pkeys.xml and 64bit-pkeys.xml are identical, consolidate them into a single keys.xml. 2. Enable PKU for x32 to fix: $ gdbserver :123456 x32-program ... .../gdbserver/regcache.cc:255: A problem internal to GDBserver has been detected . Unknown register pkru requested on Tiger Lake. |
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|
Tiezhu Yang
|
e74d08100d |
gdb: LoongArch: Add initial target description support
This commit adds initial target description support for LoongArch. Signed-off-by: Zhensong Liu <liuzhensong@loongson.cn> Signed-off-by: Qing zhang <zhangqing@loongson.cn> Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> |
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Joel Brobecker
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4a94e36819 |
Automatic Copyright Year update after running gdb/copyright.py
This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script. |
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Simon Marchi
|
557b4d7650 |
gdbsupport: make gdb_assert_not_reached accept a format string
Change gdb_assert_not_reached to accept a format string plus corresponding arguments. This allows giving more precise messages. Because the format string passed by the caller is prepended with a "%s:" to add the function name, the callers can no longer pass a translated string (`_(...)`). Make the gdb_assert_not_reached include the _(), just like the gdb_assert_fail macro just above. Change-Id: Id0cfda5a57979df6cdaacaba0d55dd91ae9efee7 |
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Luis Machado
|
37989733d8 |
Extend the prologue analyzer to handle the bti instruction
Handle the BTI instruction in the prologue analyzer. The patch handles all the variations of the BTI instruction. |
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Luis Machado
|
7fd8546853 |
[AArch64] Make gdbserver register set selection dynamic
The current register set selection mechanism for AArch64 is static, based on a pre-populated array of register sets. This means that we might potentially probe register sets that are not available. This is OK if the kernel errors out during ptrace, but probing the tag_ctl register, for example, does not result in a ptrace error if the kernel supports the tagged address ABI but not MTE (PR 28355). Making the register set selection dynamic, based on feature checks, solves this and simplifies the code a bit. It allows us to list all of the register sets only once, and pick and choose based on HWCAP/HWCAP2 or other properties. I plan to backport this fix to GDB 11 as well. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28355 |
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Srinath Parvathaneni
|
ae66a8f19e |
[ARM] Add support for M-profile MVE extension
This patch adds support for the M-profile MVE extension, which includes the
following:
- New M-profile XML feature m-profile-mve
- MVE vector predication status and control register (VPR)
- p0 pseudo register (contained in the VPR)
- q0 ~ q7 pseudo vector registers
- New feature bits
- Documentation update
Pseudo register p0 is the least significant bits of vpr and can be accessed
as $p0 or displayed through $vpr. For more information about the register
layout, please refer to [1].
The q0 ~ q7 registers map back to the d0 ~ d15 registers, two d registers
per q register.
The register dump looks like this:
(gdb) info reg all
r0 0x0 0
r1 0x0 0
r2 0x0 0
r3 0x0 0
r4 0x0 0
r5 0x0 0
r6 0x0 0
r7 0x0 0
r8 0x0 0
r9 0x0 0
r10 0x0 0
r11 0x0 0
r12 0x0 0
sp 0x0 0x0 <__Vectors>
lr 0xffffffff -1
pc 0xd0c 0xd0c <Reset_Handler>
xpsr 0x1000000 16777216
d0 0 (raw 0x0000000000000000)
d1 0 (raw 0x0000000000000000)
d2 0 (raw 0x0000000000000000)
d3 0 (raw 0x0000000000000000)
d4 0 (raw 0x0000000000000000)
d5 0 (raw 0x0000000000000000)
d6 0 (raw 0x0000000000000000)
d7 0 (raw 0x0000000000000000)
d8 0 (raw 0x0000000000000000)
d9 0 (raw 0x0000000000000000)
d10 0 (raw 0x0000000000000000)
d11 0 (raw 0x0000000000000000)
d12 0 (raw 0x0000000000000000)
d13 0 (raw 0x0000000000000000)
d14 0 (raw 0x0000000000000000)
d15 0 (raw 0x0000000000000000)
fpscr 0x0 0
vpr 0x0 [ P0=0 MASK01=0 MASK23=0 ]
s0 0 (raw 0x00000000)
s1 0 (raw 0x00000000)
s2 0 (raw 0x00000000)
s3 0 (raw 0x00000000)
s4 0 (raw 0x00000000)
s5 0 (raw 0x00000000)
s6 0 (raw 0x00000000)
s7 0 (raw 0x00000000)
s8 0 (raw 0x00000000)
s9 0 (raw 0x00000000)
s10 0 (raw 0x00000000)
s11 0 (raw 0x00000000)
s12 0 (raw 0x00000000)
s13 0 (raw 0x00000000)
s14 0 (raw 0x00000000)
s15 0 (raw 0x00000000)
s16 0 (raw 0x00000000)
s17 0 (raw 0x00000000)
s18 0 (raw 0x00000000)
s19 0 (raw 0x00000000)
s20 0 (raw 0x00000000)
s21 0 (raw 0x00000000)
s22 0 (raw 0x00000000)
s23 0 (raw 0x00000000)
s24 0 (raw 0x00000000)
s25 0 (raw 0x00000000)
s26 0 (raw 0x00000000)
s27 0 (raw 0x00000000)
s28 0 (raw 0x00000000)
s29 0 (raw 0x00000000)
s30 0 (raw 0x00000000)
s31 0 (raw 0x00000000)
q0 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q1 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q2 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q3 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q4 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q5 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q6 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
q7 {u8 = {0x0 <repeats 16 times>}, u16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u32 = {0x0, 0x0, 0x0, 0x0}, u64 = {0x0, 0x0}, f32 = {0x0, 0x0, 0x0, 0x0}, f64 = {0x0, 0x0}}
p0 0x0 0
Built and regtested with a simulator.
[1] https://developer.arm.com/documentation/ddi0553/bn
Co-Authored-By: Luis Machado <luis.machado@linaro.org>
|
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Luis Machado
|
4d224f4a58 |
[ARM] Refactor some constants
In preparation for the MVE extension patch, this one refactors some of the register-related constants we have for ARM. Basically I'm separating counting constants from numbering constants. For example, ARM_A1_REGNUM is a numbering constant, whereas ARM_NUM_ARG_REGS is a counting constant. |
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Andrew Burgess
|
96f842cbdb |
gdb/riscv: add support for vector registers in target descriptions
This commit adds support to RISC-V GDB for vector registers in the incoming target description. The vector registers should be described in a feature called "org.gnu.gdb.riscv.vector", and should contain the register v0 to v31. There's no restriction on the size or type of these registers, so the target description can set these up as it requires. However, if the target feature is present then all of the registers must be present, and they must all be the same size, these requirements are, I believe, inline with the RISC-V vector extension. The DWARF register numbers for the vector registers have been added, and the code to map between GDB's internal numbering and the DWARF numbering has been updated. I have not yet added a feature/riscv/*.xml file for the vector extension, the consequence of this is that we can't, right now, detect vector registers on a native target, this patch is all about supporting vectors on a remote target. It is worth noting that I don't actually have access to a RISC-V target with vectors, so the only testing that this patch has had has been done using 'set tdesc filename ....' to load a target description to which I have manually added the vector feature. This has shown that the vector register feature can be successfully parsed, and that the registers show up in the expected register groups. Additionally, the RISC-V vector extension is currently at v0.10, which is also the v1.0 draft release. However, this extension is not yet finalised. It is possible (but unlikely I think) that the register set could change between now and the final release of the vector extension. If this were to happen then we would potentially end up changing the requirements for the new org.gnu.gdb.riscv.vector feature. I really don't think it is likely that the register set will change this late in the process, and even if it did, changing the feature requirements will not be a problem as far as I am concerned (when the alternative is GDB just continues without this feature for now). gdb/ChangeLog: * NEWS: Mention new target feature name. * arch/riscv.c (riscv_create_target_description): GDB doesn't currently create target descriptions containing vector registers. * arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member variable. <operator==>: Also compare vlen. <hash>: Also include vlen. * riscv-tdep.c (riscv_feature_name_vector): New static global. (struct riscv_vector_feature): New struct. (riscv_vector_feature): New static global. (riscv_register_reggroup_p): Ensure vector registers are part of the 'all' group, and part of the 'vector' group. (riscv_dwarf_reg_to_regnum): Handle vector registers. (riscv_gdbarch_init): Check vector register feature. * riscv-tdep.h: Add vector registers to GDB's internal register numbers, and to the DWARF register numbers. gdb/doc/ChangeLog: * gdb.texinfo (RISC-V Features): Mention vector register feature. |
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Luis Machado
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0746f49b1d |
[AArch64] Fix off-by-one when calculating tag granules.
When we want to fetch tags from a memory range, the last address in that range is not included. There is a off-by-one error in aarch64_mte_get_tag_granules, which this patch fixes. gdb/ChangeLog: 2021-05-13 Luis Machado <luis.machado@linaro.org> * arch/aarch64-mte-linux.c (aarch64_mte_get_tag_granules): Don't include the last address in the range. |
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Luis Machado
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cf44c9fa1b |
AArch64: Report tag violation error information
Whenever a memory tag violation occurs, we get a SIGSEGV. Additional information can be obtained through the siginfo data structure. For AArch64 the Linux kernel may expose the fault address and tag information, if we have a synchronous event. Otherwise there is no fault address available. The synchronous event looks like this: -- (gdb) continue Continuing. Program received signal SIGSEGV, Segmentation fault Memory tag violation while accessing address 0x0500fffff7ff8000 Allocation tag 0x1. Logical tag 0x5 -- The asynchronous event looks like this: -- (gdb) continue Continuing. Program received signal SIGSEGV, Segmentation fault Memory tag violation Fault address unavailable. -- gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-tdep.c (aarch64_linux_report_signal_info): New function. (aarch64_linux_init_abi): Register aarch64_linux_report_signal_info as the report_signal_info hook. * arch/aarch64-linux.h (SEGV_MTEAERR): Define. (SEGV_MTESERR): Define. |
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Luis Machado
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c7782e50b1 |
AArch64: Implement the memory tagging gdbarch hooks
This patch implements the memory tagging gdbarch hooks for AArch64, for the MTE feature. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-tdep.c: Include target.h, arch-utils.h, value.h. (aarch64_mte_get_atag, aarch64_linux_tagged_address_p) (aarch64_linux_memtag_mismatch_p, aarch64_linux_set_memtags) (aarch64_linux_get_memtag, aarch64_linux_memtag_to_string): New functions. (aarch64_linux_init_abi): Initialize MTE-related gdbarch hooks. * arch/aarch64-mte-linux.c (aarch64_mte_make_ltag_bits) (aarch64_mte_make_ltag, aarch64_linux_set_ltag) (aarch64_linux_get_ltag): New functions. * arch/aarch64-mte-linux.h (AARCH64_MTE_LOGICAL_TAG_START_BIT) (AARCH64_MTE_LOGICAL_MAX_VALUE): Define. (aarch64_mte_make_ltag_bits, aarch64_mte_make_ltag) (aarch64_mte_set_ltag, aarch64_mte_get_ltag): New prototypes. |
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Luis Machado
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4601818e8c |
AArch64: Implement memory tagging target methods for AArch64
The patch implements the memory tagging target hooks for AArch64, so we can handle MTE. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * Makefile.in (ALL_64_TARGET_OBS): Add arch/aarch64-mte-linux.o. (HFILES_NO_SRCDIR): Add arch/aarch64-mte-linux.h and nat/aarch64-mte-linux-ptrace.h. * aarch64-linux-nat.c: Include nat/aarch64-mte-linux-ptrace.h. (aarch64_linux_nat_target) <supports_memory_tagging>: New method override. <fetch_memtags>: New method override. <store_memtags>: New method override. (aarch64_linux_nat_target::supports_memory_tagging): New method. (aarch64_linux_nat_target::fetch_memtags): New method. (aarch64_linux_nat_target::store_memtags): New method. * arch/aarch64-mte-linux.c: New file. * arch/aarch64-mte-linux.h: Include gdbsupport/common-defs.h. (AARCH64_MTE_GRANULE_SIZE): Define. (aarch64_memtag_type): New enum. (aarch64_mte_get_tag_granules): New prototype. * configure.nat (NATDEPFILES): Add nat/aarch64-mte-linux-ptrace.o. * configure.tgt (aarch64*-*-linux*): Add arch/aarch64-mte-linux.o. * nat/aarch64-mte-linux-ptrace.c: New file. * nat/aarch64-mte-linux-ptrace.h: New file. |
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Luis Machado
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5e984dbf35 |
AArch64: Add MTE register set support for GDB and gdbserver
AArch64 MTE support in the Linux kernel exposes a new register through ptrace. This patch adds the required code to support it. include/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-nat.c (fetch_mteregs_from_thread): New function. (store_mteregs_to_thread): New function. (aarch64_linux_nat_target::fetch_registers): Update to call fetch_mteregs_from_thread. (aarch64_linux_nat_target::store_registers): Update to call store_mteregs_to_thread. * aarch64-tdep.c (aarch64_mte_register_names): New struct. (aarch64_cannot_store_register): Handle MTE registers. (aarch64_gdbarch_init): Initialize and setup MTE registers. * aarch64-tdep.h (gdbarch_tdep) <mte_reg_base>: New field. <has_mte>: New method. * arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define. gdbserver/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * linux-aarch64-low.cc (aarch64_fill_mteregset): New function. (aarch64_store_mteregset): New function. (aarch64_regsets): Add MTE register set entry. (aarch64_sve_regsets): Add MTE register set entry. |
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Luis Machado
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c1bd443b4d |
AArch64: Add target description/feature for MTE registers
This patch adds a target description and feature "mte" for aarch64. It includes one new register, tag_ctl, that can be used to configure the tag generation rules and sync/async modes. It is 64-bit in size. The patch also adjusts the code that creates the target descriptions at runtime based on CPU feature checks. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-nat.c (aarch64_linux_nat_target::read_description): Take MTE flag into account. Slight refactor to hwcap flag checking. * aarch64-linux-tdep.c (aarch64_linux_core_read_description): Likewise. * aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for MTE. (aarch64_read_description): Add mte_p parameter and update to use it. Update the documentation. (aarch64_gdbarch_init): Update call to aarch64_read_description. * aarch64-tdep.h (aarch64_read_description): Add mte_p parameter. * arch/aarch64.c: Include ../features/aarch64-mte.c. (aarch64_create_target_description): Add mte_p parameter and update the code to use it. * arch/aarch64.h (aarch64_create_target_description): Add mte_p parameter. * features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml. * features/aarch64-mte.c: New file, generated. * features/aarch64-mte.xml: New file. gdbserver/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to aarch64_linux_read_description. (initialize_low_tracepoint): Likewise. * linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag into account. * linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension for MTE. (aarch64_linux_read_description): Add mte_p parameter and update to use it. * linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p parameter. |
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Luis Machado
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0424512519 |
AArch64: Add MTE CPU feature check support
This patch is a preparation for the next patches implementing MTE. It just adds a HWCAP2 constant for MTE, creates a new generic arch/aarch64-mte-linux.h file and includes that file in the source files that will use it. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * Makefile.in (HFILES_NO_SRCDIR): Add arch/aarch64-mte-linux.h. * aarch64-linux-nat.c: Include arch/aarch64-mte-linux.h. * aarch64-linux-tdep.c: Likewise * arch/aarch64-mte-linux.h: New file. gdbserver/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * linux-aarch64-low.cc: Include arch/aarch64-mte-linux.h. |
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Matthew Malcomson
|
807f647cac |
GDB: aarch64: Add ability to displaced step over a BR/BLR instruction
Enable displaced stepping over a BR/BLR instruction
Displaced stepping over an instruction executes a instruction in a
scratch area and then manually fixes up the PC address to leave
execution where it would have been if the instruction were in its
original location.
The BR instruction does not need modification in order to run correctly
at a different address, but the displaced step fixup method should not
manually adjust the PC since the BR instruction sets that value already.
The BLR instruction should also avoid such a fixup, but must also have
the link register modified to point to just after the original code
location rather than back to the scratch location.
This patch adds the above functionality.
We add this functionality by modifying aarch64_displaced_step_others
rather than by adding a new visitor method to aarch64_insn_visitor.
We choose this since it seems that visitor approach is designed
specifically for PC relative instructions (which must always be modified
when executed in a different location).
It seems that the BR and BLR instructions are more like the RET
instruction which is already handled specially in
aarch64_displaced_step_others.
This also means the gdbserver code to relocate an instruction when
creating a fast tracepoint does not need to be modified, since nothing
special is needed for the BR and BLR instructions there.
Regression tests showed nothing untoward on native aarch64 (though it
took a while for me to get the testcase to account for PIE).
------#####
Original observed (mis)behaviour before was that displaced stepping over
a BR or BLR instruction would not execute the function they called.
Most easily seen by putting a breakpoint with a condition on such an
instruction and a print statement in the functions they called.
When run with the breakpoint enabled the function is not called and
"numargs called" is not printed.
When run with the breakpoint disabled the function is called and the
message is printed.
--- GDB Session
~ [15:57:14] % gdb ../using-blr
Reading symbols from ../using-blr...done.
(gdb) disassemble blr_call_value
Dump of assembler code for function blr_call_value:
...
0x0000000000400560 <+28>: blr x2
...
0x00000000004005b8 <+116>: ret
End of assembler dump.
(gdb) break *0x0000000000400560
Breakpoint 1 at 0x400560: file ../using-blr.c, line 22.
(gdb) condition 1 10 == 0
(gdb) run
Starting program: /home/matmal01/using-blr
[Inferior 1 (process 33279) exited with code 012]
(gdb) disable 1
(gdb) run
Starting program: /home/matmal01/using-blr
numargs called
[Inferior 1 (process 33289) exited with code 012]
(gdb)
Test program:
---- using-blr ----
\#include <stdio.h>
typedef int (foo) (int, int);
typedef void (bar) (int, int);
struct sls_testclass {
foo *x;
bar *y;
int left;
int right;
};
__attribute__ ((noinline))
int blr_call_value (struct sls_testclass x)
{
int retval = x.x(x.left, x.right);
if (retval % 10)
return 100;
return 9;
}
__attribute__ ((noinline))
int blr_call (struct sls_testclass x)
{
x.y(x.left, x.right);
if (x.left % 10)
return 100;
return 9;
}
int
numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("numargs called\n");
return 10;
}
void
altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("altfunc called\n");
}
int main(int argc, char **argv)
{
struct sls_testclass x = { .x = numargs, .y = altfunc, .left = 1, .right = 2 };
if (argc > 2)
{
blr_call (x);
}
else
blr_call_value (x);
return 10;
}
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Simon Marchi
|
c6185dce03 |
gdb: convert aarch64 to new-style debug macros
I haven't tried this on an actual aarch64 machine, but I am able to
exercise it like this:
(gdb) set debug aarch64
(gdb) maintenance selftest aa
Running selftest aarch64-analyze-prologue.
[aarch64] aarch64_analyze_prologue: prologue analysis gave up addr=0x14 opcode=0xf94013e0
Running selftest aarch64-process-record.
Ran 2 unit tests, 0 failed
gdb/ChangeLog:
* arch/aarch64-insn.h (aarch64_debug_printf): New.
* arch/aarch64-insn.c: Use aarch64_debug_printf.
* aarch64-tdep.c: Use aarch64_debug_printf.
Change-Id: Ifdb40e2816ab8e55a9aabb066d1833d9b5a46094
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Joel Brobecker
|
3666a04883 |
Update copyright year range in all GDB files
This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
|
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Luis Machado
|
6afcd2d416 |
[AArch64] SVE/FPSIMD fixup for big endian
The FPSIMD dump in signal frames and ptrace FPSIMD dump in the SVE context structure follows the target endianness, whereas the SVE dumps are endianness-independent (LE). Therefore, when the system is in BE mode, we need to reverse the bytes for the FPSIMD data. Given the V registers are larger than 64-bit, I've added a way for value bytes to be set, as opposed to passing a 64-bit fixed quantity. This fits nicely with the unwinding *_got_bytes function and makes the trad-frame more flexible and capable of saving larger registers. The memory for the bytes is allocated via the frame obstack, so it gets freed after we're done inspecting the frame. gdb/ChangeLog: 2020-12-10 Luis Machado <luis.machado@linaro.org> * aarch64-linux-tdep.c (aarch64_linux_restore_vreg) New function. (aarch64_linux_sigframe_init): Call aarch64_linux_restore_vreg. * aarch64-tdep.h (V_REGISTER_SIZE): Move to ... * arch/aarch64.h: ... here. * nat/aarch64-sve-linux-ptrace.c: Include endian.h. (aarch64_maybe_swab128): New function. (aarch64_sve_regs_copy_to_reg_buf) (aarch64_sve_regs_copy_from_reg_buf): Adjust FPSIMD entries. * trad-frame.c (trad_frame_reset_saved_regs): Initialize the data field. (TF_REG_VALUE_BYTES): New enum value. (trad_frame_value_bytes_p): New function. (trad_frame_set_value_bytes): New function. (trad_frame_set_reg_value_bytes): New function. (trad_frame_get_prev_register): Handle register values saved as bytes. * trad-frame.h (trad_frame_set_reg_value_bytes): New prototype. (struct trad_frame_saved_reg) <data>: New field. (trad_frame_set_value_bytes): New prototype. (trad_frame_value_bytes_p): New prototype. |
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Luis Machado
|
5382f97180 |
Fix shifting of negative value
When UBSan is enabled, I noticed runtime errors complaining of shifting of negative numbers. This patch fixes this by reusing existing macros from the ARM port. It also removes unused macros from AArch64's port. gdb/ChangeLog: 2020-12-04 Luis Machado <luis.machado@linaro.org> * aarch64-tdep.c (submask, bit, bits): Remove. * arch/aarch64-insn.c (extract_signed_bitfield): Remove. (aarch64_decode_adr, aarch64_decode_b aarch64_decode_bcond) (aarch64_decode_cb, aarch64_decode_tb) (aarch64_decode_ldr_literal): Use sbits to extract a signed immediate. * arch/aarch64-insn.h (submask, bits, bit, sbits): New macros. |
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Andrew Burgess
|
2542804022 |
gdb/riscv: rewrite target description validation, add rv32e support
This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare. |
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Simon Marchi
|
dda83cd783 |
gdb, gdbserver, gdbsupport: fix leading space vs tabs issues
Many spots incorrectly use only spaces for indentation (for example, there are a lot of spots in ada-lang.c). I've always found it awkward when I needed to edit one of these spots: do I keep the original wrong indentation, or do I fix it? What if the lines around it are also wrong, do I fix them too? I probably don't want to fix them in the same patch, to avoid adding noise to my patch. So I propose to fix as much as possible once and for all (hopefully). One typical counter argument for this is that it makes code archeology more difficult, because git-blame will show this commit as the last change for these lines. My counter counter argument is: when git-blaming, you often need to do "blame the file at the parent commit" anyway, to go past some other refactor that touched the line you are interested in, but is not the change you are looking for. So you already need a somewhat efficient way to do this. Using some interactive tool, rather than plain git-blame, makes this trivial. For example, I use "tig blame <file>", where going back past the commit that changed the currently selected line is one keystroke. It looks like Magit in Emacs does it too (though I've never used it). Web viewers of Github and Gitlab do it too. My point is that it won't really make archeology more difficult. The other typical counter argument is that it will cause conflicts with existing patches. That's true... but it's a one time cost, and those are not conflicts that are difficult to resolve. I have also tried "git rebase --ignore-whitespace", it seems to work well. Although that will re-introduce the faulty indentation, so one needs to take care of fixing the indentation in the patch after that (which is easy). gdb/ChangeLog: * aarch64-linux-tdep.c: Fix indentation. * aarch64-ravenscar-thread.c: Fix indentation. * aarch64-tdep.c: Fix indentation. * aarch64-tdep.h: Fix indentation. * ada-lang.c: Fix indentation. * ada-lang.h: Fix indentation. * ada-tasks.c: Fix indentation. * ada-typeprint.c: Fix indentation. * ada-valprint.c: Fix indentation. * ada-varobj.c: Fix indentation. * addrmap.c: Fix indentation. * addrmap.h: Fix indentation. * agent.c: Fix indentation. * aix-thread.c: Fix indentation. * alpha-bsd-nat.c: Fix indentation. * alpha-linux-tdep.c: Fix indentation. * alpha-mdebug-tdep.c: Fix indentation. * alpha-nbsd-tdep.c: Fix indentation. * alpha-obsd-tdep.c: Fix indentation. * alpha-tdep.c: Fix indentation. * amd64-bsd-nat.c: Fix indentation. * amd64-darwin-tdep.c: Fix indentation. * amd64-linux-nat.c: Fix indentation. * amd64-linux-tdep.c: Fix indentation. * amd64-nat.c: Fix indentation. * amd64-obsd-tdep.c: Fix indentation. * amd64-tdep.c: Fix indentation. * amd64-windows-tdep.c: Fix indentation. * annotate.c: Fix indentation. * arc-tdep.c: Fix indentation. * arch-utils.c: Fix indentation. * arch/arm-get-next-pcs.c: Fix indentation. * arch/arm.c: Fix indentation. * arm-linux-nat.c: Fix indentation. * arm-linux-tdep.c: Fix indentation. * arm-nbsd-tdep.c: Fix indentation. * arm-pikeos-tdep.c: Fix indentation. * arm-tdep.c: Fix indentation. * arm-tdep.h: Fix indentation. * arm-wince-tdep.c: Fix indentation. * auto-load.c: Fix indentation. * auxv.c: Fix indentation. * avr-tdep.c: Fix indentation. * ax-gdb.c: Fix indentation. * ax-general.c: Fix indentation. * bfin-linux-tdep.c: Fix indentation. * block.c: Fix indentation. * block.h: Fix indentation. * blockframe.c: Fix indentation. * bpf-tdep.c: Fix indentation. * break-catch-sig.c: Fix indentation. * break-catch-syscall.c: Fix indentation. * break-catch-throw.c: Fix indentation. * breakpoint.c: Fix indentation. * breakpoint.h: Fix indentation. * bsd-uthread.c: Fix indentation. * btrace.c: Fix indentation. * build-id.c: Fix indentation. * buildsym-legacy.h: Fix indentation. * buildsym.c: Fix indentation. * c-typeprint.c: Fix indentation. * c-valprint.c: Fix indentation. * c-varobj.c: Fix indentation. * charset.c: Fix indentation. * cli/cli-cmds.c: Fix indentation. * cli/cli-decode.c: Fix indentation. * cli/cli-decode.h: Fix indentation. * cli/cli-script.c: Fix indentation. * cli/cli-setshow.c: Fix indentation. * coff-pe-read.c: Fix indentation. * coffread.c: Fix indentation. * compile/compile-cplus-types.c: Fix indentation. * compile/compile-object-load.c: Fix indentation. * compile/compile-object-run.c: Fix indentation. * completer.c: Fix indentation. * corefile.c: Fix indentation. * corelow.c: Fix indentation. * cp-abi.h: Fix indentation. * cp-namespace.c: Fix indentation. * cp-support.c: Fix indentation. * cp-valprint.c: Fix indentation. * cris-linux-tdep.c: Fix indentation. * cris-tdep.c: Fix indentation. * darwin-nat-info.c: Fix indentation. * darwin-nat.c: Fix indentation. * darwin-nat.h: Fix indentation. * dbxread.c: Fix indentation. * dcache.c: Fix indentation. * disasm.c: Fix indentation. * dtrace-probe.c: Fix indentation. * dwarf2/abbrev.c: Fix indentation. * dwarf2/attribute.c: Fix indentation. * dwarf2/expr.c: Fix indentation. * dwarf2/frame.c: Fix indentation. * dwarf2/index-cache.c: Fix indentation. * dwarf2/index-write.c: Fix indentation. * dwarf2/line-header.c: Fix indentation. * dwarf2/loc.c: Fix indentation. * dwarf2/macro.c: Fix indentation. * dwarf2/read.c: Fix indentation. * dwarf2/read.h: Fix indentation. * elfread.c: Fix indentation. * eval.c: Fix indentation. * event-top.c: Fix indentation. * exec.c: Fix indentation. * exec.h: Fix indentation. * expprint.c: Fix indentation. * f-lang.c: Fix indentation. * f-typeprint.c: Fix indentation. * f-valprint.c: Fix indentation. * fbsd-nat.c: Fix indentation. * fbsd-tdep.c: Fix indentation. * findvar.c: Fix indentation. * fork-child.c: Fix indentation. * frame-unwind.c: Fix indentation. * frame-unwind.h: Fix indentation. * frame.c: Fix indentation. * frv-linux-tdep.c: Fix indentation. * frv-tdep.c: Fix indentation. * frv-tdep.h: Fix indentation. * ft32-tdep.c: Fix indentation. * gcore.c: Fix indentation. * gdb_bfd.c: Fix indentation. * gdbarch.sh: Fix indentation. * gdbarch.c: Re-generate * gdbarch.h: Re-generate. * gdbcore.h: Fix indentation. * gdbthread.h: Fix indentation. * gdbtypes.c: Fix indentation. * gdbtypes.h: Fix indentation. * glibc-tdep.c: Fix indentation. * gnu-nat.c: Fix indentation. * gnu-nat.h: Fix indentation. * gnu-v2-abi.c: Fix indentation. * gnu-v3-abi.c: Fix indentation. * go32-nat.c: Fix indentation. * guile/guile-internal.h: Fix indentation. * guile/scm-cmd.c: Fix indentation. * guile/scm-frame.c: Fix indentation. * guile/scm-iterator.c: Fix indentation. * guile/scm-math.c: Fix indentation. * guile/scm-ports.c: Fix indentation. * guile/scm-pretty-print.c: Fix indentation. * guile/scm-value.c: Fix indentation. * h8300-tdep.c: Fix indentation. * hppa-linux-nat.c: Fix indentation. * hppa-linux-tdep.c: Fix indentation. * hppa-nbsd-nat.c: Fix indentation. * hppa-nbsd-tdep.c: Fix indentation. * hppa-obsd-nat.c: Fix indentation. * hppa-tdep.c: Fix indentation. * hppa-tdep.h: Fix indentation. * i386-bsd-nat.c: Fix indentation. * i386-darwin-nat.c: Fix indentation. * i386-darwin-tdep.c: Fix indentation. * i386-dicos-tdep.c: Fix indentation. * i386-gnu-nat.c: Fix indentation. * i386-linux-nat.c: Fix indentation. * i386-linux-tdep.c: Fix indentation. * i386-nto-tdep.c: Fix indentation. * i386-obsd-tdep.c: Fix indentation. * i386-sol2-nat.c: Fix indentation. * i386-tdep.c: Fix indentation. * i386-tdep.h: Fix indentation. * i386-windows-tdep.c: Fix indentation. * i387-tdep.c: Fix indentation. * i387-tdep.h: Fix indentation. * ia64-libunwind-tdep.c: Fix indentation. * ia64-libunwind-tdep.h: Fix indentation. * ia64-linux-nat.c: Fix indentation. * ia64-linux-tdep.c: Fix indentation. * ia64-tdep.c: Fix indentation. * ia64-tdep.h: Fix indentation. * ia64-vms-tdep.c: Fix indentation. * infcall.c: Fix indentation. * infcmd.c: Fix indentation. * inferior.c: Fix indentation. * infrun.c: Fix indentation. * iq2000-tdep.c: Fix indentation. * language.c: Fix indentation. * linespec.c: Fix indentation. * linux-fork.c: Fix indentation. * linux-nat.c: Fix indentation. * linux-tdep.c: Fix indentation. * linux-thread-db.c: Fix indentation. * lm32-tdep.c: Fix indentation. * m2-lang.c: Fix indentation. * m2-typeprint.c: Fix indentation. * m2-valprint.c: Fix indentation. * m32c-tdep.c: Fix indentation. * m32r-linux-tdep.c: Fix indentation. * m32r-tdep.c: Fix indentation. * m68hc11-tdep.c: Fix indentation. * m68k-bsd-nat.c: Fix indentation. * m68k-linux-nat.c: Fix indentation. * m68k-linux-tdep.c: Fix indentation. * m68k-tdep.c: Fix indentation. * machoread.c: Fix indentation. * macrocmd.c: Fix indentation. * macroexp.c: Fix indentation. * macroscope.c: Fix indentation. * macrotab.c: Fix indentation. * macrotab.h: Fix indentation. * main.c: Fix indentation. * mdebugread.c: Fix indentation. * mep-tdep.c: Fix indentation. * mi/mi-cmd-catch.c: Fix indentation. * mi/mi-cmd-disas.c: Fix indentation. * mi/mi-cmd-env.c: Fix indentation. * mi/mi-cmd-stack.c: Fix indentation. * mi/mi-cmd-var.c: Fix indentation. * mi/mi-cmds.c: Fix indentation. * mi/mi-main.c: Fix indentation. * mi/mi-parse.c: Fix indentation. * microblaze-tdep.c: Fix indentation. * minidebug.c: Fix indentation. * minsyms.c: Fix indentation. * mips-linux-nat.c: Fix indentation. * mips-linux-tdep.c: Fix indentation. * mips-nbsd-tdep.c: Fix indentation. * mips-tdep.c: Fix indentation. * mn10300-linux-tdep.c: Fix indentation. * mn10300-tdep.c: Fix indentation. * moxie-tdep.c: Fix indentation. * msp430-tdep.c: Fix indentation. * namespace.h: Fix indentation. * nat/fork-inferior.c: Fix indentation. * nat/gdb_ptrace.h: Fix indentation. * nat/linux-namespaces.c: Fix indentation. * nat/linux-osdata.c: Fix indentation. * nat/netbsd-nat.c: Fix indentation. * nat/x86-dregs.c: Fix indentation. * nbsd-nat.c: Fix indentation. * nbsd-tdep.c: Fix indentation. * nios2-linux-tdep.c: Fix indentation. * nios2-tdep.c: Fix indentation. * nto-procfs.c: Fix indentation. * nto-tdep.c: Fix indentation. * objfiles.c: Fix indentation. * objfiles.h: Fix indentation. * opencl-lang.c: Fix indentation. * or1k-tdep.c: Fix indentation. * osabi.c: Fix indentation. * osabi.h: Fix indentation. * osdata.c: Fix indentation. * p-lang.c: Fix indentation. * p-typeprint.c: Fix indentation. * p-valprint.c: Fix indentation. * parse.c: Fix indentation. * ppc-linux-nat.c: Fix indentation. * ppc-linux-tdep.c: Fix indentation. * ppc-nbsd-nat.c: Fix indentation. * ppc-nbsd-tdep.c: Fix indentation. * ppc-obsd-nat.c: Fix indentation. * ppc-ravenscar-thread.c: Fix indentation. * ppc-sysv-tdep.c: Fix indentation. * ppc64-tdep.c: Fix indentation. * printcmd.c: Fix indentation. * proc-api.c: Fix indentation. * producer.c: Fix indentation. * producer.h: Fix indentation. * prologue-value.c: Fix indentation. * prologue-value.h: Fix indentation. * psymtab.c: Fix indentation. * python/py-arch.c: Fix indentation. * python/py-bpevent.c: Fix indentation. * python/py-event.c: Fix indentation. * python/py-event.h: Fix indentation. * python/py-finishbreakpoint.c: Fix indentation. * python/py-frame.c: Fix indentation. * python/py-framefilter.c: Fix indentation. * python/py-inferior.c: Fix indentation. * python/py-infthread.c: Fix indentation. * python/py-objfile.c: Fix indentation. * python/py-prettyprint.c: Fix indentation. * python/py-registers.c: Fix indentation. * python/py-signalevent.c: Fix indentation. * python/py-stopevent.c: Fix indentation. * python/py-stopevent.h: Fix indentation. * python/py-threadevent.c: Fix indentation. * python/py-tui.c: Fix indentation. * python/py-unwind.c: Fix indentation. * python/py-value.c: Fix indentation. * python/py-xmethods.c: Fix indentation. * python/python-internal.h: Fix indentation. * python/python.c: Fix indentation. * ravenscar-thread.c: Fix indentation. * record-btrace.c: Fix indentation. * record-full.c: Fix indentation. * record.c: Fix indentation. * reggroups.c: Fix indentation. * regset.h: Fix indentation. * remote-fileio.c: Fix indentation. * remote.c: Fix indentation. * reverse.c: Fix indentation. * riscv-linux-tdep.c: Fix indentation. * riscv-ravenscar-thread.c: Fix indentation. * riscv-tdep.c: Fix indentation. * rl78-tdep.c: Fix indentation. * rs6000-aix-tdep.c: Fix indentation. * rs6000-lynx178-tdep.c: Fix indentation. * rs6000-nat.c: Fix indentation. * rs6000-tdep.c: Fix indentation. * rust-lang.c: Fix indentation. * rx-tdep.c: Fix indentation. * s12z-tdep.c: Fix indentation. * s390-linux-tdep.c: Fix indentation. * score-tdep.c: Fix indentation. * ser-base.c: Fix indentation. * ser-mingw.c: Fix indentation. * ser-uds.c: Fix indentation. * ser-unix.c: Fix indentation. * serial.c: Fix indentation. * sh-linux-tdep.c: Fix indentation. * sh-nbsd-tdep.c: Fix indentation. * sh-tdep.c: Fix indentation. * skip.c: Fix indentation. * sol-thread.c: Fix indentation. * solib-aix.c: Fix indentation. * solib-darwin.c: Fix indentation. * solib-frv.c: Fix indentation. * solib-svr4.c: Fix indentation. * solib.c: Fix indentation. * source.c: Fix indentation. * sparc-linux-tdep.c: Fix indentation. * sparc-nbsd-tdep.c: Fix indentation. * sparc-obsd-tdep.c: Fix indentation. * sparc-ravenscar-thread.c: Fix indentation. * sparc-tdep.c: Fix indentation. * sparc64-linux-tdep.c: Fix indentation. * sparc64-nbsd-tdep.c: Fix indentation. * sparc64-obsd-tdep.c: Fix indentation. * sparc64-tdep.c: Fix indentation. * stabsread.c: Fix indentation. * stack.c: Fix indentation. * stap-probe.c: Fix indentation. * stubs/ia64vms-stub.c: Fix indentation. * stubs/m32r-stub.c: Fix indentation. * stubs/m68k-stub.c: Fix indentation. * stubs/sh-stub.c: Fix indentation. * stubs/sparc-stub.c: Fix indentation. * symfile-mem.c: Fix indentation. * symfile.c: Fix indentation. * symfile.h: Fix indentation. * symmisc.c: Fix indentation. * symtab.c: Fix indentation. * symtab.h: Fix indentation. * target-float.c: Fix indentation. * target.c: Fix indentation. * target.h: Fix indentation. * tic6x-tdep.c: Fix indentation. * tilegx-linux-tdep.c: Fix indentation. * tilegx-tdep.c: Fix indentation. * top.c: Fix indentation. * tracefile-tfile.c: Fix indentation. * tracepoint.c: Fix indentation. * tui/tui-disasm.c: Fix indentation. * tui/tui-io.c: Fix indentation. * tui/tui-regs.c: Fix indentation. * tui/tui-stack.c: Fix indentation. * tui/tui-win.c: Fix indentation. * tui/tui-winsource.c: Fix indentation. * tui/tui.c: Fix indentation. * typeprint.c: Fix indentation. * ui-out.h: Fix indentation. * unittests/copy_bitwise-selftests.c: Fix indentation. * unittests/memory-map-selftests.c: Fix indentation. * utils.c: Fix indentation. * v850-tdep.c: Fix indentation. * valarith.c: Fix indentation. * valops.c: Fix indentation. * valprint.c: Fix indentation. * valprint.h: Fix indentation. * value.c: Fix indentation. * value.h: Fix indentation. * varobj.c: Fix indentation. * vax-tdep.c: Fix indentation. * windows-nat.c: Fix indentation. * windows-tdep.c: Fix indentation. * xcoffread.c: Fix indentation. * xml-syscall.c: Fix indentation. * xml-tdesc.c: Fix indentation. * xstormy16-tdep.c: Fix indentation. * xtensa-config.c: Fix indentation. * xtensa-linux-nat.c: Fix indentation. * xtensa-linux-tdep.c: Fix indentation. * xtensa-tdep.c: Fix indentation. gdbserver/ChangeLog: * ax.cc: Fix indentation. * dll.cc: Fix indentation. * inferiors.h: Fix indentation. * linux-low.cc: Fix indentation. * linux-nios2-low.cc: Fix indentation. * linux-ppc-ipa.cc: Fix indentation. * linux-ppc-low.cc: Fix indentation. * linux-x86-low.cc: Fix indentation. * linux-xtensa-low.cc: Fix indentation. * regcache.cc: Fix indentation. * server.cc: Fix indentation. * tracepoint.cc: Fix indentation. gdbsupport/ChangeLog: * common-exceptions.h: Fix indentation. * event-loop.cc: Fix indentation. * fileio.cc: Fix indentation. * filestuff.cc: Fix indentation. * gdb-dlfcn.cc: Fix indentation. * gdb_string_view.h: Fix indentation. * job-control.cc: Fix indentation. * signals.cc: Fix indentation. Change-Id: I4bad7ae6be0fbe14168b8ebafb98ffe14964a695 |
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Andrew Burgess
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bbb826f5e9 |
gdb: Delay releasing target_desc_up in more cases
After commit:
commit
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Andrew Burgess
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51a948fdf0 |
gdb: Have allocate_target_description return a unique_ptr
Update allocate_target_description to return a target_desc_up, a specialisation of unique_ptr. This commit does not attempt to make use of the unique_ptr in the best possible way, in almost all cases we immediately release the pointer from within the unique_ptr and then continue as before. There are a few places where it was easy to handle the unique_ptr, and in these cases I've done that. Everything under gdb/features/* is auto-regenerated. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/aarch32.c (aarch32_create_target_description): Release unique_ptr returned from allocate_target_description. * arch/aarch64.c (aarch64_create_target_description): Likewise. * arch/amd64.c (amd64_create_target_description): Likewise. * arch/arc.c (arc_create_target_description): Likewise. * arch/arm.c (arm_create_target_description): Likewise. * arch/i386.c (i386_create_target_description): Likewise. * arch/riscv.c (riscv_create_target_description): Update return type. Handle allocate_target_description returning a unique_ptr. (riscv_lookup_target_description): Update to handle unique_ptr. * arch/tic6x.c (tic6x_create_target_description): Release unique_ptr returned from allocate_target_description. * features/microblaze-with-stack-protect.c: Regenerate. * features/microblaze.c: Regenerate. * features/mips-dsp-linux.c: Regenerate. * features/mips-linux.c: Regenerate. * features/mips64-dsp-linux.c: Regenerate. * features/mips64-linux.c: Regenerate. * features/nds32.c: Regenerate. * features/nios2.c: Regenerate. * features/or1k.c: Regenerate. * features/rs6000/powerpc-32.c: Regenerate. * features/rs6000/powerpc-32l.c: Regenerate. * features/rs6000/powerpc-403.c: Regenerate. * features/rs6000/powerpc-403gc.c: Regenerate. * features/rs6000/powerpc-405.c: Regenerate. * features/rs6000/powerpc-505.c: Regenerate. * features/rs6000/powerpc-601.c: Regenerate. * features/rs6000/powerpc-602.c: Regenerate. * features/rs6000/powerpc-603.c: Regenerate. * features/rs6000/powerpc-604.c: Regenerate. * features/rs6000/powerpc-64.c: Regenerate. * features/rs6000/powerpc-64l.c: Regenerate. * features/rs6000/powerpc-7400.c: Regenerate. * features/rs6000/powerpc-750.c: Regenerate. * features/rs6000/powerpc-860.c: Regenerate. * features/rs6000/powerpc-altivec32.c: Regenerate. * features/rs6000/powerpc-altivec32l.c: Regenerate. * features/rs6000/powerpc-altivec64.c: Regenerate. * features/rs6000/powerpc-altivec64l.c: Regenerate. * features/rs6000/powerpc-e500.c: Regenerate. * features/rs6000/powerpc-e500l.c: Regenerate. * features/rs6000/powerpc-isa205-32l.c: Regenerate. * features/rs6000/powerpc-isa205-64l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec32l.c: Regenerate. * features/rs6000/powerpc-isa205-altivec64l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa205-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-htm-vsx64l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx32l.c: Regenerate. * features/rs6000/powerpc-isa207-vsx64l.c: Regenerate. * features/rs6000/powerpc-vsx32.c: Regenerate. * features/rs6000/powerpc-vsx32l.c: Regenerate. * features/rs6000/powerpc-vsx64.c: Regenerate. * features/rs6000/powerpc-vsx64l.c: Regenerate. * features/rs6000/rs6000.c: Regenerate. * features/rx.c: Regenerate. * features/s390-gs-linux64.c: Regenerate. * features/s390-linux32.c: Regenerate. * features/s390-linux32v1.c: Regenerate. * features/s390-linux32v2.c: Regenerate. * features/s390-linux64.c: Regenerate. * features/s390-linux64v1.c: Regenerate. * features/s390-linux64v2.c: Regenerate. * features/s390-te-linux64.c: Regenerate. * features/s390-tevx-linux64.c: Regenerate. * features/s390-vx-linux64.c: Regenerate. * features/s390x-gs-linux64.c: Regenerate. * features/s390x-linux64.c: Regenerate. * features/s390x-linux64v1.c: Regenerate. * features/s390x-linux64v2.c: Regenerate. * features/s390x-te-linux64.c: Regenerate. * features/s390x-tevx-linux64.c: Regenerate. * features/s390x-vx-linux64.c: Regenerate. * mips-tdep.c (_initialize_mips_tdep): Release unique_ptr returned from allocate_target_description. * target-descriptions.c (allocate_target_description): Update return type. (print_c_tdesc::visit_pre): Release unique_ptr returned from allocate_target_description. gdbserver/ChangeLog: * linux-low.cc (linux_process_target::handle_extended_wait): Release the unique_ptr returned from allocate_target_description. * linux-riscv-low.cc (riscv_target::low_arch_setup): Likewise. * linux-x86-low.cc (tdesc_amd64_linux_no_xml): Change type. (tdesc_i386_linux_no_xml): Change type. (x86_linux_read_description): Borrow pointer from unique_ptr object. (x86_target::get_ipa_tdesc_idx): Likewise. (initialize_low_arch): Likewise. * tdesc.cc (allocate_target_description): Update return type. gdbsupport/ChangeLog: * tdesc.h (allocate_target_description): Update return type. |
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Shahab Vahedi
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e4bd363f99 |
arc: Rename "arc_gdbarch_features" struct
"arc_gdbarch_features" is a data structure containing information about the ARC architecture: ISA version, register size, etc. This name is misleading, because although it carries the phrase "gdbarch", it has nothing to do with the type/interface in GDB. Traditionaly, "gdbarch" structures are only used for that purpose. To rectify this, this patch changes the name to "arc_arch_features". gdb/ChangeLog: * arch/arc.h: Rename "arc_gdbarch_features" to "arc_arch_features". * arc-tdep.h: Likewise. * arc-tdep.c: Likewise. |
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Shahab Vahedi
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995d3a197d |
arc: Add ARCv2 XML target along with refactoring
A few changes have been made to make the register support simpler, more flexible and extendible. The trigger for most of these changes are the remarks [1] made earlier for v2 of this patch. The noticeable improvements are: - The arc XML target features are placed under gdb/features/arc - There are two cores (based on ISA) and one auxiliary feature: v1-core: ARC600, ARC601, ARC700 v2-core: ARC EM, ARC HS aux: common in both - The XML target features represent a minimalistic sane set of registers irrespective of application (baremetal or linux). - A concept of "feature" class has been introduced in the code. The "feature" object is constructed from BFD and GDBARCH data. It contains necessary information (ISA and register size) to determine which XML target feature to use. - A new structure (ARC_REGISTER_FEATURE) is added that allows providing index, names, and the necessity of registers. This simplifies the sanity checks and future extendibility. - Documnetation has been updated to reflect ARC features better. - Although the feature names has changed, there still exists backward compatibility with older names through find_obsolete_[core,aux]_names() functions. The last two points were inspired from RiscV port. [1] https://sourceware.org/pipermail/gdb-patches/2020-May/168511.html gdb/ChangeLog: * arch/arc.h (arc_gdbarch_features): New class to stir the selection of target XML. (arc_create_target_description): Use FEATURES to choose XML target. (arc_lookup_target_description): Use arc_create_target_description to create _new_ target descriptions or return the already created ones if the FEATURES is the same. * arch/arc.c: Implementation of prototypes described above. * gdb/arc-tdep.h (arc_regnum enum): Add more registers. (arc_gdbarch_features_init): Initialize the FEATURES struct. * arc-tdep.c (*_feature_name): Make feature names consistent. (arc_register_feature): A new struct to hold information about registers of a particular target/feature. (arc_check_tdesc_feature): Check if XML provides registers in compliance with ARC_REGISTER_FEATURE structs. (arc_update_acc_reg_names): Add aliases for r58 and r59. (determine_*_reg_feature_set): Which feature name to look for. (arc_gdbarch_features_init): Given MACH and ABFD, initialize FEATURES. (mach_type_to_arc_isa): Convert from a set of binutils machine types to expected ISA enums to be used in arc_gdbarch_features structs. * features/Makefile (FEATURE_XMLFILES): Add new files. * gdb/features/arc/v1-aux.c: New file. * gdb/features/arc/v1-aux.xml: Likewise. * gdb/features/arc/v1-core.c: Likewise. * gdb/features/arc/v1-core.xml: Likewise. * gdb/features/arc/v2-aux.c: Likewise. * gdb/features/arc/v2-aux.xml: Likewise. * gdb/features/arc/v2-core.c: Likewise. * gdb/features/arc/v2-core.xml: Likewise. * NEWS (Changes since GDB 9): Announce obsolence of old feature names. gdb/doc/ChangeLog: * gdb.texinfo (Synopsys ARC): Update the documentation for ARC Features. gdb/testsuite/ChangeLog: * gdb.arch/arc-tdesc-cpu.xml: Use new feature names. |
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Tom de Vries
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38f8aa06d9 |
[gdb/build] Fix missing implicit constructor call with gcc 4.8
When building gdb on x86_64-linux with --enable-targets riscv64-suse-linux, I
run into:
...
src/gdb/arch/riscv.c:112:45: required from here
/usr/include/c++/4.8/bits/hashtable_policy.h:195:39: error: no matching \
function for call to 'std::pair<const riscv_gdbarch_features, const \
std::unique_ptr<target_desc, target_desc_deleter> >::pair(const \
riscv_gdbarch_features&, target_desc*&)'
: _M_v(std::forward<_Args>(__args)...) { }
^
...
for this code in riscv_lookup_target_description:
...
/* Add to the cache. */
riscv_tdesc_cache.emplace (features, tdesc);
...
Work around this compiler problem (filed as PR gcc/96537), similar to how that
was done in commit
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Andrew Burgess
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0e26741636 |
gdb/riscv: delete target descriptions when gdb exits
It was pointed out on IRC that the RISC-V target allocates target descriptions and stores them in a global map, and doesn't delete these target descriptions when GDB shuts down. This isn't a particular problem, the total number of target descriptions we can create is very limited so creating these on demand and holding them for the entire run on GDB seems reasonable. However, not deleting these objects on GDB exit means extra warnings are printed from tools like valgrind, and the address sanitiser, making it harder to spot real issues. As it's reasonably easy to have GDB correctly delete these objects on exit, lets just do that. I started by noticing that we already have a target_desc_up type, a wrapper around unique_ptr that calls a function that will correctly delete target descriptions, so I want to use that, but.... ...that type is declared in gdb/target-descriptions.h. If I try to include that file in gdb/arch/riscv.c I run into a problem, that file is compiled into both GDB and GDBServer. OK, I could guard the include with #ifdef, but surely we can do better. So then I decided to move the target_desc_up type into gdbsupport/tdesc.h, this is the interface file for generic code shared between GDB and GDBserver (relating to target descriptions). The actual implementation for the delete function still lives in gdb/target-description.c, but now gdb/arch/riscv.c can see the declaration. Problem solved.... ... but, though RISC-V doesn't use it I've now exposed the target_desc_up type to gdbserver, so in future someone _might_ start using it, which is fine, except right now there's no definition of the delete function - remember the delete I used is only defined in GDB code. No problem, I add an implementation of the delete operator into gdbserver/tdesc.cc, and all is good..... except.... I start getting this error from GCC: tdesc.cc:109:10: error: deleting object of polymorphic class type ‘target_desc’ which has non-virtual destructor might cause undefined behavior [-Werror=delete-non-virtual-dtor] Which is caused because gdbserver's target_desc type inherits from tdesc_element which has a virtual method, and so GCC worries that target_desc might be used as a base class. The solution is to declare gdbserver's target_desc class as final. This is fine so long as we never intent to inherit from target_desc (in gdbserver). But if we did then we'd want to make target_desc's destructor virtual anyway, so the error above would be resolved, and there wouldn't be an issue. gdb/ChangeLog: * arch/riscv.c (riscv_tdesc_cache): Change map type. (riscv_lookup_target_description): Return pointer out of unique_ptr. * target-descriptions.c (allocate_target_description): Add comment. (target_desc_deleter::operator()): Likewise. * target-descriptions.h (struct target_desc_deleter): Moved to gdbsupport/tdesc.h. (target_desc_up): Likewise. gdbserver/ChangeLog: * tdesc.cc (allocate_target_description): Add header comment. (target_desc_deleter::operator()): New function. * tdesc.h (struct target_desc): Declare as final. gdbsupport/ChangeLog: * tdesc.h (struct target_desc_deleter): Moved here from gdb/target-descriptions.h, extend comment. (target_desc_up): Likewise. |
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Anton Kolesov
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817a758576 |
arc: Migrate to new target features
This patch replaces usage of target descriptions in ARC, where the whole
description is fixed in XML, with new target descriptions where XML describes
individual features, and GDB assembles those features into actual target
description.
v2:
Removed arc.c from ALLDEPFILES in gdb/Makefile.in.
Removed vim modeline from arc-tdep.c to have it in a separate patch.
Removed braces from one line "if/else".
Undid the type change for "jb_pc" (kept it as "int").
Joined the unnecessary line breaks into one line.
No more moving around arm targets in gdb/features/Makefile.
Changed pattern checking for ARC features from "arc/{aux,core}" to "arc/".
v3:
Added include gaurds to arc.h.
Added arc_read_description to _create_ target descriptions less.
v4:
Got rid of ARC_SYS_TYPE_NONE.
Renamed ARC_SYS_TYPE_INVALID to ARC_SYS_TYPE_NUM.
Fixed a few indentations/curly braces.
Converted arc_sys_type_to_str from a macro to an inline function.
gdb/ChangeLog:
2020-03-16 Anton Kolesov <anton.kolesov@synopsys.com>
Shahab Vahedi <shahab@synopsys.com>
* Makefile.in: Add arch/arc.o
* configure.tgt: Likewise.
* arc-tdep.c (arc_tdesc_init): Use arc_read_description.
(_initialize_arc_tdep): Don't initialize old target descriptions.
(arc_read_description): New function to cache target descriptions.
* arc-tdep.h (arc_read_description): Add proto type.
* arch/arc.c: New file.
* arch/arc.h: Likewise.
* features/Makefile: Replace old target descriptions with new.
* features/arc-arcompact.c: Remove.
* features/arc-arcompact.xml: Likewise.
* features/arc-v2.c: Likewise
* features/arc-v2.xml: Likewise
* features/arc/aux-arcompact.xml: New file.
* features/arc/aux-v2.xml: Likewise.
* features/arc/core-arcompact.xml: Likewise.
* features/arc/core-v2.xml: Likewise.
* features/arc/aux-arcompact.c: Generate.
* features/arc/aux-v2.c: Likewise.
* features/arc/core-arcompact.c: Likewise.
* features/arc/core-v2.c: Likewise.
* target-descriptions (maint_print_c_tdesc_cmd): Support ARC features.
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Andrew Burgess
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d1c9b20ff9 |
gdb/riscv: Update API for looking up target descriptions
In preparation for adding the RISC-V gdbserver, this commit restructures the API for looking up target descriptions. The current API is riscv_create_target_description, which creates a target description from a riscv_gdbarch_features, but also caches the created target descriptions so that for a given features object we always get back the same target description object. This is important for GDB due to the way gdbarch objects are reused. As the same target description is always returned to GDB, and can be returned multiple times, it is returned as a const, however, the current cache actually stores a non-const target description. This is improved in this patch so that the cache holds a const target description. For gdbsever, this caching of the target descriptions is not needed, the gdbserver looks up one target description to describe the target it is actually running on and that is it. Further the gdbserver actually needs to modify the target description that is looked up, so for the gdbsever, returning a const target description is not acceptable. This commit aims to address this by creating two parallel target description APIs, on is the old riscv_create_target_description, however, this no longer performs any caching, and just creates a new target description, and returns it as non-const. The second API is riscv_lookup_target_description, this one performs the caching, and calls riscv_create_target_description to create a target description when needed. In order to make sure the correct API is used in the correct place I have guarded the code using the GDBSERVER define. For GDB the riscv_create_target_description is static, and not generally usable throughout GDB, only the lookup API is global. In gdbserver, the lookup functions, and the cache are not defined or created at all, only the riscv_create_target_description API is available. There should be no user visible changes after this commit. gdb/ChangeLog: * arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define if GDBSERVER is not defined. (riscv_tdesc_cache): Likewise, also store const target_desc. (STATIC_IN_GDB): Define. (riscv_create_target_description): Update declaration with STATIC_IN_GDB. (riscv_lookup_target_description): New function, only define if GDBSERVER is not defined. * arch/riscv.h (riscv_create_target_description): Declare only when GDBSERVER is defined. (riscv_lookup_target_description): New declaration when GDBSERVER is not defined. * nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this, and return riscv_gdbarch_features instead of target_desc. * nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'. (riscv_linux_read_description): Rename to... (riscv_linux_read_features): ...this. * riscv-linux-nat.c (riscv_linux_nat_target::read_description): Update to use riscv_gdbarch_features and riscv_lookup_target_description. * riscv-tdep.c (riscv_find_default_target_description): Use riscv_lookup_target_description instead of riscv_create_target_description. |