bfd * coff-i386.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_i386_relocation_section): Add support for R_SECTION.
(coff_i386_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* coff-x86_64.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_amd64_relocation_section): Add support for R_SECTION.
(coff_amd64_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* reloc.c: Add BFD_RELOC_16_SECIDX.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas * config/tc-i386.c (pe_directive_secidx): New function.
(md_pseudo_table): Add support for secidx.
(x86_cons_fix_new): Likewise.
(tc_gen_reloc): Likewise.
* expr.c (op_rank): Add O_secidx.
* expr.h (operatorT): Likewise.
* symbols.c (resolve_symbol_value): Add support for O_secidx.
* testsuite/gas/i386/secidx.s: New test source file.
* testsuite/gas/i386/secidx.d: New test driver file.
* testsuite/gas/i386/i386.exp: Run new test.
include * coff/i386.h: Define R_SECTION.
* coff/x86_64.h: Likewise.
ld * testsuite/ld-pe/secidx1.s: New test source file.
* testsuite/ld-pe/secidx2.s: New test source file.
* testsuite/ld-pe/secidx.d: New test driver file.
* testsuite/ld-pe/secidx_64.d: New test driver file.
* testsuite/ld-pe/pe.exp: Add new tests.
This commit adds the _option_ of having disassembler output syntax
highlighted in objdump. This option is _off_ by default. The new
command line options are:
--disassembler-color=off # The default.
--disassembler-color=color
--disassembler-color=extended-color
I have implemented two colour modes, using the same option names as we
use of --visualize-jumps, a basic 8-color mode ("color"), and an
extended 8bit color mode ("extended-color").
The syntax highlighting requires that each targets disassembler be
updated; each time the disassembler produces some output we now pass
through an additional parameter indicating what style should be
applied to the text.
As updating all target disassemblers is a large task, the old API is
maintained. And so, a user of the disassembler (i.e. objdump, gdb)
must provide two functions, the current non-styled print function, and
a new, styled print function.
I don't currently have a plan for converting every single target
disassembler, my hope is that interested folk will update the
disassemblers they are interested in. But it is possible some might
never get updated.
In this initial series I intend to convert the RISC-V disassembler
completely, and also do a partial conversion of the x86 disassembler.
Hopefully having the x86 disassembler at least partial converted will
allow more people to try this out easily and provide feedback.
In this commit I have focused on objdump. The changes to GDB at this
point are the bare minimum required to get things compiling, GDB makes
no use of the styling information to provide any colors, that will
come later, if this commit is accepted.
This first commit in the series doesn't convert any target
disassemblers at all (the next two commits will update some targets),
so after this commit, the only color you will see in the disassembler
output, is that produced from objdump itself, e.g. from
objdump_print_addr_with_sym, where we print an address and a symbol
name, these are now printed with styling information, and so will have
colors applied (if the option is on).
Finally, my ability to pick "good" colors is ... well, terrible. I'm
in no way committed to the colors I've picked here, so I encourage
people to suggest new colors, or wait for this commit to land, and
then patch the choice of colors.
I do have an idea about using possibly an environment variable to
allow the objdump colors to be customised, but I haven't done anything
like that in this commit, the color choices are just fixed in the code
for now.
binutils/ChangeLog:
* NEWS: Mention new feature.
* doc/binutils.texi (objdump): Describe --disassembler-color
option.
* objdump.c (disassembler_color): New global.
(disassembler_extended_color): Likewise.
(disassembler_in_comment): Likewise.
(usage): Mention --disassembler-color option.
(long_options): Add --disassembler-color option.
(objdump_print_value): Use fprintf_styled_func instead of
fprintf_func.
(objdump_print_symname): Likewise.
(objdump_print_addr_with_sym): Likewise.
(objdump_color_for_disassembler_style): New function.
(objdump_styled_sprintf): New function.
(fprintf_styled): New function.
(disassemble_jumps): Use disassemble_set_printf, and reset
disassembler_in_comment.
(null_styled_print): New function.
(disassemble_bytes): Use disassemble_set_printf, and reset
disassembler_in_comment.
(disassemble_data): Update init_disassemble_info call.
(main): Handle --disassembler-color option.
include/ChangeLog:
* dis-asm.h (enum disassembler_style): New enum.
(struct disassemble_info): Add fprintf_styled_func field, and
created_styled_output field.
(disassemble_set_printf): Declare.
(init_disassemble_info): Add additional parameter.
(INIT_DISASSEMBLE_INFO): Add additional parameter.
opcodes/ChangeLog:
* dis-init.c (init_disassemble_info): Take extra parameter,
initialize the new fprintf_styled_func and created_styled_output
fields.
* disassembler.c (disassemble_set_printf): New function definition.
It is better to rename floatformats_ia64_quad to floatformats_ieee_quad
to reflect the reality, and then we can clean up the related code.
As Tom Tromey said [1]:
These files are maintained in gcc and then imported into the
binutils-gdb repository, so any changes to them will have to
be proposed there first.
the related changes have been merged into gcc master now [2], it is time
to do it for gdb.
[1] https://sourceware.org/pipermail/gdb-patches/2022-March/186569.html
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b2dff6b2d9d6
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
This core dump note contains the value of the base address of the %fs
and %gs segments for both i386 and amd64 core dumps. It is primarily
useful in resolving the address of TLS variables in core dumps.
binutils/ChangeLog:
* readelf.c (get_freebsd_elfcore_note_type): Handle
NT_FREEBSD_X86_SEGBASES.
include/ChangeLog:
* elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.
The CTF variable section is an optional (usually-not-present) section in
the CTF dict which contains name -> type mappings corresponding to data
symbols that are present in the linker input but not in the output
symbol table: the idea is that programs that use their own symbol-
resolution mechanisms can use this section to look up the types of
symbols they have found using their own mechanism.
Because these removed symbols (mostly static variables, functions, etc)
all have names that are unlikely to appear in the ELF symtab and because
very few programs have their own symbol-resolution mechanisms, a special
linker flag (--ctf-variables) is needed to emit this section.
Historically, we emitted only removed data symbols into the variable
section. This seemed to make sense at the time, but in hindsight it
really doesn't: functions are symbols too, and a C program can look them
up just like any other type. So extend the variable section so that it
contains all static function symbols too (if it is emitted at all), with
types of kind CTF_K_FUNCTION.
This is a little fiddly. We relied on compiler assistance for data
symbols: the compiler simply emits all data symbols twice, once into the
symtypetab as an indexed symbol and once into the variable section.
Rather than wait for a suitably adjusted compiler that does the same for
function symbols, we can pluck unreported function symbols out of the
symtab and add them to the variable section ourselves. While we're at
it, we do the same with data symbols: this is redundant right now
because the compiler does it, but it costs very little time and lets the
compiler drop this kludge and save a little space in .o files.
include/
* ctf.h: Mention the new things we can see in the variable
section.
ld/
* testsuite/ld-ctf/data-func-conflicted-vars.d: New test.
libctf/
* ctf-link.c (ctf_link_deduplicating_variables): Duplicate
symbols into the variable section too.
* ctf-serialize.c (symtypetab_delete_nonstatic_vars): Rename
to...
(symtypetab_delete_nonstatics): ... this. Check the funchash
when pruning redundant variables.
(ctf_symtypetab_sect_sizes): Adjust accordingly.
* NEWS: Describe this change.
Handle the NT_AMDGPU_METADATA note, which is described here:
https://llvm.org/docs/AMDGPUUsage.html#code-object-v3-note-records
As of this patch, just print out the name, not the contents, which is in
the msgpack format.
binutils/ChangeLog:
* readelf.c (get_amdgpu_elf_note_type): New.
(process_note): Handle "AMDGPU" notes.
include/ChangeLog:
* elf/amdgcn.h (NT_AMDGPU_METADATA): New.
Change-Id: Id2dba2e2aeaa55ef7464fb35aee9c7d5f96ddb23
Decode and print the AMDGPU-specific fields of e_flags, as documented
here:
https://llvm.org/docs/AMDGPUUsage.html#header
That is:
- The specific GPU model
- Whether the xnack and sramecc features are enabled
The result looks like:
- Flags: 0x52f
+ Flags: 0x52f, gfx906, xnack any, sramecc any
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)
So for those other OS ABIs, we read them the same as HSA v3.
binutils/ChangeLog:
* readelf.c: Include elf/amdgcn.h.
(decode_AMDGPU_machine_flags): New.
(get_machine_flags): Handle flags for EM_AMDGPU machine type.
include/ChangeLog:
* elf/amdgcn.h: Add EF_AMDGPU_MACH_AMDGCN_* and
EF_AMDGPU_FEATURE_* defines.
Change-Id: Ib5b94df7cae0719a22cf4e4fd0629330e9485c12
When the machine is EM_AMDGPU, handle the various OS ABIs described
here:
https://llvm.org/docs/AMDGPUUsage.html#header
For a binary with the HSA OS ABI, the change looks like:
- OS/ABI: <unknown: 40>
+ OS/ABI: AMD HSA
binutils/ChangeLog:
* readelf.c (get_osabi_name): Handle EM_AMDGPU OS ABIs.
include/ChangeLog:
* elf/common.h (ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D):
New.
Change-Id: I383590c390f7dc2fe0f902f50038735626d71863
Add support for the AMDGCN architecture to BFD.
This is the bare minimum to get
$ ./configure --target=amdgcn-hsa-amdhsa --disable-gas
$ make all-binutils
working later in this series.
The specific AMDGCN models added here are a bit arbitrary, based on
what we intend to initially support in GDB. This list will need to be
updated in the future anyway. The complete up-to-date list of existing
AMDGPU models can be found here:
https://llvm.org/docs/AMDGPUUsage.html#processors
The ELF format for this architecture is documented here:
https://llvm.org/docs/AMDGPUUsage.html#elf-code-object
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)
So at least, we know that all AMDGPU objects (of which AMDGCN objects
are a subset of) at the time of writing encode the specific GPU model in
the EF_AMDGPU_MACH field of e_flags.
bfd/ChangeLog:
* Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES):
Add cpu-amdgcn.c.
(BFD64_BACKENDS): Add elf64-amdgcn.lo.
(BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c.
* Makefile.in: Re-generate.
* cpu-amdgcn.c: New.
* elf64-amdgcn.c: New.
* archures.c (bfd_architecture): Add bfd_arch_amdgcn and related
mach defines.
(bfd_amdgcn_arch): New.
(bfd_archures_list): Add bfd_amdgcn_arch.
* bfd-in2.h: Re-generate.
* config.bfd: Handle amdgcn* target.
* configure.ac: Handle amdgcn_elf64_le_vec.
* configure: Re-generate.
* elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA.
* targets.c (amdgcn_elf64_le_vec): New.
(_bfd_target_vector): Add amdgcn_elf64_le_vec.
include/ChangeLog:
* elf/amdgpu.h: New.
* elf/common.h (ELFOSABI_AMDGPU_HSA): Add.
Change-Id: I969f7b14960797e88891c308749a6e341eece5b2
Let's hope this stays dead, but it's here as a patch separate from
those that removed use of powerpc_macros just in case it needs to be
resurrected.
include/
* opcode/ppc.h (struct powerpc_macro): Delete declaration.
(powerpc_macros, powerpc_num_macros): Likewise..
opcodes/
* ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete.
gas/
* config/tc-ppc.c (ppc_macro): Delete function.
(ppc_macro_hash): Delete.
(ppc_setup_opcodes, md_assemble): Delete macro support.
The extended instructions implemented in powerpc_macros aren't used by
the disassembler. That means instructions like "sldi r3,r3,2" appear
in disassembly as "rldicr r3,r3,2,61", which is annoying since many
other extended instructions are shown.
Note that some of the instructions moved out of the macro table to the
opcode table won't appear in disassembly, because they are aliases
rather than a subset of the underlying raw instruction. If enabled,
rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many
occurrences in the case of clrlsldi if n <= b was added to the extract
functions.)
The patch also fixes a small bug in opcode sanity checking.
include/
* opcode/ppc.h (PPC_OPSHIFT_SH6): Define.
opcodes/
* ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn),
(insert_crdn, extract_crdn, insert_rrdn, extract_rrdn),
(insert_sldn, extract_sldn, insert_srdn, extract_srdn),
(insert_erdb, extract_erdb, insert_csldn, extract_csldb),
(insert_irdb, extract_irdn): New functions.
(ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb):
Define and add associated powerpc_operands entries.
(powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi",
"sldi", "extldi", "clrlsldi", "insrdi" and corresponding record
(ie. dot suffix) forms.
(powerpc_macros): Delete same from here.
gas/
* config/tc-ppc.c (insn_validate): Don't modify value passed
to operand->insert for PPC_OPERAND_PLUS1 when calculating mask.
Handle PPC_OPSHIFT_SH6.
* testsuite/gas/ppc/prefix-reloc.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
ld/
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/notoc.d: Update.
* testsuite/ld-powerpc/notoc3.d: Update.
* testsuite/ld-powerpc/tlsdesc2.d: Update.
* testsuite/ld-powerpc/tlsget.d: Update.
* testsuite/ld-powerpc/tlsget2.d: Update.
* testsuite/ld-powerpc/tlsopt5.d: Update.
* testsuite/ld-powerpc/tlsopt6.d: Update.
* Removed N extension CSRs,
ustatus, uie, utvec, uscratch, uepc, ucause, utval and uip.
* Removed two supervisor CSRs,
sedeleg and sideleg.
* Changed debug CSR address of scontext from 0x7aa to 0x5a8. We cannot support
different versions of debug specs for now, so only supporting the latest one is
the only way to move forward.
* Added debug CSRs,
mscontext (0x7aa), mcontrol6 (0x7a1, tdata1) and tmexttrigger ((0x7a1, tdata1).
* Regarded hcontext as a debug CSR.
include/
* opcode/riscv-opc.h: Updated CSRs to privileged spec v1.12 and
debug spec v1.0.
gas/
* testsuite/gas/riscv/csr.s: Updated CSRs to privileged spec v1.12
and debug spec v1.0.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
Gfortran supports namelists (a Fortran feature); it emits
DW_TAG_namelist and DW_TAG_namelist_item dies. But gdb does not
process these dies and does not support 'print' or 'ptype' commands on
namelist variables.
An attempt to print namelist variables results in gdb bailing out with
the error message as shown below.
(gdb) print nml
No symbol "nml" in current context.
This commit is to make the print and ptype commands work for namelist
variables and its items. Sample output of these commands is shared
below, with fixed gdb.
(gdb) ptype nml
type = Type nml
integer(kind=4) :: a
integer(kind=4) :: b
End Type nml
(gdb) print nml
$1 = ( a = 10, b = 20 )
include/
* bfdlink.h (struct bfd_link_info): Add commonpagesize_is_set.
ld/
PR 28751
* emultempl/elf.em (handle_option): Set commonpagesize_is_set.
* ldelf.c (ldelf_after_parse): Don't error when only one of
-z max-page-size or -z common-page-size is given, correct the
other value to make it sane.
* testsuite/ld-elf/elf.exp (mbind2a, mbind2b): Do not pass
-z max-page-size.
Add a -z pack-relative-relocs option to enable DT_RELR and create a
relr.dyn section for DT_RELR. DT_RELR is implemented with the linker
relaxation infrastructure, but it doesn't require the --relax option
enabled. -z pack-relative-relocs implies -z combreloc. -z nocombreloc
implies -z nopack-relative-relocs.
-z pack-relative-relocs is chosen over the similar option in lld,
--pack-dyn-relocs=relr, to implement a glibc binary lockout mechanism
with a special glibc version symbol, to avoid random crashes of DT_RELR
binaries with the existing glibc binaries.
bfd/
* elf-bfd.h (elf_link_hash_table): Add srelrdyn.
* elflink.c (_bfd_elf_link_create_dynamic_sections): Create a
.relr.dyn section for DT_RELR.
include/
* bfdlink.h (bfd_link_info): Add enable_dt_relr.
ld/
* News: Mention -z pack-relative-relocs and
-z nopack-relative-relocs.
* ld.texi: Document -z pack-relative-relocs and
-z nopack-relative-relocs.
* ldelf.c (ldelf_after_parse): Disable DT_RELR if not building
PIE nor shared library. Add 3 spare dynamic tags for DT_RELR,
DT_RELRSZ and DT_RELRENT.
* ldlang.c (lang_relax_sections): Also enable relaxation if
DT_RELR is enabled.
* emulparams/elf32_x86_64.sh: Source dt-relr.sh.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Likewise.
* emulparams/dt-relr.sh: New file.
* scripttempl/elf.sc: Support .relr.dyn.
XCOFF assembly defines the visibility using an additional argument
on several pseudo-ops: .globl, .weak, .extern and .comm.
This implies that .globl and .weak syntax is different than the
usual GNU syntax. But we want to provide compatibility with AIX
assembler, especially because GCC is generating the visibility
using this XCOFF syntax.
PR 22085
bfd/ChangeLog:
* coffcode.h (coff_write_object_contents): Change XCOFF header
vstamp field to 2.
* coffgen.c (coff_print_symbol): Increase the size for n_type.
gas/ChangeLog:
* config/tc-ppc.c (ppc_xcoff_get_visibility): New function.
(ppc_globl): New function.
(ppc_weak): New function.
(ppc_comm): Add visibility field support.
(ppc_extern): Likewise.
* testsuite/gas/all/cofftag.d: Adjust to new n_type size
providing by objdump.
* testsuite/gas/ppc/test1xcoff32.d: Likewise.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-visibility-1-32.d: New test.
* testsuite/gas/ppc/xcoff-visibility-1-64.d: New test.
* testsuite/gas/ppc/xcoff-visibility-1.s: New test.
include/ChangeLog:
* coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN,
SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines.
* coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility
field.
ld/ChangeLog:
* testsuite/ld-pe/pr19803.d: Adjust to new n_type size
providing by objdump.
Currently, on 32-bit and 64-bit ARM, it seems that ld generates p_align
values of 0x10000 even if no section alignment is greater than 0x1000.
The issue is more general and probably affects other targets with multiple
page sizes.
While file layout absolutely must take 64K page size into account, that
does not have to be reflected in the p_align value. If running on a 64K
kernel, the file will be loaded at a 64K page boundary by necessity. On
a 4K kernel, 64K alignment is not needed.
The glibc loader has been fixed to honor p_align:
https://sourceware.org/bugzilla/show_bug.cgi?id=28676
similar to kernel:
commit ce81bb256a224259ab686742a6284930cbe4f1fa
Author: Chris Kennelly <ckennelly@google.com>
Date: Thu Oct 15 20:12:32 2020 -0700
fs/binfmt_elf: use PT_LOAD p_align values for suitable start address
This means that on 4K kernels, we will start to do extra work for 64K
p_align, but this pointless for pretty much all binaries (whose section
alignment rarely exceeds 16).
The minimum page size is used, instead of the maximum section alignment
due to this glibc bug:
https://sourceware.org/bugzilla/show_bug.cgi?id=28688
It has been fixed in glibc 2.35. But linker output must work on existing
glibc binaries.
1. Set p_align to the minimum page size while laying out segments aligning
to the maximum page size or section alignment. The run-time loader can
align segments to the minimum page size or above, depending on system page
size.
2. If -z max-page-size=NNN is used, p_align will be set to the maximum
page size or the largest section alignment.
3. If a section requires alignment higher than the minimum page size,
don't set p_align to the minimum page size.
4. If a section requires alignment higher than the maximum page size,
set p_align to the section alignment.
5. For objcopy, when the minimum page size != the maximum page size,
p_align may be set to the minimum page size while segments are aligned
to the maximum page size. In this case, the input p_align will be
ignored and the maximum page size will be used to align the ouput
segments.
6. Update linker to disallow the common page size > the maximum page size.
7. Update linker to avoid the common page size > the maximum page size.
8. Adjust pru_irq_map-1.d to expect p_align == sh_addralign:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4
...
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1
LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x4
vs.
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 20000000 00007c 000004 00 AX 0 0 4
...
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000074 0x00000000 0x00000000 0x00008 0x00008 RW 0x1
LOAD 0x00007c 0x20000000 0x20000000 0x00004 0x00004 R E 0x1
To enable this linker optimization, the backend should define ELF_P_ALIGN
to ELF_MINPAGESIZE.
bfd/
PR ld/28689
PR ld/28695
* elf-bfd.h (elf_backend_data): Add p_align.
* elf.c (assign_file_positions_for_load_sections): Set p_align
to the default p_align value while laying out segments aligning
to maximum page size or section alignment.
(elf_is_p_align_valid): New function.
(copy_elf_program_header): Call elf_is_p_align_valid to determine
if p_align is valid.
* elfxx-target.h (ELF_P_ALIGN): New. Default to 0.
(elfNN_bed): Add ELF_P_ALIGN.
* elfxx-x86.h (ELF_P_ALIGN): New. Set to ELF_MINPAGESIZE.
include/
PR ld/28689
PR ld/28695
* bfdlink.h (bfd_link_info): Add maxpagesize_is_set.
ld/
PR ld/28689
PR ld/28695
* emultempl/elf.em (gld${EMULATION_NAME}_handle_option): Set
link_info.maxpagesize_is_set for -z max-page-size=NNN.
* ldelf.c (ldelf_after_parse): Disallow link_info.commonpagesize
> link_info.maxpagesize.
* testsuite/ld-elf/elf.exp: Pass -z max-page-size=0x4000 to
linker to build mbind2a and mbind2b.
* testsuite/ld-elf/header.d: Add -z common-page-size=0x100.
* testsuite/ld-elf/linux-x86.exp: Add PR ld/28689 tests.
* testsuite/ld-elf/p_align-1.c: New file.
* testsuite/ld-elf/page-size-1.d: New test.
* testsuite/ld-elf/pr26936.d: Add -z common-page-size=0x1000.
* testsuite/ld-elf/seg.d: Likewise.
* testsuite/ld-scripts/rgn-at5.d: Likewise.
* testsuite/ld-pru/pru_irq_map-1.d: Append 1 to name. Adjust
expected PT_LOAD segment alignment.
* testsuite/ld-pru/pru_irq_map-2.d: Append 2 to name.
* testsuite/ld-scripts/pr23571.d: Add -z max-page-size=0x1000.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.
For the avoidance of doubt, all changes in this commits were
performed by the script.
This makes way for a clean 1.12 based Hypervisor Ext support.
There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210
is based on priv spec 1.9.1, but it seems unlikely that they implemented
H-ext).
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
gas/
* testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs
defined in the privileged spec 1.9.1.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg.s: Likewise.
include/
* opcode/riscv-opc.h: Drop the hypervisor csrs defined in the
privileged spec 1.9.1.
This patch adds AArch32 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.
The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A
are technically redundant but it seemed less surprising to include
them anyway.
include/
* opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros.
(ARM_ARCH_V9_3A): Likewise.
gas/
* doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a.
* config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros.
(armv93a_ext_table): Likewise.
(arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a.
(cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A.
* NEWS: Mention the above.
* testsuite/gas/arm/attr-march-armv9_1-a.d: New test.
* testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise.
* testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.
This patch adds AArch32 support for -march=armv8.[78]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.
The cpu_arch_ver entries are technically redundant but
it seemed less surprising to include them anyway.
include/
* opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros.
gas/
* doc/c-arm.texi: Add armv8.7-a and armv8.8-a.
* config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros.
(arm_archs): Add armv8.7-a and armv8.8-a.
(cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A.
* NEWS: Mention the above.
* testsuite/gas/arm/attr-march-armv8_7-a.d: New test.
* testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
This patch adds AArch64 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags, so we don't need to
eat into the vanishing number of spare AARCH64_FEATURE_* bits.
Hoewver, it was more convenient to separate out the |s of
feature flags so that Armv9.1-A could reuse the set for
Armv8.6-A, and so on.
include/
* opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro,
split out from...
(AARCH64_ARCH_V8): ...here.
(AARCH64_ARCH_V8_1_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_1): ...here.
(AARCH64_ARCH_V8_2_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_2): ...here.
(AARCH64_ARCH_V8_3_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_3): ...here.
(AARCH64_ARCH_V8_4_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_4): ...here.
(AARCH64_ARCH_V8_5_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_5): ...here.
(AARCH64_ARCH_V8_6_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_6): ...here.
(AARCH64_ARCH_V8_7_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_7): ...here.
(AARCH64_ARCH_V8_8_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_8): ...here.
(AARCH64_ARCH_V9_FEATURES): New macro, split out from...
(AARCH64_ARCH_V9): ...here.
(AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros.
(AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros.
(AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros.
gas/
* doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a.
* config/tc-aarch64.c (aarch64_archs): Likewise.
* NEWS: Mention the above.
* testsuite/gas/aarch64/armv9_invalid.d,
testsuite/gas/aarch64/armv9_invalid.s,
testsuite/gas/aarch64/armv9_invalid.l: New test.
* testsuite/gas/aarch64/armv9_1.d,
testsuite/gas/aarch64/armv9_1.s: Likewise.
* testsuite/gas/aarch64/armv9_1_invalid.d,
testsuite/gas/aarch64/armv9_1_invalid.s,
testsuite/gas/aarch64/armv9_1_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_2.d,
testsuite/gas/aarch64/armv9_2.s: Likewise.
* testsuite/gas/aarch64/armv9_2_invalid.d,
testsuite/gas/aarch64/armv9_2_invalid.s,
testsuite/gas/aarch64/armv9_2_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_3.d,
testsuite/gas/aarch64/armv9_3.s: Likewise.
According to the privileged spec, there are five new instructions for
svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to
enable the hypervisor extension. But there is no implementation of
hypervisor extension in mainline for now, so let's consider the related
issues later.
31..25 24..20 19..15 14..12 11...7 6..2 1..0
sinval.vma 0001011 rs2 rs1 000 00000 11100 11
sfence.w.inval 0001100 00000 00000 000 00000 11100 11
sfence.inval.ir 0001100 00001 00000 000 00000 11100 11
hinval.vvma 0010011 rs2 rs1 000 00000 11100 11
hinval.gvma 0110011 rs2 rs1 000 00000 11100 11
This patch is cherry-picked from the riscv integration branch since the
svinval extension is frozen for now. Besides, we fix the funct7 encodings
of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011
and 0x0110011.
bfd/
* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
(riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL.
gas/
* testsuite/gas/riscv/svinval.d: New testcase.
* testsuite/gas/riscv/svinval.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for svinval.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
* riscv-opc.c (riscv_opcodes): Added svinval instructions.
FreeBSD's kernel has recently added two new ELF auxiliary vector
entries. AT_FXRNG points to a root seed version for the kernel's
PRNG. Userland can use this to reseed a userland PRNG after the
kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a
kernel-provided vDSO.
This change displays the proper name and description of these entries
in 'info auxv'.
include/ChangeLog:
* elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.
We're including system headers after local headers in a bunch of
places, but this leads to conflicts when our local headers happen
to define symbols that show up in the system headers.
Use the more standard order of:
* config.h (via defs.h)
* system headers
* local library headers (e.g. bfd & libiberty)
* sim specific headers
The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.
I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]
include/
* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
(AARCH64_OPND_MOPS_WB_Rn): Likewise.
opcodes/
* aarch64-asm.h (ins_x0_to_x30): New inserter.
* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
* aarch64-dis.h (ext_x0_to_x30): New extractor.
* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
* aarch64-tbl.h (aarch64_feature_mops): New feature set.
(aarch64_feature_mops_memtag): Likewise.
(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
(MOPS_SET_INSN): New macros.
(aarch64_opcode_table): Add MOPS instructions.
(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
* aarch64-opc.c (aarch64_print_operand): Handle
AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
AARCH64_OPND_MOPS_WB_Rn.
(verify_three_different_regs): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* doc/c-aarch64.texi: Document +mops.
* config/tc-aarch64.c (parse_x0_to_x30): New function.
(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
(aarch64_features): Add "mops".
* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
* testsuite/gas/aarch64/mops_invalid.s,
* testsuite/gas/aarch64/mops_invalid.d,
* testsuite/gas/aarch64/mops_invalid.l: Likewise.
This patch adds skeleton support for -march=armv8.8-a, testing only
that it correctly inherits from armv8.7-a.
include/
* opcode/aarch64.h (AARCH64_FEATURE_V8_8): New macro.
(AARCH64_ARCH_V8_8): Likewise.
gas/
* doc/c-aarch64.texi: Document armv8.8-a.
* config/tc-aarch64.c (aarch64_archs): Add armv8-8-a
* testsuite/gas/aarch64/v8-8-a.s,
* testsuite/gas/aarch64/v8-8-a.d: New test.
libopcodes has some code to check constraints across sequences
of consecutive instructions. It was added to support MOVPRFX
sequences but is going to be useful for the Armv8.8-A MOPS
feature as well.
Currently the structure has one field to record the instruction
that started a sequence and another to record the remaining
instructions in the sequence. It's more convenient for the
MOPS code if we put the instructions into a single array instead.
No functional change intended.
include/
* opcode/aarch64.h (aarch64_instr_sequence): Replace num_insns
and current_insns with num_added_insns and num_allocated_insns.
opcodes/
* aarch64-opc.c (add_insn_to_sequence): New function.
(init_insn_sequence): Update for new aarch64_instr_sequence layout.
Add the first instruction to the inst array.
(verify_constraints): Update for new aarch64_instr_sequence layout.
Don't add the last instruction to the array.
When introducing this code, I forgot that we had some macros for this.
Replace some "manual" pragma diagnostic with some DIAGNOSTIC_* macros,
provided by include/diagnostics.h.
In diagnostics.h:
- Add DIAGNOSTIC_ERROR, to enable a diagnostic at error level.
- Add DIAGNOSTIC_ERROR_SWITCH, to enable -Wswitch at error level, for
both gcc and clang.
Additionally, using DIAGNOSTIC_PUSH, DIAGNOSTIC_ERROR_SWITCH and
DIAGNOSTIC_POP seems to misbehave with g++ 4.8, where we see these
errors:
CXX ada-tasks.o
/home/smarchi/src/binutils-gdb/gdb/ada-tasks.c: In function void read_known_tasks():
/home/smarchi/src/binutils-gdb/gdb/ada-tasks.c:998:10: error: enumeration value ADA_TASKS_UNKNOWN not handled in switch [-Werror=switch]
switch (data->known_tasks_kind)
^
Because of the POP, the diagnostic should go back to being disabled,
since it was disabled in the beginning, but that's not what we see
here. Versions of GCC >= 5 compile correctly.
Work around this by making DIAGNOSTIC_ERROR_SWITCH a no-op for GCC < 5.
Note that this code (already as it exists in master today) enables
-Wswitch at the error level even if --disable-werror is passed. It
shouldn't be a problem, as it's not like a new enumerator will appear
out of nowhere and cause a build error if building with future
compilers. Still, for correctness, we would ideally want to ask the
compiler to enable -Wswitch at its default level (as if the user had
passed -Wswitch on the command-line). There doesn't seem to be a way to
do this.
Change-Id: Id33ebec3de39bd449409ea0bab59831289ffe82d
As defined on: https://systemd.io/COREDUMP_PACKAGE_METADATA/
this note will be used starting from Fedora 36. Allow
readelf --notes to pretty print it:
Displaying notes found in: .note.package
Owner Data size Description
FDO 0x00000039 FDO_PACKAGING_METADATA
Packaging Metadata: {"type":"deb","name":"fsverity-utils","version":"1.3-1"}
Signed-off-by: Luca Boccassi <luca.boccassi@microsoft.com>
According the rvv spec,
https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc
The bits of vtype immediate from 8 to (xlen - 1) should be reserved.
Therefore, we should also dump the vtype immediate as numbers, when
they are set over 8-bits. I think this is a bug that we used to support
vediv extension and use the bit 8 and 9 of vtype, but forgot to update
the behavior when removing the vediv.
Consider the testcases,
vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used.
vsetvli a0, a1, 0x400 # the reserved bit 10 is used.
vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used.
vsetvli a0, a1, 0x100 # the reserved bit 8 is used.
vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used.
vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used.
The original objdump shows the following result,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu
c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu
10: f005f557 vsetivli a0,11,e8,m1,tu,mu
14: d005f557 vsetivli a0,11,e8,m1,tu,mu
But in fact the correct result should be,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,768
c: 1005f557 vsetvli a0,a1,256
10: f005f557 vsetivli a0,11,768
14: d005f557 vsetivli a0,11,256
gas/
* testsuite/gas/riscv/vector-insns.d: Added testcases to
test the reserved bit 8 to (xlen-1) of vtype.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES,
since they are different for operand Vc and Vb.
opcodes/
* riscv-dis.c (print_insn_args): Updated imm_vtype_res to
extract the reserved immediate of vtype correctly.
In preparation for the next commit, which will add GDB support for
RISC-V disassembler options, this commit restructures how the
disassembler options are managed within libopcodes.
The implementation provided here is based on this mailing list patch
which was never committed:
https://sourceware.org/pipermail/binutils/2021-January/114944.html
which in turn took inspiration from the MIPS implementation of the
same feature.
The biggest changes from the original mailing list post are:
1. The GDB changes have been split into a separate patch, and
2. The `riscv_option_args_privspec` variable, which held the valid
priv-spec values is now gone, instead we use the `riscv_priv_specs`
array from bfd/cpu-riscv.c instead.
Co-authored-by: Simon Cook <simon.cook@embecosm.com>
include/ChangeLog:
* dis-asm.h (disassembler_options_riscv): Declare.
opcodes/ChangeLog:
* riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
(riscv_options): New static global.
(disassembler_options_riscv): New function.
(print_riscv_disassembler_options): Rewrite to use
disassembler_options_riscv.
