I ran
for i in $(find . -name configure.ac); do pushd $(dirname $i); autoreconf -vf; popd; done
to re-generate all automake/autoconf files throughout the repo (with
upstream autoconf 2.69 and automake 1.15.1). These were the changes
that came out. I am pushing this as obvious.
libdecnumber/ChangeLog:
* aclocal.m4, configure: Re-generate.
sim/bfin/ChangeLog:
* aclocal.m4, configure: Re-generate.
sim/erc32/ChangeLog:
* configure: Re-generate.
sim/mips/ChangeLog:
* configure: Re-generate.
sim/testsuite/ChangeLog:
* configure: Re-generate.
Change-Id: I97335c09972d25cc5f6fd8da4db4ffe4a0348787
GCC 10 enables -fno-common by default. This resulted in multiple
definition linker errors since a global variable was declared and
defined in a header file:
ld: libsim.a(idecode.o):sim/v850/idecode.h:71: multiple definition of
`idecode_issue'; libsim.a(irun.o):sim/v850/idecode.h:71: first defined
here
ld: libsim.a(engine.o):sim/v850/idecode.h:71: multiple definition of
`idecode_issue'; libsim.a(irun.o):sim/v850/idecode.h:71: first defined
here
ld: libsim.a(support.o):sim/v850/idecode.h:71: multiple definition of
`idecode_issue'; libsim.a(irun.o):sim/v850/idecode.h:71: first defined
here
ld: libsim.a(semantics.o):sim/v850/idecode.h:71: multiple definition
of `idecode_issue'; libsim.a(irun.o):sim/v850/idecode.h:71: first
defined here
sim/igen
PR sim/26194
* lf.h (lf_get_file_type): Declare.
* lf.c (lf_get_file_type): Define.
* gen-idecode.c (print_idecode_issue_function_header): Use
lf_get_file_type() to issue an extern variable declaration in
case of header files.
GCC 10 enables -fno-common by default. This resulted in a multiple
definition linker error since global variables were declared and defined
in a header file:
ld: ld-insn.o:sim/ppc/ld-insn.h:221: multiple definition of
`max_model_fields_len'; igen.o:sim/ppc/ld-insn.h:221: first defined here
sim/ppc
* ld-insn.h (last_model, last_model_data, last_model_function,
last_model_internal, last_model_macro, last_model_static):
Delete.
(max_model_fields_len, model_data, model_functions,
model_internal, model_macros, model_static, models): Declare, but do not
define.
* ld-insn.c (last_model, last_model_data, last_model_function,
last_model_internal, last_model_macro, last_model_static,
max_model_fields_len, model_data, model_functions,
model_internal, model_macros, model_static, models): Define.
A comment in the implementation of blr says:
/* The pseudo code in the spec says we update LR before fetching.
the value from the rn. */
With 'rn' being the register holding the destination address.
This may have been true at one point, but the ISA manual now clearly
shows the destination register being read before the link register is
written.
This commit updates the implementation of blr to match.
sim/aarch64/ChangeLog:
PR sim/25318
* simulator.c (blr): Read destination register before calling
aarch64_save_LR.
Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064
The MSP430X RRUX instruction (unsigned right shift) is synthesized as
the RRC (rotate right through carry) instruction, but with the ZC
(zero carry) bit of the opcode extention word set.
Ensure the carry flag is ignored when the ZC bit is set.
sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
an RRC instruction, if the ZC bit of the extension word is set.
sim/testsuite/sim/msp430/ChangeLog:
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* rrux.s: New test.
When trying to compile GDB with --target=avr, with gcc 9.2.0, I am
getting a bunch of:
/home/simark/src/binutils-gdb/sim/avr/../common/nrun.c:94:7: error: implicit declaration of function ‘abort’ [-Werror=implicit-function-declaration]
94 | abort ();
| ^~~~~
/home/simark/src/binutils-gdb/sim/avr/../common/nrun.c:94:7: error: incompatible implicit declaration of built-in function ‘abort’ [-Werror]
/home/simark/src/binutils-gdb/sim/avr/../common/nrun.c:94:7: note: include ‘<stdlib.h>’ or provide a declaration of ‘abort’
I did what the compiler told me and added the relevant includes in the
problematic files.
sim/common/ChangeLog:
* nrun.c: Include stdlib.h.
* sim-core.c: Likewise.
* sim-engine.c: Likewise.
* sim-io.c: Likewise.
* sim-module.c: Likewise.
* sim-reason.c: Likewise.
PR build/24572 notes that "make install-strip" fails. For me, it
works in every directory except "sim", so this patch adds
install-strip targets to the Makefiles that appear there.
sim/ChangeLog
2019-12-19 Tom Tromey <tromey@adacore.com>
PR build/24572:
* Makefile.in (install-strip): New target.
sim/common/ChangeLog
2019-12-19 Tom Tromey <tromey@adacore.com>
PR build/24572:
* Makefile.in (install-strip): New target.
sim/igen/ChangeLog
2019-12-19 Tom Tromey <tromey@adacore.com>
PR build/24572:
* Makefile.in (install-strip): New target.
sim/ppc/ChangeLog
2019-12-19 Tom Tromey <tromey@adacore.com>
PR build/24572:
* Makefile.in (install-strip): New target.
sim/testsuite/ChangeLog
2019-12-19 Tom Tromey <tromey@adacore.com>
PR build/24572:
* Makefile.in (install-strip): New target.
Change-Id: I76613bc5c7e7812284f33826f8a5d914477fcdc5
This change adds support for the unlink system call, which is
required by the GCC testsuite. It also switches read/write/open
system calls to use the sim_io_* functions.
2019-12-14 Anthony Green <green@moxielogic.com>
* interp.c (sim_engine_run): Make use of sim_io_* functions for
read/write/open system calls. Implement the unlink system call.
Newer GCC's have switched to -fno-common by default, and this breaks the build
for the ARM sim, like this:
binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:65: multiple definition of `DSPsc'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:134: first defined here
binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:64: multiple definition of `DSPacc'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:133: first defined here
binutils-gdb.git~gdb-8.3-release/sim/arm/maverick.c:63: multiple definition of `DSPregs'; libsim.a(wrapper.o):binutils-gdb.git~gdb-8.3-release/sim/arm/wrapper.c:132: first defined here
I also noticed a few warnings due to mismatching types, as follows:
../../../../repos/binutils-gdb/sim/arm/wrapper.c: In function ‘sim_create_inferior’:
../../../../repos/binutils-gdb/sim/arm/wrapper.c:335:16: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
for (arg = argv; *arg != NULL; arg++)
^
../../../../repos/binutils-gdb/sim/arm/wrapper.c:342:8: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
arg = argv;
^
../../../../repos/binutils-gdb/sim/arm/wrapper.c:345:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
for (arg = argv; *arg != NULL; arg++)
^
The following patch fixes both of the above.
sim/arm/ChangeLog:
2019-12-06 Luis Machado <luis.machado@linaro.org>
* armemu.c (isize): Move this declaration ...
* arminit.c (isize): ... here.
* maverick.h: New file.
* wrapper.c: Include "maverick.h".
(<struct maverick_regs>, <union maverick_acc_regs>): Remove and update
comment.
(sim_create_inferior): Cast variables to proper type.
* maverick.c: Include "maverick.h".
(<struct maverick_regs>, <union maverick_acc_regs>): Move
declarations to maverick.h and update comment.
(DSPsc, DSPacc, DSPregs): Adjust comment.
Change-Id: I21db699d3b61b2de8c44053e47be4387285af28f
Representation of max 32-bit integer is 10 chars.
The potential issue is observed by GCC 7 targeted to AArch64.
sim/common/ChangeLog:
2019-12-01 Pavel I. Kryukov <kryukov@frtk.ru>
* sim-utils.c: Prevent buffer overflow.
sim/testsuite/ChangeLog:
* configure: Regenerate.
sim/testsuite/sim/pru/ChangeLog:
* add.s: New test.
* allinsn.exp: New file.
* dmem-zero-pass.s: New test.
* dmem-zero-trap.s: New test.
* dram.s: New test.
* jmp.s: New test.
* loop-imm.s: New test.
* loop-reg.s: New test.
* mul.s: New test.
* subreg.s: New test.
* testutils.inc: New file.
This is a simple test to ensure that the l.adrp instruction can be assembled and
simulated correctly.
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* adrp.S: New file.
This is a very basic test but it ensure the machine is wired up
correctly and that the assembler works.
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* fpu64a32.S: New file.
Define and wire up unordered floating point comparison operations for cgen
targets. This patch depends on my posted cgen patches[0].
[0] https://www.sourceware.org/ml/cgen/2019-q2/msg00013.html
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-accfp.c (unorderedsf, unordereddf): New functions.
(cgen_init_accurate_fpu): Wire up unorderedsf and unordereddf.
* cgen-fpu.h (cgen_fp_ops): Define fields unorderedsf and unordereddf.
Up until now these have not been used in any CGEN targets, add them as
they are now used by OpenRISC.
sim/common/ChangeLog:
* cgen-accfp.c (floatdidf, fixdfdi): New functions.
(cgen_init_accurate_fpu): Add floatdidf and fixdfdi.
When using writes to memory through a struct to merge and extract
multi-word value, it is the endianness of the host, not the target
that affects which order the component words need to be written into
the structure.
Of the 5 functions adjusted here 4 of them are unused. The 5th,
JOINSIDF will soon be used by the or1k target.
For or1k, simulated on x86-64, this change fixes this function so that
the correct bytes are now returned.
sim/common/ChangeLog:
* cgen-ops.h (SUBWORDXFSI): Compare HOST_BYTE_ORDER not
CURRENT_TARGET_BYTE_ORDER.
(SUBWORDTFSI): Likewise.
(JOINSIDF): Likewise.
(JOINSIXF): Likewise.
(JOINSITF): Likewise.
This commit:
commit ef9866970c
Date: Thu Mar 28 06:40:30 2019 +0900
sim/common: convert sim-arange to use sim-inline
broke many simulator targets. I fixed aarch64 in a previous commit
without realising how many other target were also broken.
This commit adds the missing includes (sim-assert.h and libiberty.h),
which seem to be needed by many simulator targets, in a central
location, this should fix most builds.
sim/common/ChangeLog:
* sim-base.h: Add 'sim-assert.h' include.
* sim-basics.h: Add 'libiberty.h' include.
This commit:
commit ef9866970c
Date: Thu Mar 28 06:40:30 2019 +0900
sim/common: convert sim-arange to use sim-inline
Broke the simulator build for aarch64 - some required macros are no
longer included where needed, fixed in this commit.
sim/aarch64/ChangeLog:
* cpustate.c: Add 'libiberty.h' include.
* interp.c: Add 'sim-assert.h' include.
During building of several cgen simulator's I notices the below
warnings. Adding includes fixes these.
Including config.h allows stdio.h to properly configure itself to expose
asprintf().
The other warnings for abort, free, memset, strlen are trivial.
Warnings:
../../../binutils-gdb/sim/or1k/../common/sim-watch.c: In function ‘sim_watchpoint_install’:
../../../binutils-gdb/sim/or1k/../common/sim-watch.c:415:10: warning: implicit declaration of function ‘asprintf’; did you mean ‘vasprintf’? [-Wimplicit-function-declaration]
if (asprintf (&name, "watch-%s-%s",
^~~~~~~~
vasprintf
../../../binutils-gdb/sim/lm32/../common/hw-device.c: In function ‘hw_strdup’:
../../../binutils-gdb/sim/lm32/../common/hw-device.c:59:34: warning: implicit declaration of function ‘strlen’ [-Wimplicit-function-declaration]
char *dup = hw_zalloc (me, strlen (str) + 1);
^~~~~~
../../../binutils-gdb/sim/lm32/../common/hw-events.c: In function ‘hw_event_queue_schedule’:
../../../binutils-gdb/sim/lm32/../common/hw-events.c:92:3: warning: implicit declaration of function ‘memset’ [-Wimplicit-function-declaration]
memset (&dummy, 0, sizeof dummy);
^~~~~~
../../../binutils-gdb/sim/lm32/../common/hw-handles.c: In function ‘hw_handle_remove_ihandle’:
../../../binutils-gdb/sim/lm32/../common/hw-handles.c:211:4: warning: implicit declaration of function ‘free’ [-Wimplicit-function-declaration]
free (delete);
^~~~
../../../binutils-gdb/sim/lm32/../common/sim-fpu.c: In function ‘pack_fpu’:
../../../binutils-gdb/sim/lm32/../common/sim-fpu.c:292:7: warning: implicit declaration of function ‘abort’ [-Wimplicit-function-declaration]
abort ();
^~~~~
sim/common/ChangeLog:
* sim-options.c: Include "config.h".
Include <stdio.h>.
* sim-watch.c: Include "config.h".
Include <stdio.h>.
* hw-device.c: Include <string.h>.
* hw-events.c: Include <string.h>.
* hw-handles.c: Include <stdlib.h>.
* sim-fpu.c: Include <stdlib.h>.
This fixes a TODO item and also fixes an error which we get when
building with no optimizations (-O0) in at least gcc 8.2.1.
Tested with sims that use cgen code lm32, or1k, cris, m32r and inlining
is working corretly.
Reference Error:
gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"or1200"' -DWITH_ALIGNMENT=STRICT_ALIGNMENT \
-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 -DWITH_TARGET_ADDRESS_BITSIZE=32 \
-DWITH_TARGET_BYTE_ORDER=BFD_ENDIAN_BIG -DDEFAULT_INLINE=0 -DWITH_SCACHE=16384 \
-I. -I../../../binutils-gdb/sim/or1k -I../common -I../../../binutils-gdb/sim/or1k/../common \
-I../../include -I../../../binutils-gdb/sim/or1k/../../include -I../../bfd \
-I../../../binutils-gdb/sim/or1k/../../bfd -I../../opcodes -I../../../binutils-gdb/sim/or1k/../../opcodes \
-g -o run nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a \
-ldl -lz -lm
/usr/bin/ld: libsim.a(mloop.o): in function `extract':
/home/shorne/work/openrisc/gdb-musl/sim/or1k/mloop.c:82: undefined reference to `sim_addr_range_hit_p'
/usr/bin/ld: /home/shorne/work/openrisc/gdb-musl/sim/or1k/mloop.c:83: undefined reference to `sim_addr_range_hit_p'
collect2: error: ld returned 1 exit status
make[3]: *** [Makefile:305: run] Error 1
sim/common/ChangeLog:
* Make-common.in (sim-arange_h): Remove sim-arange.c
* sim-arange.c: Remove SIM_ARANGE_C.
Add ifdef for _SIM_ARANGE_C_.
Include "sim-arange.h".
Remove include for unused "sim-assert.h".
Remove DEFINE_INLINE_P. Remove DEFINE_NON_INLINE_P.
(sim_addr_range_add): Declare as INLINE_SIM_ARANGE.
(sim_addr_range_delete): Declare as INLINE_SIM_ARANGE.
(sim_addr_range_hit_p): Change from SIM_ARANGE_INLINE to
INLINE_SIM_ARANGE.
* sim-arange.h (sim_addr_range_add): Declare as
INLINE_SIM_ARANGE.
(sim_addr_range_delete): Declare as INLINE_SIM_ARANGE.
(sim_addr_range_hit_p) Declare as INLINE_SIM_ARANGE.
Remove definition of SIM_ARANGE_INLINE.
Remove [HAVE_INLINE].
Wrap include "sim-arange.c" in H_REVEALS_MODULE_P.
* sim-base.h: Include "sim-arange.h"
* sim-basics.h: Remove include of "sim-arange.h"
* sim-inline.c: Include "sim-arange.c"
* sim-inline.h: Define INLINE_SIM_ARANGE.
Define SIM_ARANGE_INLINE. Define EXTERN_SIM_ARANGE_P.
Define STATIC_INLINE_SIM_ARANGE. Define STATIC_SIM_ARANGE.
Simon pointed out that the "common/" include change in gdb broke the
sim build. The problem was that the sim was using gdb's
create-version.sh, which changed.
This patch copies create-version.sh to the sim, so that it can
generate "version.c" in a way that works in the sim build.
Tested by rebuilding.
sim/common/ChangeLog
2019-01-26 Tom Tromey <tom@tromey.com>
* Make-common.in (version.c): Use sim's create-version.sh.
* create-version.sh: New file.
sim/ppc/ChangeLog
2019-01-26 Tom Tromey <tom@tromey.com>
* Makefile.in (version.c): Use sim's create-version.sh.
I applied the patch "Do not expand macros to 'defined'" by hand because
I couldn't apply it with git-am, and of course forgot to remove the
macro definitions. This patch fixes it, and also makes the ChangeLog
entry a bit cleaner.
Expanding a macro which contains 'defined' PP keyword is UB. It causes
a compilation failure when -Wexpansion-to-defined is used.
sim/common/Changelog:
2019-01-16 Pavel I. Kryukov <kryukov@frtk.ru>
* sim-arange.c: eliminate DEFINE_NON_INLINE_P
If HAVE_INLINE is false, SIM_ARANGE_INLINE is currently defined as
#define SIM_ARANGE_INLINE EXTERN
However, EXTERN is not defined anywhere, leading to errors such as:
In file included from
/mipt-mips/simulator/../../sim/common/sim-basics.h:147:0,
from /mipt-mips/simulator/export/gdb/sim-main.h:13,
from /mipt-mips/simulator/export/gdb/gdb_interface.cpp:7:
/mipt-mips/simulator/../../sim/common/sim-arange.h:71:27: error: ‘EXTERN’
does not name a type; did you mean ‘EUSERS’?
#define SIM_ARANGE_INLINE EXTERN
^
/mipt-mips/simulator/../../sim/common/sim-arange.h:76:1: note: in expansion
of macro ‘SIM_ARANGE_INLINE’
SIM_ARANGE_INLINE int
^~~~~~~~~~~~~~~~~
I (Simon) have reproduced the problem by simply removing the HAVE_INLINE
definition. This was originally reported by Pavel I. Kryukov
<kryukov@frtk.ru>.
sim/common/ChangeLog:
* sim-arange.h (SIM_ARANGE_INLINE): Change EXTERN to extern.
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
The host syscall callback mechanism should take care of updating the
errcode within the CB_SYSCALL struct, and we should not be adjusting
the error code once the syscall has completed. We especially, should
not be rewriting the syscall errcode based on the value of errno some
time after running the host syscall, as there is no guarantee that
errno has not be overwritten.
To perform a syscall we call cb_syscall (in syscall.c). To return
from cb_syscall control passes through one of two exit paths these are
labeled FinishSyscall and ErrorFinish and are reached using goto
statements scattered throughout the cb_syscall function.
In FinishSyscall we store the syscall result in 'sc->result', and the
error code is transated to target encoding, and stored in
'sc->errcode'.
In ErrorFinish, we again store the syscall result in 'sc->result', and
fill in 'sc->errcode' by fetching the actual errno from the host with
the 'cb->get_errno' callback.
In both cases 'sc->errcode' will have been filled in with an
appropriate value.
Further, if we look at a specific syscall example, CB_SYS_open, in
this case the first thing we do is fetch the path to open from the
target with 'get_path', if this fails then the errcode is returned,
and we jump to FinishSyscall. Notice that in this case, no host
syscall may have been performed, for example a failure to read the
path to open out of simulated memory can return EINVAL without
performing any host syscall. Given that no host syscall has been
performed, reading the host errno makes absolutely no sense.
This commit removes from sim_syscall_multi the rewriting of
sc->errcode based on the value of errno, and instead relies on the
value stored in the cb_syscall.
sim/common/ChangeLog:
* sim-syscall.c (sim_syscall_multi): Don't update sc->errcode at
this point, it should have already been set in cb_syscall.
Don't assume that cgen is located within the binutils-gdb tree. We
already have CGEN_CPU_DIR and CPU_DIR defined, these are the cpu/
directory within cgen, and the cpu/ directory within binutils-cpu.
The cris target tries to find CPU_DIR relative to the cgen source
tree, which can be wrong when building with an out of tree cgen.
sim/cris/ChangeLog:
* Makefile.in: Replace uses of CGEN_CPU_DIR with CPU_DIR, and
remove the definition of CGEN_CPU_DIR.
When configuring with '--enbale-cgen-maint' the default for both the
opcodes/ and sim/ directories is to assume that the cgen source is
within the binutils-gdb source tree as binutils-gdb/cgen/.
In the old cvs days, this worked well, as cgen was just another
sub-module of the single cvs repository and could easily be checked
out within the binutils-gdb directory, and managed by cvs in the
normal way.
Now that binutils-gdb is in git, while cgen is still in cvs, placing
the cgen respository within the binutils-gdb tree is more troublesome,
and it would be nice if the two tools could be kept separate.
Luckily there is already some initial code in the configure.ac files
for both opcodes/ and sim/ to support having cgen be located outside
of the binutils-gdb tree, however, this was speculative code written
imagining a future where cgen would be built and installed to some
location.
Right now there is no install support for cgen, and so the configure
code in opcodes/ and sim/ doesn't really do anything useful. In this
commit I repurpose this code to allow binutils-gdb to be configured so
that it can make use of a cgen source directory that is outside of the
binutils-gdb tree.
With this commit applied it is now possible to configure and build
binutils-gdb like this:
/path/to/binutils-gdb/src/configure --enable-cgen-maint=/path/to/cgen/src/cgen/
make all-opcodes
make -C opcodes run-cgen-all
Just in case anyone is still using cgen inside the binutils-gdb tree,
I have left the default behaviour of '--enable-cgen-maint' (with no
parameter) unchanged, that is it looks for the cgen directory as
'binutils-gdb/cgen/'.
opcodes/ChangeLog:
* configure.ac (enable-cgen-maint): Support passing path to cgen
source tree.
* configure: Regenerate.
sim/ChangeLog:
* common/acinclude.m4 (enable-cgen-maint): Support passing path to
cgen source tree.
* cris/configure: Regenerate.
* frv/configure: Regenerate.
* iq2000/configure: Regenerate.
* lm32/configure: Regenerate.
* m32r/configure: Regenerate.
* or1k/configure: Regenerate.
* sh64/configure: Regenerate.
This removes a Cygwin-specific libtermcap hack that was dependent on
the presence of one of the multiple alternative libraries. The one it
was hard-coded to pick isn't included with Cygwin anymore.
According to Corinna, libtermcap was removed from Cygwin a long time
ago, and libncurses is used in Cygwin for a long time too.
The fix is to make Cygwin use the same autoconf code to figure out the
correct lib as any other target.
sim/erc32/Changelog:
2018-10-30 Joel Sherrill <joel@rtems.org>
* configure.ac: Remove the Cygwin-specific libtermcap.a hack
and use the standard logic to determine which library to use.
* configure: Regenerate.
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
This code was introduced back in 1998, and C99 appeared next year,
defining the `xor` as an 'alternative keyword' if iso646.h is
included. Moreover, C++98 defines it on the language level. As a
result, the code is not buildable with C++ compiler or if iso646.h is
included beforehand.
According to comment, `sim_cpu_core` is mostly a clone of `sim_core`,
so I renamed it to `byte_xor` as it's called in `sim_core`.
sim/common/ChangeLog:
* sim-core.h (sim_cpu_core): Rename cpu_core.xor to
cpu_core.byte_xor.
* sim-core.c (sim_core_set_xor): Likewise.
(sim_core_xor_read_buffer): Likewise.
(sim_core_xor_write_buffer): Likewise.
binutils/
* MAINTAINERS: Update my e-mail address, downgrade to MIPS I-IV
ISA maintenance.
gdb/
* MAINTAINERS: Update my e-mail address, downgrade to MIPS I-IV
ISA maintenance.
sim/
* MAINTAINERS: Update my e-mail address, downgrade to MIPS I-IV
ISA maintenance.
Since I helped upstream the or1k port I would like to claim myself as
maintainer.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* MAINTAINERS (or1k): Add myself as or1k maintainer.
Signed-off-by: Stafford Horne <shorne@gmail.com>
When trying to run the update-gnulib.sh script in gdb, I get this:
Error: Wrong automake version (Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\${ <-- HERE ([^ =:+{}]+)}/ at /opt/automake/1.11.1/bin/automake line 4113.), we need 1.11.1.
Aborting.
Apparently, it's an issue with a regex in automake that triggers a
warning starting with Perl 5.22. It has been fixed in automake 1.15.1.
So I think it's a good excuse to bump the versions of autoconf and
automake used in the gnulib import. And to avoid requiring multiple
builds of autoconf/automake, it was suggested that we bump the required
version of those tools for all binutils-gdb.
For autoconf, the 2.69 version is universally available, so it's an easy
choice. For automake, different distros and distro versions have
different automake versions. But 1.15.1 seems to be the most readily
available as a package. In any case, it's easy to build it from source.
I removed the version checks from AUTOMAKE_OPTIONS and AC_PREREQ,
because I don't think they are useful in our case. They only specify a
lower bound for the acceptable version of automake/autoconf. That's
useful if you let the user choose the version of the tool they want to
use, but want to set a minimum version (because you use a feature that
was introduced in that version). In our case, we force people to use a
specific version anyway. For the autoconf version, we have the check in
config/override.m4 that enforces the version we want. It will be one
less thing to update next time we change autotools version.
I hit a few categories of problems that required some changes. They are
described below along with the chosen solutions.
Problem 1:
configure.ac:17: warning: AM_INIT_AUTOMAKE: two- and three-arguments forms are deprecated. For more info, see:
configure.ac:17: http://www.gnu.org/software/automake/manual/automake.html#Modernize-AM_005fINIT_005fAUTOMAKE-invocation
Solution 1:
Adjust the code based on the example at that URL.
Problem 2 (in zlib/):
Makefile.am: error: required file './INSTALL' not found
Makefile.am: 'automake --add-missing' can install 'INSTALL'
Makefile.am: error: required file './NEWS' not found
Makefile.am: error: required file './AUTHORS' not found
Makefile.am: error: required file './COPYING' not found
Makefile.am: 'automake --add-missing' can install 'COPYING'
Solution 2:
Add the foreign option to AUTOMAKE_OPTIONS.
Problem 3:
doc/Makefile.am:20: error: support for Cygnus-style trees has been removed
Solution 3:
Remove the cygnus options.
Problem 4:
Makefile.am:656: warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Solution 4:
Rename "INCLUDES = " to "AM_CPPFLAGS += " (because AM_CPPFLAGS is
already defined earlier).
Problem 5:
doc/Makefile.am:71: warning: suffix '.texinfo' for Texinfo files is discouraged; use '.texi' instead
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 5:
Rename .texinfo files to .texi.
Problem 6:
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 6:
Remove the hack at the bottom of doc/Makefile.am and use
the info-in-builddir automake option.
Problem 7:
doc/Makefile.am:35: error: required file '../texinfo.tex' not found
doc/Makefile.am:35: 'automake --add-missing' can install 'texinfo.tex'
Solution 7:
Use the no-texinfo.tex automake option. We also have one in
texinfo/texinfo.tex, not sure if we should point to that, or move it
(or a newer version of it added with automake --add-missing) to
top-level.
Problem 8:
Makefile.am:131: warning: source file 'config/tc-aarch64.c' is in a subdirectory,
Makefile.am:131: but option 'subdir-objects' is disabled
automake: warning: possible forward-incompatibility.
automake: At least a source file is in a subdirectory, but the 'subdir-objects'
automake: automake option hasn't been enabled. For now, the corresponding output
automake: object file(s) will be placed in the top-level directory. However,
automake: this behaviour will change in future Automake versions: they will
automake: unconditionally cause object files to be placed in the same subdirectory
automake: of the corresponding sources.
automake: You are advised to start using 'subdir-objects' option throughout your
automake: project, to avoid future incompatibilities.
Solution 8:
Use subdir-objects, that means adjusting references to some .o that will now
be in config/.
Problem 9:
configure.ac:375: warning: AC_LANG_CONFTEST: no AC_LANG_SOURCE call detected in body
../../lib/autoconf/lang.m4:193: AC_LANG_CONFTEST is expanded from...
../../lib/autoconf/general.m4:2601: _AC_COMPILE_IFELSE is expanded from...
../../lib/autoconf/general.m4:2617: AC_COMPILE_IFELSE is expanded from...
../../lib/m4sugar/m4sh.m4:639: AS_IF is expanded from...
../../lib/autoconf/general.m4:2042: AC_CACHE_VAL is expanded from...
../../lib/autoconf/general.m4:2063: AC_CACHE_CHECK is expanded from...
configure.ac:375: the top level
Solution 9:
Use AC_LANG_SOURCE, or use proper quoting.
Problem 10 (in intl/):
configure.ac:7: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS
/usr/share/aclocal/threadlib.m4:36: gl_THREADLIB_EARLY_BODY is expanded from...
/usr/share/aclocal/threadlib.m4:29: gl_THREADLIB_EARLY is expanded from...
/usr/share/aclocal/threadlib.m4:318: gl_THREADLIB is expanded from...
/usr/share/aclocal/lock.m4:9: gl_LOCK is expanded from...
/usr/share/aclocal/intl.m4:211: gt_INTL_SUBDIR_CORE is expanded from...
/usr/share/aclocal/intl.m4:25: AM_INTL_SUBDIR is expanded from...
/usr/share/aclocal/gettext.m4:57: AM_GNU_GETTEXT is expanded from...
configure.ac:7: the top level
Solution 10:
Add AC_USE_SYSTEM_EXTENSIONS in configure.ac.
ChangeLog:
* libtool.m4: Use AC_LANG_SOURCE.
* configure.ac: Remove AC_PREREQ, use AC_LANG_SOURCE.
* README-maintainer-mode: Update version requirements.
* ar-lib: New file.
* test-driver: New file.
* configure: Re-generate.
bfd/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
(INCLUDES): Rename to ...
(AM_CPPFLAGS): ... this.
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9, cygnus, add
info-in-builddir no-texinfo.tex.
(info_TEXINFOS): Rename bfd.texinfo to bfd.texi.
* doc/bfd.texinfo: Rename to ...
* doc/bfd.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove cygnus, add
info-in-builddir no-texinfo.tex.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
config/ChangeLog:
* override.m4 (_GCC_AUTOCONF_VERSION): Bump from 2.64 to 2.69.
etc/ChangeLog:
* configure.in: Remove AC_PREREQ.
* configure: Re-generate.
gas/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
(TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix.
* configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles,
extra_objects): Add config/ prefix.
* doc/as.texinfo: Rename to...
* doc/as.texi: ... this.
* doc/Makefile.am: Rename as.texinfo to as.texi throughout.
Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and
info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gdb/ChangeLog:
* common/common-defs.h (PACKAGE_NAME, PACKAGE_VERSION,
PACKAGE_STRING, PACKAGE_TARNAME): Undefine.
* configure.ac: Remove AC_PREREQ, add missing quoting.
* gnulib/configure.ac: Modernize usage of
AC_INIT/AM_INIT_AUTOMAKE. Remove AC_PREREQ.
* gnulib/update-gnulib.sh (AUTOCONF_VERSION): Bump to 2.69.
(AUTOMAKE_VERSION): Bump to 1.15.1.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
* gnulib/aclocal.m4: Re-generate.
* gnulib/config.in: Re-generate.
* gnulib/configure: Re-generate.
* gnulib/import/Makefile.in: Re-generate.
gdb/gdbserver/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
gdb/testsuite/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
gold/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting and usage
of AC_LANG_SOURCE.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.11, add info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* gconfig.in: Re-generate.
intl/ChangeLog:
* configure.ac: Add AC_USE_SYSTEM_EXTENSIONS, remove AC_PREREQ.
* configure: Re-generate.
* config.h.in: Re-generate.
* aclocal.m4: Re-generate.
ld/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack, rename ld.texinfo to
ld.texi, ldint.texinfo to ldint.texi throughout.
(AUTOMAKE_OPTIONS): Add info-in-builddir.
* README: Rename ld.texinfo to ld.texi, ldint.texinfo to
ldint.texi throughout.
* gen-doc.texi: Likewise.
* h8-doc.texi: Likewise.
* ld.texinfo: Rename to ...
* ld.texi: ... this.
* ldint.texinfo: Rename to ...
* ldint.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
libdecnumber/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* aclocal.m4.
libiberty/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* config.in: Re-generate.
opcodes/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
* configure.ac: Remove AC_PREREQ.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
readline/ChangeLog.gdb:
* configure: Re-generate.
* examples/rlfe/configure: Re-generate.
sim/ChangeLog:
* All configure.ac: Remove AC_PREREQ.
* All configure: Re-generate.
zlib/ChangeLog.bin-gdb:
* configure.ac: Modernize AC_INIT call, remove AC_PREREQ.
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add
foreign.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
Following my recent transition from Imagination Technologies to the
reincarnated MIPS company update MAINTAINERS entries accordingly.
binutils/
* MAINTAINERS: Update my company e-mail address.
gdb/
* MAINTAINERS: Update my company e-mail address.
sim/
* MAINTAINERS: Update my company e-mail address.
This is the testsuite for the or1k sim, it tests running many of the
basic architecture instructions on the openrisc sim.
sim/testsuite/sim/or1k/ChangeLog:
2017-12-12 Peter Gavin <pgavin@gmail.com>
Stafford Horne <shorne@gmail.com>
* add.S: New file.
* alltests.exp: New file.
* and.S: New file.
* basic.S: New file.
* div.S: New file.
* ext.S: New file.
* find.S: New file.
* flag.S: New file.
* fpu.S: New file.
* jump.S: New file.
* load.S: New file.
* mac.S: New file.
* mfspr.S: New file.
* mul.S: New file.
* or.S: New file.
* or1k-asm-test-env.h: New file.
* or1k-asm-test-helpers.h: New file.
* or1k-asm-test.h: New file.
* or1k-asm.h: New file.
* or1k-test.ld: New file.
* ror.S: New file.
* shift.S: New file.
* spr-defs.h: New file.
* sub.S: New file.
* xor.S: New file.
sim/testsuite/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
These are separted out to make the patch easier to read and smaller.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
* or1k/aclocal.m4: Generated.
* or1k/config.in: Generated.
* or1k/configure: Generated.
These are the simulator files generated by cgen. These are split out
from the main sim patch to make the patch easier to review and smaller.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* or1k/arch.c: Generated.
* or1k/arch.h: Generated.
* or1k/cpu.c: Generated.
* or1k/cpu.h: Generated.
* or1k/cpuall.h: Generated.
* or1k/decode.c: Generated.
* or1k/decode.h: Generated.
* or1k/model.c: Generated.
* or1k/sem-switch.c: Generated.
* or1k/sem.c: Generated.
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN
based sim so the bulk of the code is generated from the .cpu files by
CGEN. The engine decode and execute logic in mloop uses scache with
pseudo-basic-block extraction and supports both full and fast (switch)
modes.
The sim does not implement an mmu at the moment. The sim does implement
fpu instructions via the common sim-fpu implementation.
sim/ChangeLog:
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
* configure.tgt: Add or1k sim.
* or1k/README: New file.
* or1k/Makefile.in: New file.
* or1k/configure.ac: New file.
* or1k/mloop.in: New file.
* or1k/or1k-sim.h: New file.
* or1k/or1k.c: New file.
* or1k/sim-if.c: New file.
* or1k/sim-main.h: New file.
* or1k/traps.c: New file.
FT32B is a new FT32 family member.
This patch adds support for the compressed instructions to gdb and sim.
gdb/ChangeLog:
* ft32-tdep.c (ft32_fetch_instruction): New function.
(ft32_analyze_prologue): Use ft32_fetch_instruction().
sim/ChangeLog:
* ft32/interp.c (step_once): Add ft32 shortcode decoder.
FT32B is a new FT32 family member. It has a code
compression scheme, which requires the use of linker
relaxations. The change is quite large, so submission
is in several parts.
Part 1 adds a 15-bit instruction field, and CPU-specific functions for
the code compression that are used in binutils and GDB.
bfd/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-ft32.c: Add HOWTO R_FT32_15.
* reloc.c: Add BFD_RELOC_FT32_15.
gas/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with
K15.
(md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15.
include/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* elf/ft32.h: Add R_FT32_15.
* opcode/ft32.h: Replace FT32_FLD_K8 with K15.
(ft32_shortcode, sc_compar, ft32_split_shortcode,
ft32_merge_shortcode, ft32_merge_shortcode): New functions.
opcodes/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
* opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
K15. Add jmpix pattern.
sim/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
This patch fixes the build failure by using disassembler to get
disassemble function pointer, and do the disassembly, because
print_insn_little_arm is no longer visible outside opcodes/
binutils-gdb/sim/arm/wrapper.c:98:10: error: implicit declaration of function 'print_insn_little_arm' [-Werror=implicit-function-declaration]
size = print_insn_little_arm (0, & info);
^
sim/arm:
2017-09-21 Yao Qi <yao.qi@linaro.org>
* wrapper.c (print_insn): Use disassembler instead of
print_insn_little_arm.
Previously this used the error function from GDB directly when linked
against GDB instead of the error method in the host callbacks
structure. This was exposed via a link error when GDB was converted
to C++. The error function invokes the error callback similar to
sim_io_error.
Note that there are also error functions in sim/ppc/main.c and
sim/ppc/misc.c. The ppc libsim.a expects each consumer to provide
several symbols used by the library including "error". sim-calls.c
provides these symbols when the library is linked into gdb. The dgen,
igen, tmp-filter, tmp-ld-decode, tmp-ld-cache, and tmp-ld-insn programs
use the functions from misc.c. psim uses the functions from main.c.
sim/ppc/ChangeLog:
PR sim/20863
* sim_calls.c (error): New function.
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only. However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd. This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).
There isn't any functionality change.
binutils:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* objdump.c (disassemble_data): Caller update.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (disassembler): Update declaration.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* disassemble.c (disassembler): Add arguments a, big and mach.
Use them.
sim/common:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* sim-trace.c (trace_disasm): Caller update.
sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
sim/aarch64/
* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
flag check.
sim/testsuite/sim/aarch64/
* adds.s: Add checks for values -2 and 1, where C is not set.
sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
sim/aarch64/
* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
2. Move test_false if inside loop. Fix logic for computing result
stored to vd.
sim/testsuite/sim/aarch64
* bit.s: New.
sim/aarch64/
* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
(do_vec_LDn_single, do_vec_STn_single): New.
(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
loop over nregs using new var n. Add n times size to address in loop.
Add n to vd in loop.
(do_vec_load_store): Add comment for instruction bit 24. New var
single to hold instruction bit 24. Add new code to use single. Move
ldnr support inside single if statements. Fix ldnr register counts
inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
sim/testsuite/sim/aarch64/
* ldn_single.s: New.
* ldnr.s: New.
* stn_single.s: New.
sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
sim/aarch64
* simulator.c (NEG, POS): Move before set_flags_for_add64.
(set_flags_for_add64): Replace with a modified copy of
set_flags_for_sub64.
sim/testsuite/sim/aarch64
* testutils.inc (pass): Move .Lpass to start.
(fail): Move .Lfail to start. Return 1 instead of 0.
(start): Moved .Lpass and .Lfail to here.
* adds.s: New.
* fstur.s: New.
* tbnz.s: New.
When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU
implicitly. Restore the defines for these to the local sd and cpu vars.
This was broken by the clean up in commit d47f5b30d8.
Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
The common sim tracing code already handles loading and tracking of
symbols from the target program so that it can show symbol info in
trace/disassembly calls. Once we touch up the trace code and add a
few API callbacks, ports don't need to do loading and searching of
symbol tables themselves anymore.
A few funcs are only used locally, so mark them static to avoid warnings
due to -Wmissing-prototypes.
Some funcs cast the return value wrong, so drop them (and let void * just
work by default).
Update some prototypes to be new style.
The current machs.h mixes common enums with Blackfin-specific defines.
This causes us troubles with header inclusion order such that we can't
drop the old SIM_CPU typedef (which is duplicated in common code). By
splitting the two up, we can unwind this dependency chain, and drop the
old typedef. It also fixes building with older gcc versions.
* simulator.c (aarch64_step): Revert pervious delta.
(aarch64_run): Call sim_events_tick after each
instruction is simulated, and if necessary call
sim_events_process.
* simulator.h: Revert previous delta.
* interp.c (sim_create_inferior): Allow for being called with a
NULL abfd parameter. If a bfd is provided, initialise the sim
with that start address.
* simulator.c (HALT_NYI): Just print out the numeric value of the
instruction when not tracing.
(aarch64_step): Change from static to global.
* simulator.h: Add a prototype for aarch64_step().
The major reason this header was needed, bfd_default_set_arch_mach,
has now moved to bfd.h.
gdb/
* amd64-darwin-tdep.c: Don't include libbfd.h.
* i386-darwin-tdep.c: Likewise.
* rs6000-nat.c: Likewise.
* rs6000-tdep.c: Likewise.
sim/aarch64/
* memory.c: Don't include libbfd.h.
sim/rl78/
* load.c: Don't include libbfd.h.
(rl78_load): Don't use private iovec seek or read.
sim/rx/
* load.c: Don't include libbfd.h.
(rx_load): Don't use private iovec seek or read.
PR target/ 19401
* avr/interp.c (step_once): Pass break instruction address to
sim_engine_halt function which writes that to PC. Remove code that
follows that function call as it is unreachable.
* armemu.c (Multiply64): Only issue error messages about invalid
arguments if debugging is enabled.
* armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
* cpustate.h: Include config.h.
(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
use anonymous structs to align members.
* simulator.c (aarch64_step): Use sim_core_read_buffer and
endian_le2h_4 to read instruction from pc.
sim/sh/
* interp.c (dmul): Split into dmul_s and dmul_u. Use explicit integer
width types and simplify implementation.
* gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
PR 19872
bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised
version number if the version is zero.
bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised
version number if the version is zero.
* cpustate.c (aarch64_set_reg_s32): New function.
(aarch64_set_reg_u32): New function.
(aarch64_get_FP_half): Place half precision value into the correct
slot of the union.
(aarch64_set_FP_half): Likewise.
* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
aarch64_set_reg_u32.
* memory.c (FETCH_FUNC): Cast the read value to the access type
before converting it to the return type. Rename to FETCH_FUNC64.
(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
accesses. Use for 32-bit memory access functions.
* simulator.c (ldrsb_wb): Use sign extension not zero extension.
(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
(ldrsh_scale_ext, ldrsw_abs): Likewise.
(ldrh32_abs): Store 32 bit value not 64-bits.
(ldrh32_wb, ldrh32_scale_ext): Likewise.
(do_vec_MOV_immediate): Fix computation of val.
(do_vec_MVNI): Likewise.
(DO_VEC_WIDENING_MUL): New macro.
(do_vec_mull): Use new macro.
(do_vec_mul): Use new macro.
(do_vec_MLA): Read values before writing.
(do_vec_xtl): Likewise.
(do_vec_SSHL): Select correct shift value.
(do_vec_USHL): Likewise.
(do_scalar_UCVTF): New function.
(do_scalar_vec): Call new function.
(store_pair_u64): Treat reads of SP as reads of XZR.
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
register as a half precision floating point number.
(aarch64_set_FP_half): New function. Similar, but for setting
a half precision register.
(aarch64_get_thread_id): New function. Returns the value of the
CPU's TPIDR register.
(aarch64_get_FPCR): New function. Returns the value of the CPU's
floating point control register.
(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
register.
* cpustate.h: Add prototypes for new functions.
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
* memory.c: Use unaligned core access functions for all memory
reads and writes.
* simulator.c (HALT_NYI): Generate an error message if tracing
will not tell the user why the simulator is halting.
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
(INSTR): New time-saver macro.
(fldrb_abs): New function. Loads an 8-bit value using a scaled
offset.
(fldrh_abs): New function. Likewise for 16-bit values.
(do_vec_SSHL): Allow for negative shift values.
(do_vec_USHL): Likewise.
(do_vec_SHL): Correct computation of shift amount.
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
shifts and computation of shift value.
(clz): New function. Counts leading zero bits.
(do_vec_CLZ): New function. Implements CLZ (vector).
(do_vec_MOV_element): Call do_vec_CLZ.
(dexSimpleFPCondCompare): Implement.
(do_FCVT_half_to_single): New function. Implements one of the
FCVT operations.
(do_FCVT_half_to_double): New function. Likewise.
(do_FCVT_single_to_half): New function. Likewise.
(do_FCVT_double_to_half): New function. Likewise.
(dexSimpleFPDataProc1Source): Call new FCVT functions.
(do_scalar_SHL): Handle negative shifts.
(do_scalar_shift): Handle SSHR.
(do_scalar_USHL): New function.
(do_double_add): Simplify to just performing a double precision
add operation. Move remaining code into...
(do_scalar_vec): ... New function.
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
functions.
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
registers.
(system_set): New function.
(do_MSR_immediate): New function. Stub for now.
(do_MSR_reg): New function. Likewise. Partially implements MSR
instruction.
(do_SYS): New function. Stub for now,
(dexSystem): Call new functions.
* simulator.c (set_flags_for_sub32): Correct type of signbit.
(CondCompare): Swap interpretation of bit 30.
(DO_ADDP): Delete macro.
(do_vec_ADDP): Copy source registers before starting to update
destination register.
(do_vec_FADDP): Likewise.
(do_vec_load_store): Fix computation of sizeof_operation.
(rbit64): Fix type of constant.
(aarch64_step): When displaying insn value, display all 32 bits.
* cgen-scache.c (scache_option_handler): Prevent possible
undefined behaviour computing the size of the scache by using
unsigned integers instead of signed integers.
This fixes PR sim/19441. In the MIPS simulator the microMIPS
functions in micromips.igen were not predicated on the microMIPS
models. This was causing build issues for some target triples.
This patch sets all the microMIPS specific functions to only be built if
the micromips32, micromips64 or micromipsdsp models are used.
PR sim/19441
* micromips.igen (delayslot_micromips): Enable for `micromips32',
`micromips64' and `micromipsdsp' only.
(process_isa_mode): Enable for `micromips32' and `micromips64' only.
(do_micromips_jalr, do_micromips_jal): Likewise.
(compute_movep_src_reg): Likewise.
(compute_andi16_imm): Likewise.
(convert_fmt_micromips): Likewise.
(convert_fmt_micromips_cvt_d): Likewise.
(convert_fmt_micromips_cvt_s): Likewise.
(FMT_MICROMIPS): Likewise.
(FMT_MICROMIPS_CVT_D): Likewise.
(FMT_MICROMIPS_CVT_S): Likewise.
This patch makes a fair number of fixes in the various comments of
sim-fpu.c, mostly to either better conform to the GNU Coding Standards
(sentences start with a capital letter, end with a period), or to
fix spelling mistakes.
sim/common/ChangeLog:
* sim-fpu.c: Minor comment fixes throughout.
This patch just makes a copy of formatting changes to better conform
with the GNU Coding Style.
sim/common/ChangeLog:
* sim-fpu.c (print_bits): Minor reformatting (no code change).
(sim_fpu_map): Likewise.
The mips bfd will sign extend 32-bit addresses into 64-bit values,
so if the entry happens to be 0x80000000 or higher, it is turned to
0xffffffff80000000 which points to memory that doesn't exist.
This wasn't an issue until commit 26f8bf63bf
as all addresses were automatically truncated there in the translate
function to 32-bits. When we cleaned up that code, the full 64-bits
were checked leading to many test failures for mips-sde-elf targets
and such.
Rather than stuffing the command line with a bunch of -D flags, start
moving things to config.h which is managed by autoheader. This makes
the makefile a bit simpler and the build output tighter, and it makes
the migration to automake easier as there are fewer vars to juggle.
We'll want to move the other options out too, but it'll take more work.
This was imported from the ppc sim, but that was only used to control
a single file, and that is already governed by the hw models. There's
no need to have a sep configure option here, especially since none of
the other sims are using it. Even when the code is enabled, there's
no runtime overhead.
Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in
order to make the configure flag available. There's no real reason
to not allow this flag for all ports, so move it to the common sim
macro. This way we get standard behavior across all ports too.
Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order
to make the configure flag available, which none of them do. There's
no real reason to not allow this flag for all ports, so move it to the
common sim macro. This way we get standard behavior across all ports.
We don't have alternative nltvals.def files, so always symlinking
the targ-vals.def file to it doesn't gain us anything. It does
make the build more complicated though and a pain to convert to
something newer (like automake). Drop the symlinking entirely.
In the future, we'll want to explode this file anyways into the
respective arch dirs so things can be selected dynamically at
runtime, so it's not like we'll be bringing this back.
No other port calls this macro directly, and mips has it hardcoded
to the default -- disabling smp. In the future we'll enable this
for all targets in common code, so tidy up the mips code now.
Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order
to make the configure flag available. There's no real reason to not
allow this flag for all ports, so move it to the common sim macro.
This way we get standard behavior across all ports too.
These options were never exposed for most sims (just the ppc one),
and they are really only useful on 32-bit x86 systems. Considering
modern systems tend to be 64-bit x86_64 and how well modern compilers
are at optimizing code, these have outlived their usefulness.
No other sub directory provides such a configuration option, so
drop it from the sim dir as well. This cleans up a good bit of
code in the process.
If people want to use custom flags for just the sim, they can
still run configure+make by hand in the sim subdir and use the
normal CFLAGS settings.
Now that cconfig.h doesn't exist, there's no need to build in the common
subdir anymore. We leave the configure/Makefile files in there as there
is a helper for developers to generate the nltvals.def file. Once that
gets cleaned up in the future though, we can drop the build logic too.
The common subdir sets up a cconfig.h file to hold checks for the common
code. In practice, most files still end up using config.h instead which
just leads to confusion.
Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON
so we can drop the cconfig.h file altogether. Now there is only a single
config.h file like normal.
Some targets have started to add support for calling the disassembler
automatically when executing code. Add support for that directly into
the trace core.
The cris sim hit a few failures after the recent getopt logic, and the
expected output showed a few ways we can improve things to better match
other utils.
The compiler/C library should produce reasonable code for htonl/ntohl,
and at least glibc tries pretty hard to always produce good code for
them. This logic only had support for 32-bit x86 systems anymore, and
it's unlikely people were even opting into this, so drop it all.
The compiler should produce reasonable code here in general, so punt the
various arch checks and bswap defines. This code will eventually go away
entirely when we convert it to the common memory code.
Fix a long standing todo where we let getopt write directly to stderr
when an invalid option is passed. Use the sim io funcs instead as they
go through the filtered callbacks that gdb wants.
Clean up some more remains of WITH_DEVICES that escaped notice.
We also clean up GETTWI/SETTWI defines in a few ports where they
were copied & pasted and are unused as they happen to be near the
device code.
The --enable-sim-hostendian flag was purely so people had an escape route
for when cross-compiling. This is because historically, AC_C_BIGENDIAN
did not work in those cases. That was fixed a while ago though, so we can
require that macro everywhere now and simplify a good bit of code.
Rather than re-invent endian defines, as well as maintain our own list
of OS & arch-specific includes, punt all that logic in favor of the bfd
ones already set up and maintained elsewhere. We already rely on the
bfd library, so leveraging the endian aspect should be fine.
The iq2000/m32r/sh64 option parsing logic appears to have always been
dead. At least iq2000/sh64 are simply copy & paste rot from m32r.
The lm32 option parsing hack here hasn't been needed for a while -- this
was fixed back in commit 11409fac6b in the
common code.
The global current_state handle to the current simulator state is a
design idea that was half implemented, but never really cleaned up.
The point was to have a global variable pointing to the state so that
funcs could more quickly & easily access the state anywhere. We've
instead moved in the direction of passing state around everywhere and
don't have any intention of moving back.
I also can't find any references to gdb using this variable, or to
cgen related "dump_regs" functions, both of which were used in the
comments related to this code.
When connecting to the simulator in gdb, we don't want it to exit on
us when we pass down unknown/invalid/help/etc... options. Plumb down
the kind argument so we can handle both gdb & psim interfaces.
We can leverage the cpu->regs array rather than going through the
function helpers to get nice compact code.
Further, fix up the return values: return -1 when we can't find a
register (and let the caller write out warnings), return 2/4 when
we actually write out that amount, and handle the zero reg.
This array isn't used anywhere, and the init phase actually corrupts
some memory because the array has 18 elements but tries to set the
19th (ZERO) position.
This change tracks the "closed" state of file descriptors 0, 1, and 2,
introducing the function fdbad() to emul_netbsd.c and emul_unix.c.
Note that a function of the same name and purpose exists in
sim/common/callback.c.
This patch eliminates all of the "unresolved testcases" when testing
GDB against the powerpc simulator.
This occurs because the powerpc simulator closes, on behalf of the
testcase, the file descriptors associated with stdin, stdout, and
stderr. GDB still needs these descriptors to communicate with the
user or, in this case, with the testing framework.
The disasm framework reserves the private_data field for the disassemblers
themselves, not for people who use the disassembler. Instead, there is an
application_data field for callers such as the sim. Switch to it to avoid
random corruption/crashes when the disassemblers use private_data.
Pretty much all targets are using this module already, so add it to the
common list of objects. The only oddball out here is cris and that's
because it supports loading via an offset for all the phdrs. We drop
support for that.
No arch is using this anymore, and we want all new ports using the
hardware framework instead. Punt WITH_DEVICES and the two callbacks
device_io_{read,write}_buffer.
We can also punt the tconfig.h file as no port is using it anymore.
This fixes in-tree builds that get confused by picking up the wrong
one (common/ vs <port>/) caused by commit ae7d0cac8c.
Any port that needs to set up a global define can use their own
sim-main.h file that they must provide regardless.
The bfin port is using the WITH_DEVICES framework for two reasons:
- get access to the cpu making the request (if available)
- check the alignment & size for core & system MMRs
We addressed the first part with commit dea10706e9,
and we handle the second part with this commit. Arguably this is more
correct too because trying to do bad reads/writes directly (when devices
support is disabled) often results in bad memory accesses.
As part of this clean up, we also adjust all of the existing logic that
would reject invalid accesses: the code was relying on the checks never
returning, but that's not the case when things like gdb (via the user's
commands) are making the requests. Thus we'd still end up with bad mem
accesses, or sometimes gdb being hung due to while(1) loops.
Now we can connect (most of) these models into any address and have them
work correctly.
We set up an array of 3 elements and then index into it with a 2bit
value. We check the range before we actually use the pointer, but
the indexing is enough to make asan upset, so just stuff a fourth
value in there to keep things simple.
The bfin port has been using the device callback largely so it could be
passed the cpu when available. Add this logic to the common core code
so all ports get access to the active cpu.
The semantics of these buffer functions are changed slightly in that
errors halt the engine synchronously rather than returning the length
to the caller. We'll probably adjust this in a follow up commit.
The bfin code isn't updated just yet as it has a bit more logic in the
device layer that needs to be unwound at which point we can delete it
entirely.
The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address. When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded. If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.
Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.
The point of passing down the cpu to core reads/writes is to signal which
cpu is making the access. For system accesses (such as internal memory
initialization), passing the cpu down doesn't make sense, and in the case
of early init like cris, can cause crashes. Since the cpu isn't fully set
up at this point, if the core code tries to access some fields (like the
PC reg), it'll crash. While cris shouldn't be doing this setup here (it
should be in the inferior stage), we'll deal with that later.
For targets that process argv in sim_create_inferior, improve the code:
- provide more details in the comment
- make the check for when to re-init more robust
- clean out legacy sim_copy_argv code
This will be cleaned up more in the future when we have a common inferior
creation function, but at least help new ports get it right until then.
The frv port used the device logic to support a single cache address,
and the comments around that are "these were merely copied from a diff
port and are unused", plus the code to attach the memory is "#if 0".
Just punt it all.
The m32r port was using the device framework to handle two devices: the
cache and uart registers. Both can be implemented in the newer hardware
framework instead which allows us to drop the device logic entirely, as
well as delete the tconfig.h file.
While creating the new uart device model, I also added support for using
stdin to read/write data rather than only supporting sockets.
This has been lightly tested as there doesn't appear to be test coverage
for the code already. If anyone still cares about this port, then they
should (hopefully) file bug reports.
The cris port was using the device framework to handle two addresses when
the --cris-900000xx flag was specified. That can be implemented using the
newer hardware framework instead which allows us to drop the device logic
entirely, as well as delete the tconfig.h file. Basically we create a new
cris_900000xx device model and move the read logic out of devices.c and
into that. The rest of the devices logic was callback to the hardware
framework already.
Much like we autodetect the path to the run program when there is none
set explicitly, do the same for the rvdummy program. Otherwise the
default make check fails to execute the helper properly.
These trace calls don't seem to add anything useful and break the cris
hw tests, so punt them. They were disabled before commit 6d519a4606
but were re-enabled as part of TRACE macro cleanups.
