Commit Graph

4039 Commits

Author SHA1 Message Date
Mike Frysinger
04b4939b03 gdb: riscv: enable sim integration
Now the simulator can be loaded via gdb using "target sim".
2021-02-04 19:15:17 -05:00
Mike Frysinger
b9249c461c sim: riscv: new port
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
2021-02-04 19:02:19 -05:00
Mike Frysinger
6451541244 sim: cgen-trace: tweak printf call
GCC warns that we pass a non-string literal as the format string,
so add an explicit "%s" to make it happy.
2021-01-31 17:31:44 -05:00
Mike Frysinger
bccec180ce sim: bpf: fix mainloop extract call
The extract function takes the argbuf, not the scache.
2021-01-31 17:19:38 -05:00
Mike Frysinger
ba2f0de216 sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name
We renamed these years ago, but it looks like the cgen core missed the
TRACE_EXTRACT function, so these new ports still used the incompatible
common name.  Fix those ports to use the right func.
2021-01-31 17:08:49 -05:00
Stafford Horne
5bc4f5ca15 sim: cgen-accfp: Fix pointer sign warnings
When compiling we get the following warnings:

  common/cgen-accfp.c: In function 'fixsfsi':
  common/cgen-accfp.c:370:18: warning: pointer targets in passing argument 1 of 'sim_fpu_to32i' differ in signedness [-Wpointer-sign]
     sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
                    ^
  common/cgen-accfp.c: In function 'fixdfsi':
  common/cgen-accfp.c:381:18: warning: pointer targets in passing argument 1 of 'sim_fpu_to32i' differ in signedness [-Wpointer-sign]
     sim_fpu_to32i (&res, &op1, sim_fpu_round_near);
                    ^
2021-01-31 15:26:58 -05:00
Mike Frysinger
5f05936d9b sim: v850: cleanup build warnings
This port only had one minor warning left in it, so fix it and then
enable -Werror behavior by deleting the macro call.  We'll use the
common default now (which is -Werror).
2021-01-31 15:19:16 -05:00
Mike Frysinger
44b30b7f0e sim: v850: fix handling of SYS_times
My recent rewrite of the nltvals generator fixed a bug where SYS_times
was not being exported for v850.  But that in turn uncovered this bug
where the SYS_times codepath had a compile error.
2021-01-31 15:15:33 -05:00
Mike Frysinger
3c811346e9 sim: moxie: cleanup build warnings
This port only had one minor warning left in it, so fix it and then
enable -Werror behavior by deleting the macro call.  We'll use the
common default now (which is -Werror).
2021-01-31 12:06:29 -05:00
Mike Frysinger
9a7ba4aa0e sim: common: change gennltvals helper to Python
This tool is only run by developers and not in a release build,
so rewrite it in Python to make it more maintainable.
2021-01-30 20:17:46 -05:00
Mike Frysinger
683b8d961e sim: m68hc11: fix printf size warnings
GCC complains %llu is wrong for signed64, so switch to PRIi64.
2021-01-30 10:40:26 -05:00
Mike Frysinger
b9e016f517 sim: m68hc11: localize a few functions
These are only used in this file and lack prototypes, so gcc
complains about it.  Add static everywhere to clean that up.
2021-01-30 10:28:38 -05:00
Mike Frysinger
fb8d4e59af sim: m68hc11: tweak printf-style funcs
GCC complains that we past non-string literals to a printf style func,
so put a %s in here to keep it quiet.
2021-01-30 10:25:04 -05:00
Mike Frysinger
ee64caae5b sim: m68hc11: include stdlib.h for prototypes
These files use abort() & strtod(), so include stdlib.h for them.
2021-01-30 10:21:15 -05:00
Mike Frysinger
d4e3adda12 sim: watchpoints: change sizeof_pc to sizeof(sim_cia)
Existing ports already have sizeof_pc set to the same size as sim_cia,
so simply make that part of the core code.  We already assume this in
places by way of sim_pc_{get,set}, and this is how it's documented in
the sim-base.h API.

There is code to allow sims to pick different register word sizes from
address sizes, but most ports use the defaults for both (32-bits), and
the few that support multiple register sizes never change the address
size (so address defaults to register).  I can't think of any machine
where the register hardware size would be larger than the address word
size either.  We have ABIs that behave that way (e.g. x32), but the
hardware is still equivalent register sized.
2021-01-30 10:14:21 -05:00
Mike Frysinger
18d4b488f4 sim: profile: fix bucketing with 64-bit targets
When the target's PC is 64-bits, this shift expands into a range of
8 * 8 - 1 which doesn't work with 32-bit constants.  Force it to be
a 64-bit value all the time and let the compiler truncate it.
2021-01-30 01:15:04 -05:00
Mike Frysinger
88f68ee277 sim: m68hc11: stop making hardware conditional
This port doesn't build if these hardware modules are omitted, and
there's no reason we need to make it conditional at build time, so
always enable it.  The hardware devices only get turned on if the
user requests it at runtime via hardware settings.
2021-01-30 01:09:38 -05:00
Mike Frysinger
f4dd74915b sim: hw: replace fgets with getline
This avoids fixed sized buffers on the stack.
2021-01-30 01:07:58 -05:00
Mike Frysinger
481fac96bd sim: common: sort nltvals.def
This was largely already done, but I think people didn't quite notice.
2021-01-30 01:00:07 -05:00
Mike Frysinger
008a02e36d sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Maciej W. Rozycki
c651f0a614 MAINTAINERS: Update my e-mail address
binutils/
	* MAINTAINERS: Update my e-mail address.

	gdb/
	* MAINTAINERS: Update my e-mail address.

	sim/
	* MAINTAINERS: Update my e-mail address.
2021-01-22 00:10:39 +00:00
Mike Frysinger
c65ca138c4 sim: ppc: update version script usage
This matches the changes in the common code.
2021-01-19 10:54:06 -05:00
Mike Frysinger
0e7620dcdc sim: bfin: delete accidental ADI copyright
This wasn't supposed to be in here when it was first merged as we
had specifically disabled it for all the tests (and ADI has papers
in place w/the FSF).  Clean up this one.
2021-01-18 21:30:12 -05:00
Mike Frysinger
f89f33e57c sim: common: simplify version script
We don't use the host & target aliases, so don't bother emitting them.
2021-01-18 12:25:57 -05:00
Mike Frysinger
5e25901fcc sim: common: delete configure & Makefile
This was mostly orphaned a while back, but left behind so people could
still run `make headers`.  Merge that one target to the top sim dir and
delete all the build logic.  This should avoid confusing people further.
2021-01-18 12:23:18 -05:00
Mike Frysinger
4cfcd3b333 sim: common: modernize gennltvals.sh
It's not 1996 anymore, so stop writing shell code like it is, and
rewrite it with modern POSIX shell standards.  This makes it much
more user friendly.

Then regenerate the file with latest newlib sources to verify.
2021-01-18 12:19:19 -05:00
Mike Frysinger
1368b914e9 sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.
2021-01-15 19:18:34 -05:00
Mike Frysinger
bb3eddb5bd sim: testsuite: delete configure script
Now that we've moved all ports to dejagnu & testsuite/sim/, the only
thing the testsuite/configure script has been doing is filling in the
sim_arch field in the testsuite/Makefile.  We can simply let the top
sim/configure script do that for us now.  This simplifies & speeds up
the build a bit by killing an entire configure script.
2021-01-15 01:51:11 -05:00
Mike Frysinger
29fd199ed8 sim: d10v: relocate tests & clean up test harness
This is the only target using a dir directly under testsuite/.  All
others use sim/<arch>/ instead.  Relocate it so all targets look the
same, and so we can leverage the common test harness.

We drop loop.s in the process because it was never referenced and
was just 2 lines of code.

All other test files are moved & have directives added to the top so
that the test harness can invoke them correctly.
2021-01-15 01:49:23 -05:00
Mike Frysinger
137d6efd8a sim: mips: delete empty stub test dir
No tests were ever added in here in the ~22 years since it was first
created.  Seems unlikely any tests will be added at this rate, and
the sim/mips/ testdir already has some (light) coverage for this
target.  So punt the tree.
2021-01-15 01:46:51 -05:00
Mike Frysinger
89bfc2a429 sim: frv: clean up redundant test coverage
The frv-elf subdir contained five tests:
* cache: A cache test of some sort.
* exit47: A program to test exit status of 47 from sim.
* grloop: Some basic limited loop test program.
* hello: Standard "hello world" output program.
* loop: An infinite loop program.

The loop.s test is never referenced anywhere, and is all of 2 lines.
Anyone who really needs a while(1); test case and re-implement it
themselves locally.

The cache.s code isn't referenced anywhere because it requires some
custom args to the run program, and when this testcase was added, we
didn't have any support for that.  We do now, so we can add a header
to enable that.  Turns out the code crashes even with those, so turn
around and mark it xfail.  Maybe someone someday will care.

That leaves the small exit47, grloop, and hello tests.  Now that the
sim test harness supports testing for custom exit status, we can move
them all to sim/frv/ to maintain test coverage.

The remaining differences between frv-elf & sim/frv are:
* frv-elf/ runs for frv-*-elf while sim/frv/ runs for frv*-*-*.
* frv-elf/ runs "*.s" files while sim/frv/ only has .cgs and such.

On closer inspection, these are also meaningless distinctions:
* There is nothing specific to the tests that require an *-elf
  target.  Normally that would mean newlib+libgloss type stuff,
  but there's no such requirement in frv-elf/.
* The ".s" suffix is the standard "this is an assembly file" suffix.
  Since FRV is a CGEN target, we can reuse the existing convention of
  ".ms" to mean "miscellaneous .s" as in "this is an assembly file,
  and run/bucket its test results in the miscellaneous category".

So moving frv-elf/{cache,exit47,grloop,hello}.s to sim/frv/*.ms makes
sense and simplifies things quite a bit for the target while also
slightly increasing the coverage for some tuples.
2021-01-15 01:43:47 -05:00
Mike Frysinger
7cf91a2481 sim: m32r: clean up redundant test coverage
The m32r-elf subdir contained three tests:
* exit47: A program to test exit status of 47 from sim.
* hello: Standard "hello world" output program.
* loop: An infinite loop program.

There's already a sim/m32r/hello.ms test that does exactly the same
thing as m32r-elf/hello.s, so we can delete that.

The loop.s test is never referenced anywhere, and is all of 2 lines.
Anyone who really needs a while(1); test case and re-implement it
themselves locally.

That leaves the single exit47 test.  Now that the sim test harness
supports testing for custom exit status, we can easily move that to
sim/m32r/exit47.ms to maintain test coverage.

The remaining differences between m32r-elf & sim/m32r are:
* m32r-elf/ runs for m32r-*-elf while sim/m32r/ runs for m32r*-*-*.
* m32r-elf/ runs "*.s" files while sim/m32r/ runs "*.ms" files.

On closer inspection, these are also meaningless distinctions:
* There is nothing specific to the tests that require an *-elf
  target.  Normally that would mean newlib+libgloss type stuff,
  but there's no such requirement in m32r-elf/.
* The ".s" suffix is the standard "this is an assembly file"
  suffix.  Turns out ".ms" is just how sim/m32r/ (and a few other
  CGEN based targets) categorize/bucket test cases.  It simply
  means "miscellaneous .s" as in "this is an assembly file, and
  run/bucket its test results in the miscellaneous category".

So moving m32r-elf/exit47.s to sim/m32r/exit47.ms makes sense and
simplifies things quite a bit for the target while also slightly
increasing the coverage for some tuples.
2021-01-15 01:34:57 -05:00
Mike Frysinger
37a9c3a53e sim: testsuite: allow tests to declare expected exit status
Some tests want to verify they can control the exit status, and
allowing any non-zero value would allow tests to silently fail:
if it crashed & exited 1, or forced all non-zero to 1, then we
wouldn't be able to differentiate with a test exiting with a
status like 47.

Extend the test harness to allow tests to declare their expected
exit status that would be defined as a "pass".  This requires a
small tweak to the sim_run API to return the status directly, but
that shouldn't be a big deal as it's only used by sim code.
2021-01-15 01:33:35 -05:00
Mike Frysinger
54780889e9 sim: h8300: drop separate eightbit memory buffer
The h8300 sim has its own implementation for memory handling that I'd
like to replace with the common sim memory code.  However, it's got a
weird bit of code it calls "eightbit mem" that makes this not as easy
as it would otherwise be.  The code has this comment:
/* These define the size of main memory for the simulator.

   Note the size of main memory for the H8/300H is only 256k.  Keeping it
   small makes the simulator run much faster and consume less memory.

   The linker knows about the limited size of the simulator's main memory
   on the H8/300H (via the h8300h.sc linker script).  So if you change
   H8300H_MSIZE, be sure to fix the linker script too.

   Also note that there's a separate "eightbit" area aside from main
   memory.  For simplicity, the simulator assumes any data memory reference
   outside of main memory refers to the eightbit area (in theory, this
   can only happen when simulating H8/300H programs).  We make no attempt
   to catch overlapping addresses, wrapped addresses, etc etc.  */

I've read the H8/300 Programming Manual and the H8/300H Software Manual
and can't find documentation on it.  The closest I can find is the bits
about the exception vectors, but that sounds like a convention where the
first 256 bytes of memory are used for a special purpose.  The sim will
actually allocate a sep memory buffer of 256 bytes and you address it by
accessing anywhere outside of main memory.  e.g. I would expect code to
access it like:
	uint32_t *data = (void *)0;
	data[0] = reset_exception_vector;
not like the sim expects like:
	uint8_t *data = (void *)0x1000000;
	data[0] = ...;

The gcc manual has an "eightbit_data" attribute:
	Use this attribute on the H8/300, H8/300H, and H8S to indicate that
	the specified variable should be placed into the eight-bit data
	section. The compiler generates more efficient code for certain
	operations on data in the eight-bit data area. Note the eight-bit
	data area is limited to 256 bytes of data.

And the gcc code implies that it's accessed via special addressing:
   eightbit_data: This variable lives in the 8-bit data area and can
   be referenced with 8-bit absolute memory addresses.

I'm fairly certain these are referring to the 8-bit addressing modes
that allow access to 0xff00 - 0xffff with only an 8-bit immediate.
They aren't completely separate address spaces which this eightbit
memory buffer occupies.

But the sim doesn't access its eightbit memory based on specific insns,
it does it purely on the addresses requested.

Unfortunately, much of this code was authored by Michael Snyder, so I
can't ask him :(.  I asked Renesas support and they didn't know:
https://renesasrulz.com/the_vault/f/archive-forum/6952/question-about-eightbit-memory

So I've come to the conclusion that this was a little sim-specific hack
done for <some convenience> and has no relation to real hardware.  And
as such, let's drop it until someone notices and can provide a reason
for why we need to support it.
2021-01-13 21:54:00 -05:00
Mike Frysinger
d9b1deff13 sim: watch: add basic default handler that traps
The default watchpoint handler is NULL.  That means any port that
sets the STATE_WATCHPOINTS->pc field will crash if you try to use
the --watch options but don't configure the interrupt handler.  In
the past, you had to setup STATE_WATCHPOINTS->pc if you wanted to
support PC profiling, and while that was fixed a while ago, we have
a lot of ports who still configure it.

We already add a default set of interrupts (just "int") if the port
doesn't define any.  Let's also add a default handler that raises a
SIGTRAP.  When connected to gdb, this is a breakpoint which is what
people would expect.  When running standalone, it'll abort the sim,
but it's unclear whether there's anything better to do there.  This
really is just to make the watchpoint module more usable out of the
box for most ports with very little setup, at least inside of gdb.
2021-01-13 21:53:11 -05:00
Mike Frysinger
c54f3efdc2 sim: watch: fix range expression processing
The code supports a <start>[,<end>] syntax, but the logic for handling
the <end> check was broken: it would detect the first byte was ",", but
then include that in the strtoul call meaning the result is always 0.
Further, it (re)assigned to arg0 when it meant arg1 which means this
code always processed a range expression as 0,0.  Oops.
2021-01-13 05:52:51 -05:00
Mike Frysinger
62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems
My change 1ac72f0659 ("sim: convert to
bfd_endian") subtly broke the watchpoint module on little endian host
systems.  The old code used 0 to mean "whatever the host endian is",
and while that was changed to use BFD_ENDIAN_UNKNOWN, this caller was
missed.  Since its API used an int instead of an enum, the coercion
from 0 to the BFD endian enum was silently missed, and 0 happens to
be BFD_ENDIAN_BIG.

Instead of restoring the old logic by passing in BFD_ENDIAN_UNKNOWN,
we know the right host endian at compile time, so use that directly.
2021-01-13 05:52:51 -05:00
Mike Frysinger
e998918e98 sim: or1k: fix mixing of code & decl warning
Use the correct style of declaring variables at top of scope.
This fixes a few compiler warnings in the process.
2021-01-12 04:15:28 -05:00
Mike Frysinger
5e9e2f41eb sim: or1k: clean up stale build entries
This logic was migrated to the common code long ago so ports don't
need to declare them themselves.
2021-01-12 04:13:13 -05:00
Mike Frysinger
68895f7d7e sim: README-HACKING: clean up stale run references
The run.c interface was deleted long ago and everyone moved to nrun.c
(which is also the default), so no one needs to declare this anymore.
2021-01-12 04:13:11 -05:00
Mike Frysinger
f220ef633c sim: common: use #error properly 2021-01-12 03:51:44 -05:00
Mike Frysinger
f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call
This was merged into the common code a long time ago, so ports
shouldn't be calling this themselves.
2021-01-12 03:36:08 -05:00
Mike Frysinger
254c3783fe sim: tests: get common tests working again
These were written with 32-bit host assumptions baked into it.
Simplify the printf formats to use ll length modifier as it's
in C11 rather than trying to manually break it up into two,
and cleanup some of the casts to stop assuming sizeof(long) is
the same as sizeof(int).

We also have to add a few more includes for the various funcs
used in here.

The tests aren't compiled automatically still.  We can figure
that out later with more work.
2021-01-11 18:30:06 -05:00
Mike Frysinger
9c70334dee sim: always call SIM_AC_OPTION_WARNINGS
Now that all ports have opted in to this, we can require it in the
core.  It guarantees that new ports have them turned on, and defaults
to -Werror in the hopes that new ports keep their code clean from the
start.  We do this as a sep commit to make it clear that there are no
changes to existing ports as they've all explicitly called it already.
2021-01-11 09:18:27 -05:00
Mike Frysinger
5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports
We want all ports to opt into extra warnings as the default compiler
settings lets a lot slide.  Opt all the ports that haven't already in
to the warning system.  None of them build with -Werror, so disable
that by default.  Hopefully someone finds these important enough to
start fixing at some point.
2021-01-11 09:13:11 -05:00
Mike Frysinger
a0c38f0d70 sim: or1k: fix include ordering with sim-main.h
Make sure config.h is included before C library headers otherwise the
later libiberty.h include gets confused about asprintf state leading
to warnings like:
common/sim-utils.c:330:9:
	warning: implicit declaration of function 'vasprintf';
	did you mean 'xvasprintf'? [-Wimplicit-function-declaration]
2021-01-11 08:29:18 -05:00
Mike Frysinger
90e123dd60 sim: common: fix printf formats
For 32-bit targets, %x happens to work for unsigned_word.  But for
64-bit targets, it's too small, and gcc throws an error.  Use the
right printf format define for them.
2021-01-11 08:27:40 -05:00
Mike Frysinger
933306703a sim: rl78: move storage out of header
This port declares its pc variable in a header and then includes
it multiple times.  This causes linker errors with newer gcc due
to the change in -fno-common behavior.  Move the storage to a C
file so we only have one instance of it in the final program.
2021-01-11 08:25:34 -05:00
Mike Frysinger
68ed285428 sim: clean up C11 header includes
Since we require C11 now, we can assume many headers exist, and
clean up all of the conditional includes.  It's not like any of
this code actually accounted for the headers not existing, just
whether we could include them.

The strings.h cleanup is a little nuanced: it isn't in C11, but
every use of it in the codebase will include strings.h only if
string.h doesn't exist.  Since we now assume the C11 string.h
exists, we'll never include strings.h, so we can delete it.
2021-01-11 08:05:54 -05:00
Mike Frysinger
a9fd212a24 sim: replace rindex with strrchr 2021-01-09 09:40:59 -05:00
Mike Frysinger
7eb99e5e27 sim: cr16/d10v: move storage out of header
These ports declare their State variable in a header and then include
multiple times.  This causes linker errors with newer gcc due to the
change in -fno-common behavior.  Move the storage to a C file so we
only have one instance of it in the final program.
2021-01-09 09:39:17 -05:00
Mike Frysinger
f074c07d8d sim: common: clean up asprintf includes a bit
Delete stale prototypes that libiberty.h already provides, and add
missing libiberty.h includes to files that use those functions.
2021-01-09 09:32:34 -05:00
Mike Frysinger
f8cab0b995 sim: sh64: delete port
Support for sh64 was dropped from bfd et al in 2018.  Without
that, the sim port is useless.  So clean up this code too.
2021-01-09 09:29:17 -05:00
Mike Frysinger
50df264dae sim: clean up stale AC_PREREQ refs
This was purged from the tree when we upgraded to autoconf-2.69,
but a few references in the sim tree were missed.
2021-01-09 09:27:29 -05:00
Mike Frysinger
bf470982f9 sim: enable -Werror by default for some arches
We've had this off for a long time because the sim code was way too
full of warnings for it to be feasible.  However, I've cleaned things
up significantly from when this was first merged, and we can start to
turn this around.

Change the macro to enable -Werror by default, and allow ports to opt
out.  New ports will get it automatically (and we can push back on
them if they try to turn it off).

Also turn it off for the few ports that still hit warnings for me.
All the rest will get the new default, and we'll wait for feedback
if/when new issues come up.
2021-01-09 09:19:37 -05:00
Mike Frysinger
f41464416a sim: pru: fix include ordering with sim-main.h
Make sure config.h is included before C library headers otherwise the
later libiberty.h include gets confused about asprintf state leading
to warnings like:
common/sim-utils.c:330:9:
	warning: implicit declaration of function 'vasprintf';
	did you mean 'xvasprintf'? [-Wimplicit-function-declaration]
2021-01-09 08:43:48 -05:00
Mike Frysinger
b5a4a01af4 sim: hw: rework code to avoid gcc warnings
Newer gcc thinks we might return a pointer to a stack buffer, but
we don't -- we strdup it before returning.  Rework the code to just
malloc the buffer from the start and avoid the stack+strdup.
2021-01-09 08:40:07 -05:00
Mike Frysinger
ce0be4070f sim: common: add missing stdlib.h for abort() 2021-01-09 02:45:14 -05:00
Mike Frysinger
46f900c065 sim: require a C11 compiler
With GDB requiring a C++11 compiler now, this hopefully shouldn't
be a big deal.  It's been 10 years since C11 came out, so should
be plenty of time to upgrade.

This will allow us to start cleaning up random header logic and
many of our non-standard custom types.
2021-01-08 15:45:42 -05:00
Mike Frysinger
f4cfa91741 sim: ppc: stub out sim_memory_map
Not clear how to implement this in the ppc-specific sim, so just
stub it out.  This is as good as it was previously.
2021-01-08 01:03:10 -05:00
Mike Frysinger
0f8e278da2 sim: ChangeLog: move arch-specific entries into the arch dir
We don't want arch-specific entries in the common ChangeLog files.
Most arches do this already, so clean up the recent additions, and
move some older entries down to help avoid confusing newcomers.
2021-01-07 12:22:33 -05:00
Mike Frysinger
e6c1dbbfe8 sim: cris: disable test that crashes the linker
PR ld/13900
Linking this test crashes the linker, so disable it.  The crash
was reported about 9 years ago but haven't made progress, so lets
avoid the failures in test runs.
2021-01-07 12:22:14 -05:00
Mike Frysinger
a39487c668 sim: cris: use -sim with C tests for cris-elf targets
Building the C tests with a cris-elf toolchain (gcc-10.2 &
newlib-4.1.0) currently fail due to warnings it emits:
cris-elf-ld: libc.a(lib_a-closer.o): in function `_close_r':
newlib/libc/reent/closer.c:47: warning: _close is not implemented and will always fail

This is because the default target for cris-elf is bare metal, not
the simulator.  For that, we need -sim.  So add it for elf targets.

We don't add it for all targets as the simulator (and testsuite)
run both libgloss programs as well as Linux userspace programs.
2021-01-07 12:21:48 -05:00
Mike Frysinger
bfc7d04afb sim: h8300: delete opcode caching
This is in preparation for converting h8300 over to the common memory
framework.  It's not clear how much of a speed gain this was providing
in the first place -- a naive test of ~400k insns (using shlr.s) shows
that this code actually slowed things down a bit.

If anyone really cares about h8300 anymore, they can migrate to the
common insn caching logic.
2021-01-07 12:21:12 -05:00
Mike Frysinger
e904f56d02 gdb/sim: add support for exporting memory map
This allows gdb to quickly dump & process the memory map that the sim
knows about.  This isn't fully accurate, but is largely limited by the
gdb memory map format.  While the sim supports RWX bits, gdb can only
handle RW or RO regions.
2021-01-07 12:18:59 -05:00
Mike Frysinger
9446bcf6be fix paths in ChangeLog 2021-01-07 01:27:06 -05:00
Mike Frysinger
1861f7cfbf sim: cris: fix C tests with newer toolchains
Make sure we include unistd.h for getpid prototypes to fix build
warnings/errors with newer compilers & C libraries.

Doing that for close in openpf highlights these were using the
wrong function -- need to use fclose on FILE*, not close.

These tests pass again with a cris-elf toolchain.
2021-01-07 01:19:49 -05:00
Mike Frysinger
865288236d sim: fr30: delete unused testsuite
Looking through the history, it doesn't seem like the fr30 port was
ever merged.  There used to be a testsuite/fr30-elf/ dir, but that
was punted back in 2005 as being dead too.  Since there's no refs
and the dir hasn't been touched since 1999, lets assume no one will
ever notice or care.
2021-01-05 19:29:46 -05:00
Mike Frysinger
c004e77f7d sim: testsuite: delete unused Make-common.in file
This seems like it was meant to unify arch test Makefiles, but
that never happened, and we've instead unified using dejagnu.
2021-01-05 19:29:11 -05:00
Mike Frysinger
a2f8e947a8 sim: h8300: fix test mach markers
These tests all fail to assemble when targeting the h8300 or h8300h
cpu variants with errors like:
rotl.s:242: Warning: Opcode `rotl.b' with these operand types not available in H8/300H mode
rotl.s:242: Error: invalid operands

It's been this way for years and no one seems to care, so disable
them for those targets since the assembler thinks it's impossible.
2021-01-05 19:26:33 -05:00
Mike Frysinger
0c7f5bd08c sim: h8300: simplify testsuite runner
We don't need to manually enumerate every test.  Use a glob function
like every other port and rely on the (already existing) #mach headers
in each file to filter out targets we don't care about.
2021-01-05 19:26:17 -05:00
Mike Frysinger
3d52735bab sim: include stdlib.h for atoi()
Make sure the files using atoi() include stdlib.h for its prototype.
These files were relying on it being included implicitly by others
which isn't guaranteed, and newer toolchains produce warnings.
2021-01-04 20:17:37 -05:00
Mike Frysinger
9416af6e7d sim: stdlib.h for abs()
Make sure the files using abs() include stdlib.h for its prototype.
These files were relying on it being included implicitly by others
which isn't guaranteed, and newer toolchains produce warnings.
2021-01-04 20:13:10 -05:00
Mike Frysinger
dfb856ba26 sim: update bug URI to https:// 2021-01-04 18:14:37 -05:00
Mike Frysinger
babd2ee15d sim: common: version: add build & homepage info when interactive
This mirrors gdb behavior of dumping extra info when being run in
interactive mode.  It also gives us an excuse to use the otherwise
unused sim_print_config.
2021-01-04 18:10:40 -05:00
Mike Frysinger
2b667e3297 sim: common: use sim_config_print name
Meant to push this variant where naming preference is given to the
module the code resides in rather than the operation it performs.
2021-01-04 18:10:40 -05:00
Mike Frysinger
19b1c38562 sim: common: add a version output helper w/copyright+license info
This mirrors the existing sim_print_help function, and the behavior
of all other GNU tools with their --version.
2021-01-04 17:41:23 -05:00
Mike Frysinger
dbed468bcb sim: common: rename sim_print_config
print_sim_config has never been used anywhere, so rename it to follow
the sim_* naming style for all other symbols we export.
2021-01-04 17:35:20 -05:00
Mike Frysinger
0ede24f2c4 sim: common: add align_{up,down} to match gdb
We have ALIGN_{8,16,PAGE} and FLOOR_PAGE macros (where PAGE is defined as
4k) which were imported from the ppc sim.  But no other sim utilizes these
and hardcoding the sizes in the name is a bit limiting.

Let's delete these and import the two general macros that gdb uses:
	align_up(addr, bytes)
	align_down(addr, bytes)

This in turn allows us to cut over the Blackfin code immediately.
2021-01-02 20:55:21 -05:00
Joel Brobecker
3666a04883 Update copyright year range in all GDB files
This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...

gdb/ChangeLog

        Update copyright year range in copyright header of all GDB files.
2021-01-01 12:12:21 +04:00
Pavel I. Kryukov
382bc56bc7 sim/mips/sim-main.c: Include <stdlib.h> (for abort() declaration)
sim/mips/ChangeLog:

	* sim-main.c: Include <stdlib.h>.
2020-12-31 08:14:36 +04:00
Jens Bauer
9f132af9e1 Add support for the SDIV and UDIV instructions to the ARM simulator.
* armemu.c (handle_v6_insn): Add support for SDIV and UDIV.
	* thumbemu.c (handle_T2_insn): Likewise.
2020-12-15 12:40:35 +00:00
Pavel I. Kryukov
ad9675dd80 sim/mips/cp1.c: Include <stdlib.h> for abort() declaration
sim/mips/ChangeLog:

	* cp1.c: Include <stdlib.h>
2020-12-14 07:02:05 +04:00
Dimitar Dimitrov
e57cf1f2cd sim: pru: Add support for LMBD instruction
Binutils support for LMBD instruction was merged [1]. So add it also
to simulator.

LMBD instruction does left-most-bit-detection. It returns 32 if
the given bit value is not found in the provided word value.

[1] https://sourceware.org/pipermail/binutils/2020-October/113901.html

sim/pru/ChangeLog:

	* pru.h (RS1SEL): New macro.
	(RS1_WIDTH): New macro.
	* pru.isa: Describe the LMBD instruction.

sim/testsuite/sim/pru/ChangeLog:

	* lmbd.s: New test.
2020-11-12 22:41:10 +02:00
Nick Clifton
94cde56ab3 m32r sim: Add prototypes for functions that pass/return DI values
* m32r-sim.h (m32rbf_h_accum_get_handler): Always provide a
	prototype for this function.
	(m32rbf_h_accum_set_handler): Likewise.
	(m32r2f_h_accums_get_handler): Prototype.
	(m32r2f_h_accums_set_handler): Prototype.
2020-11-12 12:22:18 +00:00
Simon Marchi
8807d3127c sim/bpf: re-generate configure
I noticed a little diff when re-generating the configure file in this
directory.

sim/ChangeLog:

	* bpf/configure: Re-generate.

Change-Id: Ieb26be2cc1be8108d4b08387255f45b57f288171
2020-11-01 19:39:11 -05:00
Andrew Burgess
63aa0ac0fd sim: move ChangeLog entries into the correct files
Moves some ChangeLog entries under sim/ into the correct files.
2020-10-22 13:39:26 +01:00
Dr. David Alan Gilbert
777cd7ab3f Fix printf formatting errors where "0x" is used as a prefix for a decimal number.
bfd	* po/es.po: Fix printf format

binutils * windmc.c: Fix printf format

gas	* config/tc-arc.c: Fix printf format

opcodes	* po/es.po: Fix printf format

sim	* arm/armos.c: Fix printf format
	* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
2020-10-22 12:00:10 +01:00
Andrew Burgess
043f5c63f0 sim: Fix autoreconf errors in sim/ directory
Run autoreconf in sim/ directory and you'll see some errors.  The
problem is that autoreconf (a perl script) does not evaluate the value
passed as an argument to AC_CONFIG_AUX_DIR, so something like:

  AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../..)

does not do the right thing inside autoreconf, my understanding is
that changing to something like this is fine:

  AC_CONFIG_AUX_DIR(../..)

the generated configure seems to check the value passed, and the value
passed relative to the source directory, so I think we get basically
the same behaviour as before.

sim/testsuite/ChangeLog:

	* configure: Regnerate.
	* configure.ac (AC_CONFIG_AUX_DIR): Update.

sim/testsuite/d10v-elf/ChangeLog:

	* configure: Regnerate.
	* configure.ac (AC_CONFIG_AUX_DIR): Update.

sim/testsuite/frv-elf/ChangeLog:

	* configure: Regnerate.
	* configure.ac (AC_CONFIG_AUX_DIR): Update.

sim/testsuite/m32r-elf/ChangeLog:

	* configure: Regnerate.
	* configure.ac (AC_CONFIG_AUX_DIR): Update.

sim/testsuite/mips64el-elf/ChangeLog:

	* configure: Regnerate.
	* configure.ac (AC_CONFIG_AUX_DIR): Update.
2020-10-06 11:29:44 +01:00
Andrew Burgess
e163628395 sim/m32r: return register sizes after fetch and store
The m32r simulator currently always returns -1 for the register size
after both a fetch and a store.  In the fetch case GDB is forgiving of
this, but in the store case GDB treats a return value of -1 as an
error.

This commit updates the m32r simulator to return a valid register size
when fetching or storing a register.  This fixes any GDB test that
writes to a register, which will include any GDB test that makes an
inferior call, for example gdb.base/break.exp.

sim/m32r/ChangeLog:

	* m32r.c (m32rbf_register_size): New function.
	(m32rbf_fetch_register): Use new function.
	(m32rbf_store_register): Likewise.
2020-09-18 17:26:07 +01:00
David Faust
3ad6c19423 bpf: simulator: correct div, mod insn semantics
The div and mod eBPF instructions are unsigned, but the semantic
specification for the simulator incorrectly used signed operators.
Correct them to unsigned versions, and correct the ALU tests in
the simulator (which incorrectly assumed signed semantics).

Tested in bpf-unknown-none.

cpu/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf.cpu (define-alu-instructions): Correct semantic operators
	for div, mod to unsigned versions.

sim/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* bpf/sem-be.c: Regenerate.
	* bpf/sem-le.c: Likewise.

sim/testsuite/ChangeLog:
2020-09-08  David Faust  <david.faust@oracle.com>

	* sim/bpf/alu.s: Correct div and mod tests.
	* sim/bpf/alu32.s: Likewise.
2020-09-08 11:39:07 -07:00
Jose E. Marchesi
0316fb52d6 bpf: several small fixes in the simulator
This patch fixes the following problems:
- Missing includes in several files leading to implicit function
  declarations.
- Missing prototype for bpf_trace_printk in bpf-helpers.h
- The simulator bitsize was set to 32 bits, causing truncation of
  the program counter.

Tested in bpf-unknown-none.

sim/ChangeLog:

2020-09-03  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf/bpf.c: Include bpf-helpers.h.
	* bpf/bpf-helpers.h: Provide a prototype for bpf_trace_printk.
	* bpf/configure.ac: Set simulator bitsize to 64.
	* bpf/configure (includedir): Regenerate.
	* bpf/sim-if.c: Include stdlib.h.
	* bpf/traps.c: Likewise.
2020-09-03 18:22:08 +02:00
Jose E. Marchesi
1d01693f55 sim: better handle builds of primary targets lacking sims
When building with a primary target that doesn't feature a simulator,
one would expect for nothing to be done in sim/.  However, a
$(top_builddir)/sim/testsuite directory is created, with a Makefile
containing a rule like:

check-DEJAGNU: site.exp
	echo "Dejagnu-checking in `pwd` directory ..."
	rootme=`pwd`; export rootme; echo rootme = $$rootme; \
	srcdir=`cd ${srcdir}; pwd`; export srcdir ; echo srcdir = $$srcdir; \
	EXPECT=${EXPECT} ; export EXPECT ; echo EXPECT = $$EXPECT; \
	if [ -f $$rootme/../../expect/expect ]; then \
	  TCL_LIBRARY=`cd $$srcdir/../../tcl/library && pwd`; \
	  export TCL_LIBRARY; \
	fi; \
        echo TCL_LIBRARY = $$TCL_LIBRARY; \
	runtest=$(RUNTEST); echo runtest = $$runtest; \
	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
	  $$runtest $(RUNTESTFLAGS); \
	else echo "WARNING: could not find \`runtest'" 1>&2; :;\
	fi

Consequently, when `make check' recurses into sim/testsuite, the above
rule is executed.  Until now, the desired effect (of doing nothing)
was achieved because `runtest --version' fails due to a malformed
site.exp being generated in objdir: it is malformed because the
primary target doesn't configure a $sim_arch. i.e. this was doing the
right thing just by chance.

However, the git version of dejagnu seems to have changed in a way
runtest doesn't try to load site.exp when it gets --version.  The net
effect is that the rule above tries to actually run the tests, failing
miserably.

This little patch makes sim/configure to not recurse into
sim/testsuite if the primary target didn't configure a simulator.

Tested with:
- A simulator target (bpf-unkonwn-none).
- A simulator-less target (x86_64-linux-gnu).
- A simulator-less target and --build-targets=all.

sim/ChangeLog:

2020-09-03  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* configure.ac: Do not configure sim/testsuite nor sim/igen if the
	primary target doesn't have a simulator.
	* configure: Regenerate.
2020-09-03 18:21:20 +02:00
Simon Marchi
5798d69f03 sim/bfin: include config/pkg.m4 in configure.ac
When trying to re-generate configure in sim/bfin, I get:

    $ autoreconf -vf
    autoreconf: Entering directory `.'
    autoreconf: configure.ac: not using Gettext
    autoreconf: running: aclocal --force
    autoreconf: configure.ac: tracing
    autoreconf: configure.ac: not running libtoolize: --install not given
    autoreconf: running: /opt/autostuff/bin/autoconf --force
    configure.ac:57: error: possibly undefined macro: AC_CHECK_LIB
          If this token and others are legitimate, please use m4_pattern_allow.
          See the Autoconf documentation.
    autoreconf: /opt/autostuff/bin/autoconf failed with exit status: 1

This happens since commit f693213d12 ("Run `autoreconf -vf` throughout").

The problem (not clear from the error message) is that the
PKG_CHECK_MODULES macro used in configure.ac is undefined.  In the past, I
suppose that it relied on the person running autoconf having pkg.m4 (from
pkg-config) in their include path.  That's not my case.

Since we recently added a local version of PKG_CHECK_MODULES to our tree,
we can just make sim/bfin/configure.ac use it.  This patch makes
configure.ac include config/pkg.m4, and re-generates configure.  With this,
the configure script appears to be generated correctly, I am able to
configure and build the bfin simulator.

Note: using sinclude to include the required m4 files makes no sense to
me.  These files contain macros we need, if they are not defined then
the resulting file is unusable.  And sinclude fails silently if the file
is not found.  So, better use include/m4_include.

sim/bfin/ChangeLog:

	* configure.ac: Include config/pkg.m4.

Change-Id: I7d8012e5ed510cd7746b94e918f0feb1c701cd83
2020-08-21 11:55:08 -04:00
Luis Machado
a5353ae6cf [ARM, sim] Fix build failure with -Werror (PR26365)
There is a bit of a situation in the ARM sim with regards to the handling
of argv. sim_open () gets a const char **argv, but ARM's sim_open gets
clever and decides to modify argv in place via sim_target_parse_command_line.
I'm not sure why.

In any case, here's a fix that makes the code modify a copy of argv instead.

sim/arm/ChangeLog:

2020-08-13  Luis Machado  <luis.machado@linaro.org>

	PR sim/26365

	* wrapper.c (sim_target_parse_command_line): Free discarded argv
	entries.
	(sim_open): Use a duplicate of argv instead of the original argv.
2020-08-13 10:32:52 -03:00
Tom de Vries
b3f8962bdb [sim] Fix mbuild build breaker in sim-cpu.c
When running gdb/gdb_mbuild.sh, I run into:
...
src/sim/aarch64/../common/sim-cpu.c: In function 'sim_cpu_free':
src/sim/aarch64/../common/sim-cpu.c:64:3: error: implicit declaration of \
  function 'free' [-Werror=implicit-function-declaration]
   free (cpu);
   ^~~~
src/sim/aarch64/../common/sim-cpu.c:64:3: error: incompatible implicit \
  declaration of built-in function 'free' [-Werror]
src/sim/aarch64/../common/sim-cpu.c:64:3: note: include '<stdlib.h>' or \
  provide a declaration of 'free'
...

Fix this by adding "#include <stdlib.h>".

Tested by gdb/gdb_mbuild.sh -e aarch64-elf.

sim/common/ChangeLog:

2020-08-10  Tom de Vries  <tdevries@suse.de>

	* sim-cpu.c: Include stdlib.h for free.
2020-08-10 17:26:09 +02:00
Jozef Lawrynowicz
4b48e6d46d MSP430: sim: Increase main memory region size
The area between 0xFF00 and 0xFFC0 is unallocated in the simulator
memory map, so extend the main memory region up to 0xFFC0 to allow the
simulator to make use of the extra 192 bytes of space.

sim/msp430/ChangeLog:

	* msp430-sim.c (sim_open): Increase the size of the main memory region
	to 0xFAC0.
2020-08-07 11:01:22 +01:00
Jozef Lawrynowicz
e8a387fb5f MSP430: sim: Fix incorrect simulation of unsigned widening multiply
Operand sizes used for simulation of MSP430 hardware multiply
operations are not aligned with the sizes used on the target, resulting
in the simulator storing signed operands with too much precision.

Additionally, simulation of unsigned multiplication is missing explicit
casts to prevent any implicit sign extension.

gcc.c-torture/execute/pr91450-1.c uses unsigned widening multiplication
of 32-bit operands -4 and 2, to produce a 64-bit result:
0xffff fffc * 0x2 = 0x1 ffff fff8

If -4 is stored in 64-bit precision, then the multiplication is
essentially signed and the result is -8 in 64-bit precision
(0xffff ffff ffff fffc), which is not correct.

sim/msp430/ChangeLog:

	* msp430-sim.c (put_op): For unsigned multiplication, explicitly cast
	operands to the unsigned type before multiplying.
	* msp430-sim.h (struct msp430_cpu_state): Fix types used to store hwmult
	operands.

sim/testsuite/sim/msp430/ChangeLog:

	* mpyull_hwmult.s: New test.
2020-08-05 15:02:30 +01:00
Jose E. Marchesi
8c4c18181e sim: generated files for the eBPF simulator
This patch adds the CGEN generated files for the eBPF simulator.

sim/ChangeLog:

2020-08-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf/arch.c: Likewise.
	* bpf/arch.h: Likewise.
	* bpf/cpu.c: Likewise.
	* bpf/cpu.h: Likewise.
	* bpf/cpuall.h: Likewise.
	* bpf/decode-be.c: Likewise.
	* bpf/decode-be.h: Likewise.
	* bpf/decode-le.c: Likewise.
	* bpf/decode-le.h: Likewise.
	* bpf/defs-be.h: Likewise.
	* bpf/defs-le.h: Likewise.
	* bpf/sem-be.c: Likewise.
	* bpf/sem-le.c: Likewise.
2020-08-04 18:11:31 +02:00
Jose E. Marchesi
b26e2ae7d3 sim: eBPF simulator
This patch introduces the basics of an instruction-simulator for eBPF.
The simulator is based on CGEN.

gdb/ChangeLog:

2020-08-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* configure.tgt: Set gdb_sim for bpf-*-* targets.

sim/ChangeLog:

2020-08-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* configure.tgt (sim_arch): Add entry for bpf-*-*.
	* configure: Regenerate.
	* MAINTAINERS: Add maintainer for the BPF simulator.
	* bpf/Makefile.in: New file.
	* bpf/bpf-helpers.c: Likewise.
	* bpf/bpf-helpers.def: Likewise.
	* bpf/bpf-helpers.h: Likewise.
	* bpf/bpf-sim.h: Likewise.
	* bpf/bpf.c: Likewise.
	* bpf/config.in: Likewise.
	* bpf/configure.ac: Likewise.
	* bpf/decode.h: Likewise.
	* bpf/eng.h: Likewise.
	* bpf/mloop.in: Likewise.
	* bpf/sim-if.c: Likewise.
	* bpf/sim-main.h: Likewise.
	* bpf/traps.c: Likewise.
	* bpf/configure: Generate.
	* bpf/aclocal.m4: Likewise.

sim/testsuite/ChangeLog:

2020-08-04  David Faust  <david.faust@oracle.com>
	    Jose E. Marchesi  <jose.marchesi@oracle.com>

	* configure: Regenerate.
	* sim/bpf/allinsn.exp: New file.
	* sim/bpf/alu.s: Likewise.
	* sim/bpf/alu32.s: Likewise.
	* sim/bpf/endbe.s: Likewise.
	* sim/bpf/endle.s: Likewise.
	* sim/bpf/jmp.s: Likewise.
	* sim/bpf/jmp32.s: Likewise.
	* sim/bpf/ldabs.s: Likewise.
	* sim/bpf/mem.s: Likewise.
	* sim/bpf/mov.s: Likewise.
	* sim/bpf/testutils.inc: Likewise.
	* sim/bpf/xadd.s: Likewise.
2020-08-04 18:09:16 +02:00