The earlier commit:
commit 6576bffe6c
Date: Thu Jul 7 13:43:45 2022 +0100
opcodes/arm: add disassembler styling for arm
was causing a compiler warning about a possible uninitialized variable
usage within opcodes/arm-dis.c.
The problem is in print_mve_unpredictable, and relates to the reason
variable, which is set by a switch table.
Currently the switch table does cover every valid value, though there
is no default case. The variable switched on is passed in as an
argument to the print_mve_unpredictable function.
Looking at how print_mve_unpredictable is used, there is only one use,
the second argument is the one that is used for the switch table,
looking at how this argument is set, I don't believe it is possible
for this argument to take an invalid value.
So, I think the compiler warning is a false positive. As such, my
proposed solution is to initialize the reason variable to the string
"??", this will silence the warning, and the "??" string should never
end up being printed.
This commit adds disassembler styling for the ARM architecture.
The ARM disassembler is driven by several instruction tables,
e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc
The type for elements in each table can vary, but they all have one
thing in common, a 'const char *assembler' field. This field
contains a string that describes the assembler syntax of the
instruction.
Embedded within that assembler syntax are various escape characters,
prefixed with a '%'. Here's an example of a very simple instruction
from the arm_opcodes table:
"pld\t%a"
The '%a' indicates a particular type of operand, the function
print_insn_arm processes the arm_opcodes table, and includes a switch
statement that handles the '%a' operand, and takes care of printing
the correct value for that instruction operand.
It is worth noting that there are many print_* functions, each
function handles a single *_opcodes table, and includes its own switch
statement for operand handling. As a result, every *_opcodes table
uses a different mapping for the operand escape sequences. This means
that '%a' might print an address for one *_opcodes table, but in a
different *_opcodes table '%a' might print a register operand.
Notice as well that in our example above, the instruction mnemonic
'pld' is embedded within the assembler string. Some instructions also
include comments within the assembler string, for example, also from
the arm_opcodes table:
"nop\t\t\t@ (mov r0, r0)"
here, everything after the '@' is a comment that is displayed at the
end of the instruction disassembly.
The next complexity is that the meaning of some escape sequences is
not necessarily fixed. Consider these two examples from arm_opcodes:
"ldrex%c\tr%12-15d, [%16-19R]"
"setpan\t#%9-9d"
Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in
the first instruction, and '%9-9d' in the second instruction, but,
both of these are the '%d' escape.
However, in the first instruction, the '%d' is used to print a
register number, notice the 'r' immediately before the '%d'. In the
second instruction the '%d' is used to print an immediate, notice the
'#' just before the '%d'.
We have two problems here, first, the '%d' needs to know if it should
use register style or immediate style, and secondly, the 'r' and '#'
characters also need to be styled appropriately.
The final thing we must consider is that some escape codes result in
more than just a single operand being printed, for example, the '%q'
operand as used in arm_opcodes ends up calling arm_decode_shift, which
can print a register name, a shift type, and a shift amount, this
could end up using register, sub-mnemonic, and immediate styles, as
well as the text style for things like ',' between the different
parts.
I propose a three layer approach to adding styling:
(1) Basic state machine:
When we start printing an instruction we should maintain the idea
of a 'base_style'. Every character from the assembler string will
be printed using the base_style.
The base_style will start as mnemonic, as each instruction starts
with an instruction mnemonic. When we encounter the first '\t'
character, the base_style will change to text. When we encounter
the first '@' the base_style will change to comment_start.
This simple state machine ensures that for simple instructions the
basic parts, except for the operands themselves, will be printed in
the correct style.
(2) Simple operand styling:
For operands that only have a single meaning, or which expand to
multiple parts, all of which have a consistent meaning, then I
will simply update the operand printing code to print the operand
with the correct style. This will cover a large number of the
operands, and is the most consistent with how styling has been
added to previous architectures.
(3) New styling syntax in assembler strings:
For cases like the '%d' that I describe above, I propose adding a
new extension to the assembler syntax. This extension will allow
me to temporarily change the base_style. Operands like '%d', will
then print using the base_style rather than using a fixed style.
Here are the two examples from above that use '%d', updated with
the new syntax extension:
"ldrex%c\t%{R:r%12-15d%}, [%16-19R]"
"setpan\t%{I:#%9-9d%}"
The syntax has the general form '%{X:....%}' where the 'X'
character changes to indicate a different style. In the first
instruction I use '%{R:...%}' to change base_style to the register
style, and in the second '%{I:...%}' changes base_style to
immediate style.
Notice that the 'r' and '#' characters are included within the new
style group, this ensures that these characters are printed with
the correct style rather than as text.
The function decode_base_style maps from character to style. I've
included a character for each style for completeness, though only
a small number of styles are currently used.
I have updated arm-dis.c to the above scheme, and checked all of the
tests in gas/testsuite/gas/arm/, and the styling looks reasonable.
There are no regressions on the ARM gas/binutils/ld tests that I can
see, so I don't believe I've changed the output layout at all. There
were two binutils tests for which I needed to force the disassembler
styling off.
I can't guarantee that I've not missed some untested corners of the
disassembler, or that I might have just missed some incorrectly styled
output when reviewing the test results, but I don't believe I've
introduced any changes that could break the disassembler - the worst
should be some aspect is not styled correctly.
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
Earlier tidying still missed an opportunity: There's no need for the
"anyimm" static variable. Instead of using it in the loop to mask
"allowed" (which is necessary to satisfy operand_type_or()'s assertions)
simply use "mask", requiring it to be calculated first. That way the
post-loop masking by "mask" ahead of the operand_type_all_zero() can be
dropped.
RISC-V Psabi pr196,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196
bfd/
* elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed.
(riscv_copy_subset_list): Copy arch_str as well.
* elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list.
gas/
* config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the
architecture string in the subset_list.
(riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new
architecture string.
(s_riscv_option): Likewise.
(need_arch_map_symbol): New boolean, used to indicate if .option
directives do affect instructions.
(make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to
generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data
if reset_seg_arch_str is true.
(riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For
now, only add $x+arch if the architecture strings in subset list and segment
are different. Besides, always add $x+arch at the start of section, and do
not add $x+arch for code alignment, since rvc for alignment can be judged
from addend of R_RISCV_ALIGN.
(riscv_remove_mapping_symbol): If current and previous mapping symbol have
same value, then remove the current $x only if the previous is $x+arch;
Otherwise, always remove previous.
(riscv_add_odd_padding_symbol): Updated.
(riscv_check_mapping_symbols): Don't need to add any $x+arch if
need_arch_map_symbol is false, so changed them to $x.
(riscv_frag_align_code): Updated since riscv_mapping_state is changed.
(riscv_init_frag): Likewise.
(s_riscv_insn): Likewise.
(riscv_elf_final_processing): Call riscv_release_subset_list to release
subset_list of riscv_rps_as, rather than only release arch_str in the
riscv_write_out_attrs.
(riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str
from subset_list of riscv_rps_as.
* config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping
symbol of each segment.
* testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s.
* testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in
one file.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping-dis.d: Likewise.
* testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that
does need any $x+arch.
* testsuite/gas/riscv/mapping-non-arch.d: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Updated.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to
riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled
for some specfic code region.
(riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset
the architecture string once the ISA is different.
When no AVX512-specific functionality is in use, the disassembly of
AVX512VL insns is indistinguishable from their AVX counterparts (if such
exist). Emit the {evex} pseudo-prefix in such cases.
Where applicable drop stray uses of PREFIX_OPCODE from table entries.
By putting the templates after their AVX512 counterparts, the AVX512
flavors will be picked by default. That way the need to always use {vex}
ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as
a whole) have been disabled. This way the need for the PseudoVexPrefix
attribute also disappears.
AMX-TILE is a prereq to these, as already correctly expressed by
CPU_ANY_AMX_TILE_FLAGS. Express the dependency also in the reverse
("positive") direction.
Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64,
see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-.
This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions.
The existing behaviour of not requiring the specifier is preserved.
And the disasembly is with the specifier with this patch.
The GAS tests passed under our local tests.
opcodes/
* aarch64-asm.c: Modify `sve_size_hsd` encoding.
* aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD
for decp, incp, sqdecp, sqincp, uqdecp and uqincp.
gas/
* testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's
test_sametwo macro, where take the predicate size specifier.
* testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's
expected disassembly.
* testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's
expected assembler messages.
* testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for
decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the
predicate size specifier.
* testsuite/gas/aarch64/sve.d: Update sve testcase's expected
disassembly.
Signed-off-by: CaiJingtao <caijingtao@huawei.com>
Current F_STRICT qualifier checking is enforced after the fact
rather than as part of the match. This makes it impossible to
have, e.g.:
QLF2(S_D, S_D)
QLF2(S_D, NIL)
in the same list.
opcodes/
* aarch64-opc.c (aarch64_find_best_match): Handle F_STRICT here
rather than...
(match_operands_qualifier): ...here.
These require EVEX.W=0. Use %XS to facilitate the checking, even if for
the AVX512_4VNNIW ones this is kind of an abuse (as 's' there stands for
"signed", not "single").
While there also correct the 3rd operand for the AVX512_4VNNIW entries:
Only the memory form is allowed (just like for AVX512_4FMAPS, where the
correct type is already in use).
Make %XV also print the separating blank in the VEX case, while making
it do nothing for EVEX-encoded insns. This way the AVX-VNNI entries
can be re-used for AVX512-VNNI, at the same time fixing the lack of
EVEX.W decoding.
For the AVX-VNNI ones further make sure only VEX.66 forms are actually
decoded.
I noticed recently that se_rfmci, a VLE mode instruction, was being
accepted by non-VLE cpus, and also that se_rfmci by itself in a
section did not cause SHF_PPC_VLE to be set. ie. both testcases added
by this patch fail without the changes to tc-ppc.c here.
Also, VLE, SPE2 and LSP insns were not accepted by the assembler with
-many nor were SPE2 and LSP being disassembled with -Many.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add
vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify
disassembler index segment checks. Add LSP and SPE2 opcodes
when PPC_OPCODE_ANY too.
(md_assemble): Correct logic adding PPC_APUINFO_VLE and
SHF_PPC_VLE.
* testsuite/gas/ppc/se_rfmci.s
* testsuite/gas/ppc/se_rfmci.d,
* testsuite/gas/ppc/se_rfmci_bad.d: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
opcodes/
* ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn
when -Many.
* ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
Where sub and subf forms of an instruction exist we generally
disassemble to the extended insn sub form rather than the underlying
machine subf instruction. Do so for SPE evsubw and evsubiw too.
spe_ambiguous.d always was a bit too optimistic. There is no sensible
way to disassemble identical bytes back to different and original
source. Instead change the test to check -Mraw results.
gas/
* testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test.
* testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than
evsubfw and evsubifw.
* testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent
to evnot.
* testsuite/gas/ppc/spe_ambiguous.d: Test Mraw.
opcodes/
* ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and
evsubiw before evsubifw and mark EXT.
It has bothered me for a long time that we have disabled LSP (and SPE)
tests. Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect. I don't think there is. Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.
Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425. As far as
I can tell, LSP and SPE are mutually exclusive. This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding. So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work. I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.
Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle. (Yes, I know, as I said above some of the e200z4 processors
have LSP. Others have SPE. It's hard to choose good options. Think
of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow
adding the LSP insn set.
include/
* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
(LSP_OP_TO_SEG): Define.
binutils/
* doc/binutils.texi: Update ppc docs.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
* doc/c-ppc.texi: Document e200 and lsp.
* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
* ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set
PPC_OPCODE_LSP for e200z4 or vle.
(ppc_parse_cpu): Mutually exclude LSP and SPE.
(LSP_OPCD_SEGS): Define.
(lsp_opcd_indices): New array.
(disassemble_init_powerpc): Init lsp_opcd_indices.
(lookup_lsp): New function.
(print_insn_powerpc): Call it.
* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
(vle_opcodes): Move LSP opcodes to..
(lsp_opcodes): ..here, and sort.
(lsp_num_opcodes): New.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit removes unused variable last_map_state (set by the
print_insn_riscv function but not read anywhere else).
opcodes/ChangeLog:
* riscv-dis.c (last_map_state): Remove.
(print_insn_riscv): Remove setting last_map_state.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
Since xlen variable is not (and should not) used outside riscv-dis.c,
this commit makes this variable static.
opcodes/ChangeLog:
* riscv-dis.c (xlen): Make this variable static.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit replaces uses of int with bool whenever possible.
opcodes/ChangeLog:
* riscv-dis.c (no_aliases) Change type to bool.
(set_default_riscv_dis_options): Use boolean.
(parse_riscv_dis_option_without_args): Likewise.
(riscv_disassemble_insn): Use boolean keywords.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
This commit takes care of improper spacing for code clarity.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
Before changing the core disassembler, we take care of minor code clarity
issues and improve readability.
First, we need to clarify the roles of variables and code portions.
opcodes/ChangeLog:
* riscv-dis.c (xlen): Move before default_isa_spec. Add comment.
(default_isa_spec, default_priv_spec): Add comment.
(riscv_gpr_names, riscv_fpr_names): Likewise.
(parse_riscv_dis_option_without_args): Likewise.
(parse_riscv_dis_option, parse_riscv_dis_options): Likewise.
(maybe_print_address): Likewise.
(riscv_disassemble_insn): Fix comment about the Zfinx "extension".
Add comment about the riscv_multi_subset_supports call.
Because all standard hints must be placed before corresponding instruction
for the disassembler, they may taint basic RVI instruction section.
This commit moves all standard hints before all basic RVI instructions
to improve maintainability.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Move all standard hints before all
standard instructions.
This is a part of small tidying (declare tables in riscv-opc.c).
include/ChangeLog:
* opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to
opcodes/riscv-opc.c. New non-static definitions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_rm, riscv_pred_succ): Move from
include/opcode/riscv.h. Add description.
The operand type "Xl(...)" denotes that (...) is a literal. Specifically,
they are intended to be a constant immediate value.
This commit prints "Xl(...)" operand with dis_style_immediate style,
not dis_style_text.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Use dis_style_immediate on
the constant literal of the "Xl..." operand.
This commit fixes two minor typing-related issues for
T-Head immediate operands.
1. A signed type must be specified when printing with %i.
2. unsigned/signed int is not portable enough for max 32-bit immediates.
Instead, we should use unsigned/signed long.
The format string is changed accordingly.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Fix T-Head immediate types on
printing.
On the RISC-V disassembler, some separators have non-text style when
printed with another word with another style.
This commit splits those, making sure that those comma and tabs are printed
with the "text" style.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Split and print the comma as
text. (riscv_disassemble_insn): Split and print tabs as text.
(riscv_disassemble_data): Likewise.
This commit makes types of printf arguments on riscv_disassemble_data
as small as possible (as long as we can preserve the portability) to reduce
the cost of printf (especially on 32-bit host).
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_data): Use smallest possible type
to printing data.
"%x" format specifier requires unsigned type, not int. This commit
fixes this issue on the RISC-V disassembler.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Fix printf argument types where
the format specifier is "%x".
This commit fixes certain print calls on immediate operands to have
dis_style_immediate.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Fix immediates to have
"immediate" style. (riscv_disassemble_data): Likewise.
Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase packet buffer size to 176-bit in size.
include/ChangeLog:
* opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for
use in buffer size.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_riscv): Increase buffer size for max
176-bit length instructions.
This location of supervisor instructions is out of place (because many other
privileged instructions are located at the tail but after the supervisor
instructions, we have many unprivileged instructions including bit
manipulation / crypto / vector instructions).
Not only that, this is harmful to implement pseudoinstructions in the latest
'P'-extension proposal (CLROV and RDOV). This commit moves supervisor
instructions after all unprivileged instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Adjust indents. Move supervisor
instructions after all unprivileged instructions.
This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F'
or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx'
extension already contains "fmv.h" instruction (as well as 'Zfh').
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction.
* testsuite/gas/riscv/zqinx.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]"
instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
Pre- and post-increment/decrement are side effects, the behavior of
which is undefined when combined with passing an address of the accessed
variable in the same function invocation. There's no need for the
increments here - simply adding 1 achieves the intended effect without
triggering compiler diagnostics (which are fatal with -Werror).
FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases.
For disassembly to pick up aliases in favor of underlying insns (helping
readability in the common case), the aliases need to come ahead of the
"base" insns. Slightly more code movement is needed because of insns
with the same name needing to stay next to each other.
Note that the "rorw" alias entry also has the missing INSN_ALIAS added
here.
Clone a few testcases to exercise -Mno-aliases some more, better
covering the differences between the default and that disassembly mode.
With the command in the rule merely being "echo", i386-tbl.h won't be
rebuilt if missing, when at the same time i386-init.h is present and
up-to-date. Use a pattern rule instead to express the multiple targets
correctly (the &: rule separator is supported only by GNU make 4.3 and
newer). Note that now, for the opposite case to work (i386-tbl.h is
up-to-date but i386-init.h is missing), i386-init.h also needs
mentioning as a dependency somewhere: Add a fake dependency for
i386-opc.lo ("fake" because i386-opc.c doesn't include that header).
At the same time use $(AM_V_GEN) in the actual rule, replacing the
earlier (open-coded) "echo". And while there also drop a duplicate
dependency of i386-gen.o on i386-opc.h.
While in some cases deriving an AT&T-style suffix from an Intel syntax
memory operand size specifier is necessary, in many cases this is not
only pointless, but has led to the introduction of various workarounds:
Excessive use of IgnoreSize and NoRex64 as well as the ToDword and
ToQword attributes. Suppress suffix derivation when we can clearly tell
that the memory operand's size isn't going to be needed to infer the
possible need for the low byte/word opcode bit or an operand size prefix
(0x66 or REX.W).
As a result ToDword and ToQword can be dropped entirely, plus a fair
number of IgnoreSize and NoRex64 can also be got rid of. Note that
IgnoreSize needs to remain on legacy encoded SIMD insns with GPR
operand, to avoid emitting an operand size prefix in 16-bit mode. (Since
16-bit code using SIMD insns isn't well tested, clone an existing
testcase just enough to cover a few insns which are potentially
problematic but are being touched here.)
Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI
isn't included there. This is to fulfill the request of not allowing L
and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.
A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary signed or unsigned immediate
encoding formats. The formats have the form "XsN@S" and "XuN@S" with N
being the number of bits and S the LSB position.
For example an immediate field of 5 bytes that encodes a signed value
and is stored in the bits 24-20 of the instruction word can use the
format specifier "Xs5@20".
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
There are a few operand types not used by any RISC-V instructions.
- Cx
- Vf
- Ve
- [
- ]
- b
But most of them has a reasoning to keep them:
- Cx : Same as "Ct" except it has a constraint to have rd == rs2
(similar to "Cw"). Although it hasn't used, its role is clear
enough to implement a new instruction with this operand type.
- Vf, Ve : Used by vector AMO instructions (not ratified and real
instructions are not upstreamed yet).
- [, ] : Unused tokenization symbols. Reserving them is not harmful
and a vendor may use this symbol for special purposes.
... except "b". I could not have found any reference to this operand type
except it works like the "s" operand type. Historically, it seems... it's
just unused from the beginning. Its role is not clear either.
On such cases, we should vacate this room for the new operand type with
much clearer roles.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Remove 'b' operand type.
Some components of GNU Binutils will pass "-Wstack-usage=262144" when
"GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage",
despite that related configuration part in bfd/warning.m4 handles the latest
Clang (15.0.0 as of this writing) as "GCC >= 5.0".
The option "-Wstack-usage" was ignored when the first version of Clang is
released but even this "ignoring" behavior is removed before Clang 4.0.0.
So, if we give Clang "-Wstack-usage=262144", it generates a warning, making
the build failure.
This commit checks "__clang__" macro to prevent adding the option if the
compiler is identified as Clang.
bfd/ChangeLog:
* warning.m4: Stop appending "-Wstack-usage=262144" option when
compiled with Clang.
* configure: Regenerate.
binutils/ChangeLog:
* configure: Regenerate.
gas/ChangeLog:
* configure: Regenerate.
gold/ChangeLog:
* configure: Regenerate.
gprof/ChangeLog:
* configure: Regenerate.
ld/ChangeLog:
* configure: Regenerate.
opcodes/ChangeLog:
* configure: Regenerate.
The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented. They also lacked a bitmask
so new instructions could not be enabled by those options. Fixed.
binutils/
* doc/binutils.texi: Document -Mfuture.
gas/
* config/tc-ppc.c: Document -mfuture
* doc/c-ppc.texi: Likewise.
include/
* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.
opcodes/
* ppc-dis.c (ppc_opts) <future>: Use it.
* ppc-opc.c (FUTURE): Define.
While PR binutils/29483 has now been addressed differently, this
originally proposed change still has its merits: Avoiding vsnprintf()
for typically far more than half of the overall output results in a 2-3%
performance gain in my testing (with debug builds of objdump, libbfd,
and libopcodes).
With that part of output no longer using staging_area[], the array also
doesn't need to be quite as large anymore (the largest presently used
size is 27, from "64-bit address is disabled").
While limiting the scope of "res" it became apparent that
- no caller cares about the function's return value,
- the comment about the return value was wrong,
- a particular positive return value would have been meaningless to the
caller.
Therefore convert the function to return "void" at the same time.
This is paired with "gdb: Add non-enum disassembler options".
There is a portable mechanism for disassembler options and used on some
architectures:
- ARC
- Arm
- MIPS
- PowerPC
- RISC-V
- S/390
However, it only supports following forms:
- [NAME]
- [NAME]=[ENUM_VALUE]
Valid values for [ENUM_VALUE] must be predefined in
disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.
In this commit, it adds following format:
- [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)
This is identified by NULL value of disasm_option_arg_t.values
(normally, this is a non-NULL pointer to a NULL-terminated list).
include/ChangeLog:
* dis-asm.h (disasm_option_arg_t): Update comment of values
to allow non-enum disassembler options.
opcodes/ChangeLog:
* riscv-dis.c (print_riscv_disassembler_options): Support
non-enum disassembler options on printing disassembler help.
* arc-dis.c (print_arc_disassembler_options): Likewise.
* mips-dis.c (print_mips_disassembler_options): Likewise.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
When displaying operands, invalid opcodes may overflow operand buffer
due to additional styling characters. Each style is encoded with 3
bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and
increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles
in an operand.
gas/
PR binutils/29483
* testsuite/gas/i386/i386.exp: Run pr29483.
* testsuite/gas/i386/pr29483.d: New file.
* testsuite/gas/i386/pr29483.s: Likewise.
opcodes/
PR binutils/29483
* i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New.
(obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE.
(staging_area): Likewise.
(op_out): Likewise.
Now that we can purge templates, let's use this to improve readability a
little by shortening a few of their names, making functionally similar
ones also have identical names in their multiple incarnations.
Many of the vector conversion insns come with X/Y/Z suffixed forms, for
disambiguation purposes in AT&T syntax. All of these gorups follow
certain patterns. Introduce "xy" and "xyz" templates to reduce
redundancy.
To facilitate using a uniform name for both AVX and AVX512, further
introduce a means to purge a previously defined template: A standalone
<name> will be recognized to have this effect.
Note that in the course of the conversion VFPCLASSPH is properly split
to separate AT&T and Intel syntax forms, matching VFPCLASSP{S,D} and
yielding the intended "ambiguous operand size" diagnostic in Intel mode.
Many of the vector integer insns come in byte/word element pairs. Most
of these pairs follow certain encoding patterns. Introduce a "bw"
template to reduce redundancy.
Note that in the course of the conversion
- the AVX VPEXTRW template which is not being touched needs to remain
ahead of the new "combined" ones, as (a) this should be tried first
when matching insns against templates and (b) its Load attributes
requires it to be first,
- this add a benign/meaningless IgnoreSize attribute to the memory form
of PEXTRB; it didn't seem worth avoiding this.
Many of the vector integer insns come in dword/qword element pairs. Most
of these pairs follow certain encoding patterns. Introduce a "dq"
template to reduce redundancy.
Note that in the course of the conversion
- a few otherwise untouched templates are moved, so they end up next to
their siblings),
- drop an unhelpful Cpu64 from the GPR form of VPBROADCASTQ, matching
what we already have for KMOVQ - the diagnostic is better this way for
insns with multiple forms (i.e. the same Cpu64 attributes on {,V}MOVQ,
{,V}PEXTRQ, and {,V}PINSRQ are useful to keep),
- this adds benign/meaningless IgnoreSize attributes to the GPR forms of
KMOVD and VPBROADCASTD; it didn't seem worth avoiding this.
The vast majority of vector FP insns comes in single/double pairs. Many
pairs follow certain encoding patterns. Introduce an "sd" template to
reduce redundancy. Similarly, to further cover similarities between
AVX512F and AVX512-FP16, introduce an "sdh" template.
For element-size Disp8 shift generalize i386-gen's broadcast size
determination, allowing Disp8MemShift to be specified without an operand
in the affected templated templates. While doing the adjustment also
eliminate an unhelpful (lost information) diagnostic combined with a use
after free in what is now get_element_size().
Note that in the course of the conversion
- the AVX512F form of VMOVUPD has a stray (leftover) Load attribute
dropped,
- VMOVSH has a benign IgnoreSize added (the attribute is still strictly
necessary for VMOVSD, and necessary for VMOVSS as long as we permit
strange combinations like "-march=i286+avx"),
- VFPCLASSPH is properly split to separate AT&T and Intel syntax forms,
matching VFPCLASSP{S,D}.
This reverts commit 384f368958, which
broke i386-gen's emitting of diagnostics. As a replacement to address
the original issue of newer gcc no longer splicing lines when dropping
the line continuation backslashes, switch to using + as the line
continuation character, doing the line splicing in i386-gen.
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.
The non-SSE2AVX form of the SIMD variant of the instruction needlessly
has the (still multi-purpose) IgnoreSize attribute. All other similar
SSE2 insns use NoRex64 instead. Make this consistent, noting that the
SSE2AVX form can't have the same change made - there the memory operand
doesn't at the same time permit RegXMM (which logic uses when deciding
whether a Q suffix is okay outside of 64-bit mode).
While the other three variants each differ in attributes and hence can't
be folded, these two pairs actually can be (and were previously
overlooked). This effectively matches their AVX512VL counterparts, which
are also expressed as a single template.
While the x/y/z suffix isn't necessary to use in this case, it is still
odd that these forms don't support broadcast (unlike their AVX512F /
AVX512DQ counterparts). The lack thereof can e.g. make macro-ized
programming more difficult.
One more place where pre-existing templates should have been taken as a
basis: In Intel syntax we want to consistently issue an "ambiguous
operand size" error when a size-less memory operand is specified for an
insn where register use alone isn't sufficient for disambiguation.
BFD_VMA_FMT can't be used in format strings that need to be
translated, because the translation won't work when the type of
bfd_vma differs from the machine used to compile .pot files. We've
known about this for a long time, but patches slip through review.
So just get rid of BFD_VMA_FMT, instead using the appropriate PRId64,
PRIu64, PRIx64 or PRIo64 and SCN variants for scanf. The patch is
mostly mechanical, the only thing requiring any thought is casts
needed to preserve PRId64 output from bfd_vma values, or to preserve
one of the unsigned output formats from bfd_signed_vma values.
First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it
has also been used for KMOV* and BNDMOV. Then simplify the condition
selecting which form if "reversing" to use - except for the MOV to/from
control/debug/test registers all extended opcode space insns use bit 0
(rather than bit 1) to indicate the direction (from/to memory) of an
operation. With that, D can simply be set on the first of the two
templates, while the other can be dropped.
This syntactic sugar is present in both classical and emerging
architectures, like Alpha, SPARC and RISC-V, and assembler macros
doing the same thing can already be found in the wild e.g. [1], proving
the feature's popularity. It's better to provide support directly in the
assembler so downstream users wouldn't have to re-invent this over and
over again.
[1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
Also re-order the jump/branch opcodes while at it, so that insns are
sorted in ascending order according to opcodes, and the label form
preceding the real definition.
These two macros print either a 16 digit hex number or an 8 digit
hex number. Unfortunately they depend on both target and host, which
means that the output for 32-bit targets may be either 8 or 16 hex
digits.
Replace them in most cases with code that prints a bfd_vma using
PRIx64. In some cases, deliberately lose the leading zeros.
This change some output, notably in base/offset fields of m68k
disassembly which I think looks better that way, and in error
messages. I've kept leading zeros in symbol dumps (objdump -t)
and in PE header dumps.
bfd/
* bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete.
* bfd-in2.h: Regenerate.
* bfd.c (bfd_sprintf_vma): Don't use sprintf_vma.
(bfd_fprintf_vma): Don't use fprintf_vma.
* coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(xcoff_ppc_relocate_section): Likewise.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* mmo.c (mmo_write_symbols_and_terminator): Likewise.
* srec.c (srec_write_symbols): Likewise.
* elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma.
* pei-x86_64.c (pex64_dump_xdata): Likewise.
(pex64_bfd_print_pdata_section): Likewise.
* som.c (som_print_symbol): Likewise.
* ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma.
opcodes/
* dis-buf.c (perror_memory, generic_print_address): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* i386-dis.c (print_operand_value, print_displacement): Likewise.
* m68k-dis.c (print_base, print_indexed): Likewise.
* ns32k-dis.c (print_insn_arg): Likewise.
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete.
(opcode_fprintf_vma): Delete.
(print_main_table): Use PRIx64 to print opcode.
binutils/
* od-macho.c: Replace all uses of printf_vma with bfd_printf_vma.
* objcopy.c (copy_object): Don't use sprintf_vma. Instead use
PRIx64 to print bfd_vma values.
(copy_main): Likewise.
* readelf.c (CHECK_ENTSIZE_VALUES): Likewise.
(dynamic_section_mips_val): Likewise.
(print_vma): Don't use printf_vma. Instead use PRIx64 to print
bfd_vma values.
(dump_ia64_vms_dynamic_fixups): Likewise.
(process_version_sections): Likewise.
* rddbg.c (stab_context): Likewise.
gas/
* config/tc-i386.c (offset_in_range): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(md_assemble): Likewise.
* config/tc-mips.c (load_register, macro): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* config/tc-ia64.c (note_register_values): Don't use fprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(print_dependency): Likewise.
* listing.c (list_symbol_table): Use bfd_sprintf_vma.
* symbols.c (print_symbol_value_1): Use %p to print pointers.
(print_binary): Likewise.
(print_expr_1): Use PRIx64 to print bfd_vma values.
* write.c (print_fixup): Use %p to print pointers. Don't use
fprintf_vma.
* testsuite/gas/all/overflow.l: Update expected output.
* testsuite/gas/m68k/mcf-mov3q.d: Likewise.
* testsuite/gas/m68k/operands.d: Likewise.
* testsuite/gas/s12z/truncated.d: Likewise.
ld/
* deffilep.y (def_file_print): Don't use fprintf_vma. Instead
use PRIx64 to print bfd_vma values.
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise.
* ldlang.c (lang_map): Use %V to print region origin.
(lang_one_common): Don't use sprintf_vma.
* ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma.
* pe-dll.c (pe_dll_generate_def_file): Likewise.
gdb/
* remote.c (remote_target::trace_set_readonly_regions): Replace
uses of sprintf_vma with bfd_sprintf_vma.
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
It's entirely unclear why some of the KeyLocker insns had NoRex64 on
them - there's nothing here which could cause emission of REX.W (except
of course a user-specified "rex.w", which we ought to honor anyway).
This commit adds disassembler styling to the libopcodes ppc
disassembler. This conversion was pretty straight forward, I just
converted the fprintf_func calls to fprintf_styled_func calls and
added an appropriate style.
For testing the new styling I just assembled then disassembled the
source files in gas/testsuite/gas/ppc and manually checked that the
styling looked reasonable.
I think the only slightly weird case was how things like '4*cr1+eq'
are styled. As best I can tell, this construct, used for example in
this instruction:
crand 4*cr1+lt,4*cr1+gt,4*cr1+eq
is used to access a field of a control register. I initially tried
styling this whole construct as a register[1], but during review it
was suggested that instead different parts of the text should have
different styles. In this commit I propose styling '4*cr1+lt' like
this:
4 - immediate,
* - text,
cr1 - register
+ - text
lt - sub-mnemonic
If the user does not request styled output from objdump, then there
should be no change in the disassembler output after this commit.
[1] https://sourceware.org/pipermail/binutils/2022-July/121771.html
