mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-26 19:44:11 +08:00
x86: optimize LEA
Over the years I've seen a number of instances where people used
lea (%reg1), %reg2
or
lea symbol, %reg
despite the same thing being expressable via MOV. Since additionally
LEA often has restrictions towards the ports it can be issued to, while
MOV typically gets dealt with simply by register renaming, transform to
MOV when possible (without growing opcode size and without altering
involved relocation types).
Note that for Mach-O the new 64-bit testcases would fail (for
BFD_RELOC_X86_64_32S not having a representation), and hence get skipped
there.
This commit is contained in:
Jan Beulich
parent
b818855549
commit
fe134c6569
@ -1,3 +1,16 @@
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2021-04-26 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (want_disp32): Also check for SIZE32.
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(optimize_encoding): Handle LEA.
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* testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d,
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testsuite/gas/i386/lea.e, testsuite/gas/i386/lea-optimize.d:
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Add many more forms.
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* testsuite/gas/i386/lea16.s, testsuite/gas/i386/lea16-optimize.d,
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testsuite/gas/i386/lea64.s, testsuite/gas/i386/lea64.d,
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testsuite/gas/i386/lea64.e, testsuite/gas/i386/lea64-optimize.d:
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New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2021-04-26 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_apply_fix): Mark BFD_RELOC_X86_64_32S as
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@ -3562,7 +3562,8 @@ want_disp32 (const insn_template *t)
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|| i.prefix[ADDR_PREFIX]
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|| (t->base_opcode == 0x8d
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&& t->opcode_modifier.opcodespace == SPACE_BASE
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&& !i.types[1].bitfield.qword);
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&& (!i.types[1].bitfield.qword
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|| t->opcode_modifier.size == SIZE32));
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}
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static int
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@ -4069,6 +4070,145 @@ optimize_encoding (void)
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{
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unsigned int j;
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if (i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.tm.base_opcode == 0x8d)
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{
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/* Optimize: -O:
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lea symbol, %rN -> mov $symbol, %rN
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lea (%rM), %rN -> mov %rM, %rN
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lea (,%rM,1), %rN -> mov %rM, %rN
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and in 32-bit mode for 16-bit addressing
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lea (%rM), %rN -> movzx %rM, %rN
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and in 64-bit mode zap 32-bit addressing in favor of using a
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32-bit (or less) destination.
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*/
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if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
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{
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if (!i.op[1].regs->reg_type.bitfield.word)
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i.tm.opcode_modifier.size = SIZE32;
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i.prefix[ADDR_PREFIX] = 0;
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}
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if (!i.index_reg && !i.base_reg)
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{
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/* Handle:
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lea symbol, %rN -> mov $symbol, %rN
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*/
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if (flag_code == CODE_64BIT)
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{
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/* Don't transform a relocation to a 16-bit one. */
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if (i.op[0].disps
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&& i.op[0].disps->X_op != O_constant
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&& i.op[1].regs->reg_type.bitfield.word)
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return;
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if (!i.op[1].regs->reg_type.bitfield.qword
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|| i.tm.opcode_modifier.size == SIZE32)
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{
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i.tm.base_opcode = 0xb8;
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i.tm.opcode_modifier.modrm = 0;
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if (!i.op[1].regs->reg_type.bitfield.word)
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i.types[0].bitfield.imm32 = 1;
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else
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{
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i.tm.opcode_modifier.size = SIZE16;
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i.types[0].bitfield.imm16 = 1;
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}
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}
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else
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{
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/* Subject to further optimization below. */
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i.tm.base_opcode = 0xc7;
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i.tm.extension_opcode = 0;
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i.types[0].bitfield.imm32s = 1;
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i.types[0].bitfield.baseindex = 0;
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}
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}
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/* Outside of 64-bit mode address and operand sizes have to match if
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a relocation is involved, as otherwise we wouldn't (currently) or
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even couldn't express the relocation correctly. */
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else if (i.op[0].disps
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&& i.op[0].disps->X_op != O_constant
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&& ((!i.prefix[ADDR_PREFIX])
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!= (flag_code == CODE_32BIT
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? i.op[1].regs->reg_type.bitfield.dword
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: i.op[1].regs->reg_type.bitfield.word)))
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return;
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else
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{
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i.tm.base_opcode = 0xb8;
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i.tm.opcode_modifier.modrm = 0;
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if (i.op[1].regs->reg_type.bitfield.dword)
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i.types[0].bitfield.imm32 = 1;
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else
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i.types[0].bitfield.imm16 = 1;
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if (i.op[0].disps
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&& i.op[0].disps->X_op == O_constant
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&& i.op[1].regs->reg_type.bitfield.dword
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&& !i.prefix[ADDR_PREFIX] != (flag_code == CODE_32BIT))
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i.op[0].disps->X_add_number &= 0xffff;
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}
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i.tm.operand_types[0] = i.types[0];
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i.imm_operands = 1;
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if (!i.op[0].imms)
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{
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i.op[0].imms = &im_expressions[0];
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i.op[0].imms->X_op = O_absent;
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}
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}
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else if (i.op[0].disps
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&& (i.op[0].disps->X_op != O_constant
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|| i.op[0].disps->X_add_number))
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return;
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else
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{
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/* Handle:
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lea (%rM), %rN -> mov %rM, %rN
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lea (,%rM,1), %rN -> mov %rM, %rN
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lea (%rM), %rN -> movzx %rM, %rN
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*/
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const reg_entry *addr_reg;
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if (!i.index_reg && i.base_reg->reg_num != RegIP)
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addr_reg = i.base_reg;
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else if (!i.base_reg
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&& i.index_reg->reg_num != RegIZ
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&& !i.log2_scale_factor)
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addr_reg = i.index_reg;
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else
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return;
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if (addr_reg->reg_type.bitfield.word
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&& i.op[1].regs->reg_type.bitfield.dword)
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{
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if (flag_code != CODE_32BIT)
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return;
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i.tm.opcode_modifier.opcodespace = SPACE_0F;
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i.tm.base_opcode = 0xb7;
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}
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else
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i.tm.base_opcode = 0x8b;
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if (addr_reg->reg_type.bitfield.dword
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&& i.op[1].regs->reg_type.bitfield.qword)
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i.tm.opcode_modifier.size = SIZE32;
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i.op[0].regs = addr_reg;
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i.reg_operands = 2;
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}
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i.mem_operands = 0;
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i.disp_operands = 0;
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i.prefix[ADDR_PREFIX] = 0;
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i.prefix[SEG_PREFIX] = 0;
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i.seg[0] = NULL;
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}
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if (optimize_for_space
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&& i.tm.opcode_modifier.opcodespace == SPACE_BASE
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&& i.reg_operands == 1
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@ -538,6 +538,7 @@ if [gas_32_check] then {
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run_dump_test "optimize-6b"
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run_list_test "optimize-7" "-I${srcdir}/$subdir -march=+noavx2 -al"
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run_dump_test "lea-optimize"
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run_dump_test "lea16-optimize"
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run_dump_test "align-branch-1a"
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run_dump_test "align-branch-1b"
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run_dump_test "align-branch-1c"
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@ -1194,6 +1195,8 @@ if [gas_64_check] then {
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run_dump_test "x86-64-align-branch-2a"
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run_dump_test "x86-64-align-branch-2b"
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run_dump_test "x86-64-align-branch-2c"
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run_dump_test "lea64"
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run_dump_test "lea64-optimize"
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}
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run_dump_test "x86-64-align-branch-4a"
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run_dump_test "x86-64-align-branch-4b"
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@ -1,6 +1,6 @@
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#as: -O -q
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#objdump: -dw
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#name: i386 LEA-like segment overrride dropping
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#name: i386 LEA optimizations
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#source: lea.s
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.*: +file format .*
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@ -8,6 +8,41 @@
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Disassembly of section .text:
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0+ <start>:
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[ ]*[0-9a-f]+:[ ]+8d 00[ ]+lea[ ]+\(%eax\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 00[ ]+lea[ ]+\(%eax\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 08[ ]+lea[ ]+\(%eax,%ecx(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 08[ ]+lea[ ]+\(%eax,%ecx(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 48 01[ ]+lea[ ]+0x1\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 88 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 0c 25 00 00 00 00[ ]+lea[ ]+0x0\(,(%eiz)?(,1)?\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 04 00[ ]+lea[ ]+\(%eax,%eax(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 45 00 00 00 00[ ]+lea[ ]+0x0\(,%eax,2\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,(%eiz)?(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+67 8d 00[ ]+lea[ ]+\(%bx,%si\),%eax
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[ ]*[0-9a-f]+:[ ]+8b c0[ ]+mov[ ]+%eax,%eax
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[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
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[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
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[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
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[ ]*[0-9a-f]+:[ ]+0f b7 c6[ ]+movzwl[ ]+%si,%eax
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[ ]*[0-9a-f]+:[ ]+0f b7 f6[ ]+movzwl[ ]+%si,%esi
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[ ]*[0-9a-f]+:[ ]+0f b7 c6[ ]+movzwl[ ]+%si,%eax
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[ ]*[0-9a-f]+:[ ]+66 8b c0[ ]+mov[ ]+%ax,%ax
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[ ]*[0-9a-f]+:[ ]+66 8b c8[ ]+mov[ ]+%ax,%cx
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[ ]*[0-9a-f]+:[ ]+66 8b c8[ ]+mov[ ]+%ax,%cx
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[ ]*[0-9a-f]+:[ ]+66 8b c6[ ]+mov[ ]+%si,%ax
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[ ]*[0-9a-f]+:[ ]+66 8b f6[ ]+mov[ ]+%si,%si
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[ ]*[0-9a-f]+:[ ]+8b c9[ ]+mov[ ]+%ecx,%ecx
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[ ]*[0-9a-f]+:[ ]+8b c1[ ]+mov[ ]+%ecx,%eax
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[ ]*[0-9a-f]+:[ ]+b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 02 00[ ]+mov[ ]+\$0x2,%ax
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[ ]*[0-9a-f]+:[ ]+b8 ff ff ff ff[ ]+mov[ ]+\$0xffffffff,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 fe ff[ ]+mov[ ]+\$0xfffe,%ax
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[ ]*[0-9a-f]+:[ ]+b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 02 00[ ]+mov[ ]+\$0x2,%ax
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[ ]*[0-9a-f]+:[ ]+b8 ff ff 00 00[ ]+mov[ ]+\$0xffff,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 fe ff[ ]+mov[ ]+\$0xfffe,%ax
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[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
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[ ]*[0-9a-f]+:[ ]+66 8d 05 00 00 00 00[ ]+lea[ ]+0x0,%ax
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[ ]*[0-9a-f]+:[ ]+67 8d 06 00 00[ ]+lea[ ]+0x0,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+mov[ ]+\$0x0,%ax
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[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
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[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+mov[ ]+\$0x0,%ax
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#pass
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@ -7,6 +7,41 @@
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Disassembly of section .text:
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0+ <start>:
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[ ]*[0-9a-f]+:[ ]+36 8d 00[ ]+lea[ ]+%ss:\(%eax\),%eax
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[ ]*[0-9a-f]+:[ ]+36 8d 00[ ]+lea[ ]+%ss:\(%eax\),%eax
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[ ]*[0-9a-f]+:[ ]+36 8d 04 08[ ]+lea[ ]+%ss:\(%eax,%ecx(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+36 8d 04 08[ ]+lea[ ]+%ss:\(%eax,%ecx(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 48 01[ ]+lea[ ]+0x1\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 88 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 0c 25 00 00 00 00[ ]+lea[ ]+0x0\(,(%eiz)?(,1)?\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 04 00[ ]+lea[ ]+\(%eax,%eax(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 45 00 00 00 00[ ]+lea[ ]+0x0\(,%eax,2\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,(%eiz)?(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+67 8d 00[ ]+lea[ ]+\(%bx,%si\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 00[ ]+lea[ ]+\(%eax\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 08[ ]+lea[ ]+\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 08[ ]+lea[ ]+\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+65 8d 08[ ]+lea[ ]+%gs:\(%eax\),%ecx
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[ ]*[0-9a-f]+:[ ]+67 8d 04[ ]+lea[ ]+\(%si\),%eax
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[ ]*[0-9a-f]+:[ ]+67 8d 34[ ]+lea[ ]+\(%si\),%esi
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[ ]*[0-9a-f]+:[ ]+67 8d 04[ ]+lea[ ]+\(%si\),%eax
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[ ]*[0-9a-f]+:[ ]+66 8d 00[ ]+lea[ ]+\(%eax\),%ax
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[ ]*[0-9a-f]+:[ ]+66 8d 08[ ]+lea[ ]+\(%eax\),%cx
|
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[ ]*[0-9a-f]+:[ ]+66 8d 08[ ]+lea[ ]+\(%eax\),%cx
|
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[ ]*[0-9a-f]+:[ ]+67 66 8d 04[ ]+lea[ ]+\(%si\),%ax
|
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[ ]*[0-9a-f]+:[ ]+67 66 8d 34[ ]+lea[ ]+\(%si\),%si
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[ ]*[0-9a-f]+:[ ]+8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%ecx
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[ ]*[0-9a-f]+:[ ]+8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%eax
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[ ]*[0-9a-f]+:[ ]+8d 05 01 00 00 00[ ]+lea[ ]+0x1,%eax
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[ ]*[0-9a-f]+:[ ]+66 8d 05 02 00 00 00[ ]+lea[ ]+0x2,%ax
|
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[ ]*[0-9a-f]+:[ ]+8d 05 ff ff ff ff[ ]+lea[ ]+0xffffffff,%eax
|
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[ ]*[0-9a-f]+:[ ]+66 8d 05 fe ff ff ff[ ]+lea[ ]+0xfffffffe,%ax
|
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[ ]*[0-9a-f]+:[ ]+67 8d 06 01 00[ ]+lea[ ]+0x1,%eax
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[ ]*[0-9a-f]+:[ ]+67 66 8d 06 02 00[ ]+lea[ ]+0x2,%ax
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[ ]*[0-9a-f]+:[ ]+67 8d 06 ff ff[ ]+lea[ ]+-0x1,%eax
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[ ]*[0-9a-f]+:[ ]+67 66 8d 06 fe ff[ ]+lea[ ]+-0x2,%ax
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[ ]*[0-9a-f]+:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0,%eax
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[ ]*[0-9a-f]+:[ ]+66 8d 05 00 00 00 00[ ]+lea[ ]+0x0,%ax
|
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[ ]*[0-9a-f]+:[ ]+67 8d 06 00 00[ ]+lea[ ]+0x0,%eax
|
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[ ]*[0-9a-f]+:[ ]+67 66 8d 06 00 00[ ]+lea[ ]+0x0,%ax
|
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[ ]*[0-9a-f]+:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0,%eax
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[ ]*[0-9a-f]+:[ ]+66 8d 05 00 00 00 00[ ]+lea[ ]+0x0,%ax
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#pass
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@ -1,3 +1,4 @@
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.*: Assembler messages:
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.*:3: Warning: .* `lea' .*
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.*:4: Warning: .* `lea' .*
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.*:19: Warning: .* `lea' .*
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@ -1,4 +1,54 @@
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.text
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start:
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lea %ss:(%eax), %eax
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ss lea (%eax), %eax
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lea %ss:(%eax,%ecx), %eax
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ss lea (%eax,%ecx), %eax
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.allow_index_reg
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lea 1(%eax), %ecx
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lea sym(%eax), %ecx
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lea sym(,%eiz), %ecx
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lea (%eax,%eax), %eax
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lea (,%eax,2), %eax
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lea (,%eiz), %eax
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lea (%bx,%si), %eax
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lea (%eax), %eax
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lea (%eax), %ecx
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lea 1-1(%eax), %ecx
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lea %gs:(%eax), %ecx
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lea (%si), %eax
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lea (%si), %esi
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leal (%si), %eax
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||||
lea (%eax), %ax
|
||||
lea (%eax), %cx
|
||||
leaw (%eax), %cx
|
||||
|
||||
lea (%si), %ax
|
||||
lea (%si), %si
|
||||
|
||||
lea (,%ecx,1), %ecx
|
||||
lea (,%ecx,1), %eax
|
||||
|
||||
lea 1, %eax
|
||||
lea 2, %ax
|
||||
|
||||
lea -1, %eax
|
||||
lea -2, %ax
|
||||
|
||||
addr16 lea 1, %eax
|
||||
addr16 lea 2, %ax
|
||||
|
||||
addr16 lea -1, %eax
|
||||
addr16 lea -2, %ax
|
||||
|
||||
lea sym, %eax
|
||||
lea sym, %ax
|
||||
|
||||
addr16 lea sym, %eax
|
||||
addr16 lea sym, %ax
|
||||
|
||||
lea (,1), %eax
|
||||
lea (,1), %ax
|
||||
|
||||
48
gas/testsuite/gas/i386/lea16-optimize.d
Normal file
48
gas/testsuite/gas/i386/lea16-optimize.d
Normal file
@ -0,0 +1,48 @@
|
||||
#as: -O -q -I${srcdir}/$subdir
|
||||
#objdump: -dw -Mi8086
|
||||
#name: i386 16-bit LEA optimizations
|
||||
#source: lea16.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <start>:
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 08[ ]+lea[ ]+\(%eax,%ecx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 08[ ]+lea[ ]+\(%eax,%ecx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 48 01[ ]+lea[ ]+0x1\(%eax\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 88 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 0c 25 00 00 00 00[ ]+addr32 lea[ ]+0x0,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 00[ ]+lea[ ]+\(%eax,%eax(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 45 00 00 00 00[ ]+lea[ ]+0x0\(,%eax,2\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 25 00 00 00 00[ ]+addr32 lea[ ]+0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 00[ ]+lea[ ]+\(%bx,%si\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c0[ ]+mov[ ]+%eax,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04[ ]+lea[ ]+\(%si\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 34[ ]+lea[ ]+\(%si\),%esi
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04[ ]+lea[ ]+\(%si\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c0[ ]+mov[ ]+%ax,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%ax,%cx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%ax,%cx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c6[ ]+mov[ ]+%si,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+8b f6[ ]+mov[ ]+%si,%si
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c9[ ]+mov[ ]+%ecx,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c1[ ]+mov[ ]+%ecx,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 02 00[ ]+mov[ ]+\$0x2,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 ff ff 00 00[ ]+mov[ ]+\$0xffff,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 fe ff[ ]+mov[ ]+\$0xfffe,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 02 00[ ]+mov[ ]+\$0x2,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 ff ff ff ff[ ]+mov[ ]+\$0xffffffff,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 fe ff[ ]+mov[ ]+\$0xfffe,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 06 00 00[ ]+lea[ ]+0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00[ ]+mov[ ]+\$0x0,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 05 00 00 00 00[ ]+addr32 lea[ ]+0x0,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00[ ]+mov[ ]+\$0x0,%ax
|
||||
#pass
|
||||
7
gas/testsuite/gas/i386/lea16.s
Normal file
7
gas/testsuite/gas/i386/lea16.s
Normal file
@ -0,0 +1,7 @@
|
||||
.code16
|
||||
|
||||
.macro addr16 mnem:req opnds:vararg
|
||||
addr32 \mnem \opnds
|
||||
.endm
|
||||
|
||||
.include "lea.s"
|
||||
71
gas/testsuite/gas/i386/lea64-optimize.d
Normal file
71
gas/testsuite/gas/i386/lea64-optimize.d
Normal file
@ -0,0 +1,71 @@
|
||||
#as: -O -q
|
||||
#objdump: -drw
|
||||
#name: x86-64 LEA optimizations
|
||||
#source: lea64.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <start>:
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 08[ ]+lea[ ]+\(%rax,%rcx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 08[ ]+lea[ ]+\(%rax,%rcx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 48 01[ ]+lea[ ]+0x1\(%rax\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8d 88 00 00 00 00[ ]+lea[ ]+0x0\(%rax\),%ecx[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+8d 0c 25 00 00 00 00[ ]+lea[ ]+0x0,%ecx[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 00[ ]+lea[ ]+\(%rax,%rax(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 45 00 00 00 00[ ]+lea[ ]+0x0\(,%rax,2\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%rip\),%eax($| *#.*)
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c0[ ]+mov[ ]+%rax,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c8[ ]+mov[ ]+%rax,%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c8[ ]+mov[ ]+%rax,%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c8[ ]+mov[ ]+%rax,%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c6[ ]+mov[ ]+%esi,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8b f6[ ]+mov[ ]+%esi,%esi
|
||||
[ ]*[0-9a-f]+:[ ]+8b c6[ ]+mov[ ]+%esi,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c6[ ]+mov[ ]+%si,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b f6[ ]+mov[ ]+%si,%si
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c6[ ]+mov[ ]+%si,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c0[ ]+mov[ ]+%eax,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c0[ ]+mov[ ]+%eax,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c8[ ]+mov[ ]+%eax,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c6[ ]+mov[ ]+%si,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b f6[ ]+mov[ ]+%si,%si
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c6[ ]+mov[ ]+%si,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c9[ ]+mov[ ]+%rcx,%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+48 8b c1[ ]+mov[ ]+%rcx,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c9[ ]+mov[ ]+%ecx,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c1[ ]+mov[ ]+%ecx,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c9[ ]+mov[ ]+%cx,%cx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c1[ ]+mov[ ]+%cx,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c9[ ]+mov[ ]+%ecx,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c1[ ]+mov[ ]+%ecx,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8b c9[ ]+mov[ ]+%ecx,%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8b c1[ ]+mov[ ]+%ecx,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c9[ ]+mov[ ]+%cx,%cx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8b c1[ ]+mov[ ]+%cx,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 02 00 00 00[ ]+mov[ ]+\$0x2,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 03 00[ ]+mov[ ]+\$0x3,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 c7 c0 ff ff ff ff[ ]+mov[ ]+\$0xffffffffffffffff,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 fe ff ff ff[ ]+mov[ ]+\$0xfffffffe,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 fd ff[ ]+mov[ ]+\$0xfffd,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 01 00 00 00[ ]+mov[ ]+\$0x1,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 02 00 00 00[ ]+mov[ ]+\$0x2,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 03 00[ ]+mov[ ]+\$0x3,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 ff ff ff ff[ ]+mov[ ]+\$0xffffffff,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 fe ff ff ff[ ]+mov[ ]+\$0xfffffffe,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 fd ff[ ]+mov[ ]+\$0xfffd,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 c7 c0 00 00 00 00[ ]+mov[ ]+\$0x0,%rax[ ]+[0-9a-f]+: R_X86_64_32S[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%ax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%ax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+48 c7 c0 00 00 00 00[ ]+mov[ ]+\$0x0,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 b8 00 00[ ]+mov[ ]+\$0x0,%ax
|
||||
#pass
|
||||
70
gas/testsuite/gas/i386/lea64.d
Normal file
70
gas/testsuite/gas/i386/lea64.d
Normal file
@ -0,0 +1,70 @@
|
||||
#objdump: -drw
|
||||
#name: x86-64 LEA
|
||||
#warning_output: lea64.e
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <start>:
|
||||
[ ]*[0-9a-f]+:[ ]+64 8d 04 08[ ]+lea[ ]+%fs:\(%rax,%rcx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+65 8d 04 08[ ]+lea[ ]+%gs:\(%rax,%rcx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 48 01[ ]+lea[ ]+0x1\(%rax\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8d 88 00 00 00 00[ ]+lea[ ]+0x0\(%rax\),%ecx[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+8d 0c 25 00 00 00 00[ ]+lea[ ]+0x0,%ecx[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 00[ ]+lea[ ]+\(%rax,%rax(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 45 00 00 00 00[ ]+lea[ ]+0x0\(,%rax,2\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%rip\),%eax($| *#.*)
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 00[ ]+lea[ ]+\(%rax\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 08[ ]+lea[ ]+\(%rax\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 08[ ]+lea[ ]+\(%rax\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+65 48 8d 08[ ]+lea[ ]+%gs:\(%rax\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+8d 06[ ]+lea[ ]+\(%rsi\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 36[ ]+lea[ ]+\(%rsi\),%esi
|
||||
[ ]*[0-9a-f]+:[ ]+8d 06[ ]+lea[ ]+\(%rsi\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 06[ ]+lea[ ]+\(%rsi\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 36[ ]+lea[ ]+\(%rsi\),%si
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 06[ ]+lea[ ]+\(%rsi\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 00[ ]+lea[ ]+\(%eax\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 08[ ]+lea[ ]+\(%eax\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 08[ ]+lea[ ]+\(%eax\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 00[ ]+lea[ ]+\(%eax\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 08[ ]+lea[ ]+\(%eax\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 06[ ]+lea[ ]+\(%esi\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 36[ ]+lea[ ]+\(%esi\),%si
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 06[ ]+lea[ ]+\(%esi\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%cx
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%rcx(,1)?\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%rcx
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%ecx
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 0c 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%cx
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 0d 00 00 00 00[ ]+lea[ ]+0x0\(,%ecx(,1)?\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 04 25 01 00 00 00[ ]+lea[ ]+0x1,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 02 00 00 00[ ]+lea[ ]+0x2,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 03 00 00 00[ ]+lea[ ]+0x3,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 04 25 ff ff ff ff[ ]+lea[ ]+0xffffffffffffffff,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 fe ff ff ff[ ]+lea[ ]+0xfffffffffffffffe,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 fd ff ff ff[ ]+lea[ ]+0xfffffffffffffffd,%ax
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 04 25 01 00 00 00[ ]+lea[ ]+0x1\(,%eiz,1\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 04 25 02 00 00 00[ ]+lea[ ]+0x2\(,%eiz,1\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 25 03 00 00 00[ ]+lea[ ]+0x3\(,%eiz,1\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 04 25 ff ff ff ff[ ]+lea[ ]+0xffffffff\(,%eiz,1\),%rax
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 04 25 fe ff ff ff[ ]+lea[ ]+0xfffffffe\(,%eiz,1\),%eax
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 25 fd ff ff ff[ ]+lea[ ]+0xfffffffd\(,%eiz,1\),%ax
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%rax[ ]+[0-9a-f]+: R_X86_64_32S[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%eax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%ax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%rax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+67 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%eax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+67 66 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%ax[ ]+[0-9a-f]+: R_X86_64_32[ ]+sym
|
||||
[ ]*[0-9a-f]+:[ ]+48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%rax
|
||||
[ ]*[0-9a-f]+:[ ]+8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%eax
|
||||
[ ]*[0-9a-f]+:[ ]+66 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0,%ax
|
||||
#pass
|
||||
4
gas/testsuite/gas/i386/lea64.e
Normal file
4
gas/testsuite/gas/i386/lea64.e
Normal file
@ -0,0 +1,4 @@
|
||||
.*: Assembler messages:
|
||||
.*:3: Warning: .* `lea' .*
|
||||
.*:4: Warning: .* `lea' .*
|
||||
.*:19: Warning: .* `lea' .*
|
||||
84
gas/testsuite/gas/i386/lea64.s
Normal file
84
gas/testsuite/gas/i386/lea64.s
Normal file
@ -0,0 +1,84 @@
|
||||
.text
|
||||
start:
|
||||
lea %fs:(%rax,%rcx), %eax
|
||||
gs lea (%rax,%rcx), %eax
|
||||
|
||||
.allow_index_reg
|
||||
lea 1(%rax), %ecx
|
||||
lea sym(%rax), %ecx
|
||||
lea sym(,%riz), %ecx
|
||||
|
||||
lea (%rax,%rax), %eax
|
||||
lea (,%rax,2), %eax
|
||||
lea (%rip), %eax
|
||||
lea (,%riz), %eax
|
||||
|
||||
lea (%rax), %rax
|
||||
lea (%rax), %rcx
|
||||
lea 1-1(%rax), %rcx
|
||||
lea %gs:(%rax), %rcx
|
||||
|
||||
lea (%rsi), %eax
|
||||
lea (%rsi), %esi
|
||||
leal (%rsi), %eax
|
||||
|
||||
lea (%rsi), %ax
|
||||
lea (%rsi), %si
|
||||
leaw (%rsi), %ax
|
||||
|
||||
lea (%eax), %rax
|
||||
lea (%eax), %rcx
|
||||
leaq (%eax), %rcx
|
||||
|
||||
lea (%eax), %eax
|
||||
lea (%eax), %ecx
|
||||
|
||||
lea (%esi), %ax
|
||||
lea (%esi), %si
|
||||
leaw (%esi), %ax
|
||||
|
||||
lea (,%rcx,1), %rcx
|
||||
lea (,%rcx,1), %rax
|
||||
|
||||
lea (,%rcx,1), %ecx
|
||||
lea (,%rcx,1), %eax
|
||||
|
||||
lea (,%rcx,1), %cx
|
||||
lea (,%rcx,1), %ax
|
||||
|
||||
lea (,%ecx,1), %rcx
|
||||
lea (,%ecx,1), %rax
|
||||
|
||||
lea (,%ecx,1), %ecx
|
||||
lea (,%ecx,1), %eax
|
||||
|
||||
lea (,%ecx,1), %cx
|
||||
lea (,%ecx,1), %ax
|
||||
|
||||
lea 1, %rax
|
||||
lea 2, %eax
|
||||
lea 3, %ax
|
||||
|
||||
lea -1, %rax
|
||||
lea -2, %eax
|
||||
lea -3, %ax
|
||||
|
||||
addr32 lea 1, %rax
|
||||
addr32 lea 2, %eax
|
||||
addr32 lea 3, %ax
|
||||
|
||||
addr32 lea -1, %rax
|
||||
addr32 lea -2, %eax
|
||||
addr32 lea -3, %ax
|
||||
|
||||
lea sym, %rax
|
||||
lea sym, %eax
|
||||
lea sym, %ax
|
||||
|
||||
addr32 lea sym, %rax
|
||||
addr32 lea sym, %eax
|
||||
addr32 lea sym, %ax
|
||||
|
||||
lea (,1), %rax
|
||||
lea (,1), %eax
|
||||
lea (,1), %ax
|
||||
@ -1,3 +1,8 @@
|
||||
2021-04-26 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.tbl (lea): Add Optimize.
|
||||
* opcodes/i386-tbl.h: Re-generate.
|
||||
|
||||
2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
|
||||
|
||||
* xtensa-dis.c (print_xtensa_operand): For PC-relative operand
|
||||
|
||||
@ -228,7 +228,7 @@ out, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
|
||||
out, 0xee, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg }
|
||||
|
||||
// Load effective address.
|
||||
lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf, { BaseIndex, Reg16|Reg32|Reg64 }
|
||||
lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
||||
// Load segment registers from memory.
|
||||
lds, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
|
||||
|
||||
@ -1121,7 +1121,7 @@ const insn_template i386_optab[] =
|
||||
{ "lea", 0x8d, None, 2,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user