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Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html I cleared reserved bits when reading CPSR. It makes a problem that these bits (zero) are written back to kernel through ptrace, and it changes the state of the processor on some recent kernel, which is unexpected. In this patch, I keep these reserved bits when write CPSR back to hardware. gdb: 2016-09-21 Yao Qi <yao.qi@linaro.org> * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep bits 20 to 23. gdb/gdbserver: 2016-09-21 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to 23.
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@ -1,3 +1,8 @@
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2016-09-21 Yao Qi <yao.qi@linaro.org>
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* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
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bits 20 to 23.
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2016-09-20 Tom Tromey <tom@tromey.com>
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* python/py-value.c (convert_value_from_python): Make PyInt_Check
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@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs,
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if (arm_apcs_32
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&& REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM))
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regcache_raw_collect (regcache, ARM_PS_REGNUM,
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®s[ARM_CPSR_GREGNUM]);
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{
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uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
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regcache_raw_collect (regcache, ARM_PS_REGNUM,
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®s[ARM_CPSR_GREGNUM]);
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/* Keep reserved bits bit 20 to bit 23. */
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regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
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| (cpsr & 0x00f00000));
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}
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}
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/* Supply VFP registers contents, stored in REGS, to REGCACHE.
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@ -1,3 +1,8 @@
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2016-09-21 Yao Qi <yao.qi@linaro.org>
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* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
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23.
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2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com>
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* server.c (start_inferior): Call target_mourn_inferior instead of
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@ -62,11 +62,15 @@ arm_fill_gregset (struct regcache *regcache, void *buf)
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{
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int i;
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uint32_t *regs = (uint32_t *) buf;
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uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
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for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
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collect_register (regcache, i, ®s[i]);
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collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
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/* Keep reserved bits bit 20 to bit 23. */
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regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
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| (cpsr & 0x00f00000));
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}
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/* Supply GP registers contents, stored in BUF, to REGCACHE. */
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