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RISC-V: Scalar crypto instruction and entropy source CSR testcases.

Browse Source 
Add testcases for Scalar Crypto extension, with total testcase contain all
instructions in k-ext/k-ext-64 and sub-extension testcase for zbk* zk*. Also
add testcase for new CSR name 'seed' which is the Entropy Source in zkr.

In fact these whole testcases can be combined into one file, after we have
supported the .option arch +-= directives.

gas/
	* testsuite/gas/riscv/k-ext-64.d: New testcase for crypto instructions.
	* testsuite/gas/riscv/k-ext-64.s: Likewise.
	* testsuite/gas/riscv/k-ext.d: Likewise.
	* testsuite/gas/riscv/k-ext.s: Likewise.
	* testsuite/gas/riscv/zbkb-32.d: Likewise.
	* testsuite/gas/riscv/zbkb-32.s: Likewise.
	* testsuite/gas/riscv/zbkb-64.d: Likewise.
	* testsuite/gas/riscv/zbkb-64.s: Likewise.
	* testsuite/gas/riscv/zbkc-32.d: Likewise.
	* testsuite/gas/riscv/zbkc-64.d: Likewise.
	* testsuite/gas/riscv/zbkc.s: Likewise.
	* testsuite/gas/riscv/zbkx-32.d: Likewise.
	* testsuite/gas/riscv/zbkx-64.d: Likewise.
	* testsuite/gas/riscv/zbkx.s: Likewise.
	* testsuite/gas/riscv/zknd-32.d: Likewise.
	* testsuite/gas/riscv/zknd-32.s: Likewise.
	* testsuite/gas/riscv/zknd-64.d: Likewise.
	* testsuite/gas/riscv/zknd-64.s: Likewise.
	* testsuite/gas/riscv/zkne-32.d: Likewise.
	* testsuite/gas/riscv/zkne-32.s: Likewise.
	* testsuite/gas/riscv/zkne-64.d: Likewise.
	* testsuite/gas/riscv/zkne-64.s: Likewise.
	* testsuite/gas/riscv/zknh-32.d: Likewise.
	* testsuite/gas/riscv/zknh-32.s: Likewise.
	* testsuite/gas/riscv/zknh-64.d: Likewise.
	* testsuite/gas/riscv/zknh-64.s: Likewise.
	* testsuite/gas/riscv/zksed-32.d: Likewise.
	* testsuite/gas/riscv/zksed-64.d: Likewise.
	* testsuite/gas/riscv/zksed.s: Likewise.
	* testsuite/gas/riscv/zksh-32.d: Likewise.
	* testsuite/gas/riscv/zksh-64.d: Likewise.
	* testsuite/gas/riscv/zksh.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-zkr.d: New testcase for zkr
	csr check.
	* testsuite/gas/riscv/priv-reg-fail-zkr.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated march to
	rv32if_zkr.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Added Crypto seed csr.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.
This commit is contained in:
jiawei 2021-11-15 11:03:43 +08:00 committed by Nelson Chu
parent 3d1cafa0c6
commit fc5c1c28b3
41 changed files with 490 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
gas/testsuite/gas/riscv/k-ext-64.d Normal file
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#as: -march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
#source: k-ext-64.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0

38
gas/testsuite/gas/riscv/k-ext-64.s Normal file
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target:
ror a0, a1, a2
rol a0, a1, a2
rori a0, a1, 2
rorw a0, a1, a2
rolw a0, a1, a2
roriw a0, a1, 2
andn a0, a1, a2
orn a0, a1, a2
xnor a0, a1, a2
pack a0, a1, a2
packh a0, a1, a2
packw a0, a1, a2
brev8 a0, a0
rev8 a0, a0
clmul a0, a1, a2
clmulh a0, a1, a2
xperm4 a0, a1, a2
xperm8 a0, a1, a2
aes64ds a0, a1, a2
aes64dsm a0, a1, a2
aes64im a0, a0
aes64ks1i a0, a1, 4
aes64ks2 a0, a1, a2
aes64es a0, a1, a2
aes64esm a0, a1, a2
sha256sig0 a0, a0
sha256sig1 a0, a0
sha256sum0 a0, a0
sha256sum1 a0, a0
sha512sig0 a0, a0
sha512sig1 a0, a0
sha512sum0 a0, a0
sha512sum1 a0, a0
sm4ed a0, a1, a2, 2
sm4ks a0, a1, a2, 2
sm3p0 a0, a0
sm3p1 a0, a0

44
gas/testsuite/gas/riscv/k-ext.d Normal file
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#as: -march=rv32i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt
#source: k-ext.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0

35
gas/testsuite/gas/riscv/k-ext.s Normal file
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target:
ror a0, a1, a2
rol a0, a1, a2
rori a0, a1, 2
andn a0, a1, a2
orn a0, a1, a2
xnor a0, a1, a2
pack a0, a1, a2
packh a0, a1, a2
brev8 a0, a0
rev8 a0, a0
zip a0, a0
unzip a0, a0
clmul a0, a1, a2
clmulh a0, a1, a2
xperm4 a0, a1, a2
xperm8 a0, a1, a2
aes32dsi a0, a1, a2, 2
aes32dsmi a0, a1, a2, 2
aes32esi a0, a1, a2, 2
aes32esmi a0, a1, a2, 2
sha256sig0 a0, a0
sha256sig1 a0, a0
sha256sum0 a0, a0
sha256sum1 a0, a0
sha512sig0h a0, a1, a2
sha512sig0l a0, a1, a2
sha512sig1h a0, a1, a2
sha512sig1l a0, a1, a2
sha512sum0r a0, a1, a2
sha512sum1r a0, a1, a2
sm4ed a0, a1, a2, 2
sm4ks a0, a1, a2, 2
sm3p0 a0, a0
sm3p1 a0, a0

2
gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
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@ -1,4 +1,4 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.10 -march-attr
#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.10 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p10.l
#readelf: -A

2
gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
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@ -1,4 +1,4 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.11 -march-attr
#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.11 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p11.l
#readelf: -A

2
gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
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@ -1,4 +1,4 @@
#as: -march=rv32if -mcsr-check -mpriv-spec=1.9.1 -march-attr
#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.9.1 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9p1.l
#readelf: -A

3
gas/testsuite/gas/riscv/priv-reg-fail-zkr.d Normal file
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@ -0,0 +1,3 @@
#as: -march=rv32if -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-zkr.l

4
gas/testsuite/gas/riscv/priv-reg-fail-zkr.l Normal file
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@ -0,0 +1,4 @@
.*Assembler messages:
#...
.*Warning: invalid CSR `seed' for the current ISA
#...

1
gas/testsuite/gas/riscv/priv-reg-version-1p10.d
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@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed

1
gas/testsuite/gas/riscv/priv-reg-version-1p11.d
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@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed

1
gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
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@ -265,3 +265,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed

3
gas/testsuite/gas/riscv/priv-reg.s
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@ -282,3 +282,6 @@
csr etrigger # 0x7a1, alias to tdata1
csr textra32 # 0x7a3, alias to tdata3
csr textra64 # 0x7a3, alias to tdata3
# Scalar crypto
csr seed # 0x015, Entropy Source

22
gas/testsuite/gas/riscv/zbkb-32.d Normal file
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#as: -march=rv32i_zbkb
#source: zbkb-32.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+zip[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+unzip[ ]+a0,a0

13
gas/testsuite/gas/riscv/zbkb-32.s Normal file
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@ -0,0 +1,13 @@
target:
ror a0, a1, a2
rol a0, a1, a2
rori a0, a1, 2
andn a0, a1, a2
orn a0, a1, a2
xnor a0, a1, a2
pack a0, a1, a2
packh a0, a1, a2
brev8 a0, a0
rev8 a0, a0
zip a0, a0
unzip a0, a0

24
gas/testsuite/gas/riscv/zbkb-64.d Normal file
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#as: -march=rv64i_zbkb
#source: zbkb-64.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+ror[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rol[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rori[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+rorw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+rolw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+roriw[ ]+a0,a1,0x2
[ ]+.*:[ ]+.*[ ]+andn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+orn[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xnor[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+pack[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packh[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+packw[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+brev8[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+rev8[ ]+a0,a0

15
gas/testsuite/gas/riscv/zbkb-64.s Normal file
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target:
ror a0, a1, a2
rol a0, a1, a2
rori a0, a1, 2
rorw a0, a1, a2
rolw a0, a1, a2
roriw a0, a1, 2
andn a0, a1, a2
orn a0, a1, a2
xnor a0, a1, a2
pack a0, a1, a2
packh a0, a1, a2
packw a0, a1, a2
brev8 a0, a0
rev8 a0, a0

12
gas/testsuite/gas/riscv/zbkc-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zbkc
#source: zbkc.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2

12
gas/testsuite/gas/riscv/zbkc-64.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv64i_zbkc
#source: zbkc.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+clmul[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+clmulh[ ]+a0,a1,a2

3
gas/testsuite/gas/riscv/zbkc.s Normal file
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@ -0,0 +1,3 @@
target:
clmul a0, a1, a2
clmulh a0, a1, a2

12
gas/testsuite/gas/riscv/zbkx-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zbkx
#source: zbkx.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2

12
gas/testsuite/gas/riscv/zbkx-64.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv64i_zbkx
#source: zbkx.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+xperm4[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+xperm8[ ]+a0,a1,a2

3
gas/testsuite/gas/riscv/zbkx.s Normal file
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@ -0,0 +1,3 @@
target:
xperm4 a0, a1, a2
xperm8 a0, a1, a2

12
gas/testsuite/gas/riscv/zknd-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zknd
#source: zknd-32.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+aes32dsi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+aes32dsmi[ ]+a0,a1,a2,0x2

3
gas/testsuite/gas/riscv/zknd-32.s Normal file
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@ -0,0 +1,3 @@
target:
aes32dsi a0, a1, a2, 2
aes32dsmi a0, a1, a2, 2

15
gas/testsuite/gas/riscv/zknd-64.d Normal file
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@ -0,0 +1,15 @@
#as: -march=rv64i_zknd
#source: zknd-64.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+aes64ds[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64dsm[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64im[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2

6
gas/testsuite/gas/riscv/zknd-64.s Normal file
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@ -0,0 +1,6 @@
target:
aes64ds a0, a1, a2
aes64dsm a0, a1, a2
aes64im a0, a0
aes64ks1i a0, a1, 4
aes64ks2 a0, a1, a2

12
gas/testsuite/gas/riscv/zkne-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zkne
#source: zkne-32.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+aes32esi[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+aes32esmi[ ]+a0,a1,a2,0x2

3
gas/testsuite/gas/riscv/zkne-32.s Normal file
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@ -0,0 +1,3 @@
target:
aes32esi a0, a1, a2, 2
aes32esmi a0, a1, a2, 2

14
gas/testsuite/gas/riscv/zkne-64.d Normal file
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@ -0,0 +1,14 @@
#as: -march=rv64i_zkne
#source: zkne-64.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+aes64es[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64esm[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+aes64ks1i[ ]+a0,a1,0x4
[ ]+.*:[ ]+.*[ ]+aes64ks2[ ]+a0,a1,a2

5
gas/testsuite/gas/riscv/zkne-64.s Normal file
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@ -0,0 +1,5 @@
target:
aes64es a0, a1, a2
aes64esm a0, a1, a2
aes64ks1i a0, a1, 4
aes64ks2 a0, a1, a2

20
gas/testsuite/gas/riscv/zknh-32.d Normal file
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@ -0,0 +1,20 @@
#as: -march=rv32i_zknh
#source: zknh-32.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig0h[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig0l[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig1h[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sig1l[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sum0r[ ]+a0,a1,a2
[ ]+.*:[ ]+.*[ ]+sha512sum1r[ ]+a0,a1,a2

11
gas/testsuite/gas/riscv/zknh-32.s Normal file
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@ -0,0 +1,11 @@
target:
sha256sig0 a0, a0
sha256sig1 a0, a0
sha256sum0 a0, a0
sha256sum1 a0, a0
sha512sig0h a0, a1, a2
sha512sig0l a0, a1, a2
sha512sig1h a0, a1, a2
sha512sig1l a0, a1, a2
sha512sum0r a0, a1, a2
sha512sum1r a0, a1, a2

18
gas/testsuite/gas/riscv/zknh-64.d Normal file
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@ -0,0 +1,18 @@
#as: -march=rv64i_zknh
#source: zknh-64.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sha256sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha256sum1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sig1[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sum0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sha512sum1[ ]+a0,a0

9
gas/testsuite/gas/riscv/zknh-64.s Normal file
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@ -0,0 +1,9 @@
target:
sha256sig0 a0, a0
sha256sig1 a0, a0
sha256sum0 a0, a0
sha256sum1 a0, a0
sha512sig0 a0, a0
sha512sig1 a0, a0
sha512sum0 a0, a0
sha512sum1 a0, a0

12
gas/testsuite/gas/riscv/zksed-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zksed
#source: zksed.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2

12
gas/testsuite/gas/riscv/zksed-64.d Normal file
View File

@ -0,0 +1,12 @@
#as: -march=rv64i_zksed
#source: zksed.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sm4ed[ ]+a0,a1,a2,0x2
[ ]+.*:[ ]+.*[ ]+sm4ks[ ]+a0,a1,a2,0x2

3
gas/testsuite/gas/riscv/zksed.s Normal file
View File

@ -0,0 +1,3 @@
target:
sm4ed a0, a1, a2, 2
sm4ks a0, a1, a2, 2

12
gas/testsuite/gas/riscv/zksh-32.d Normal file
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@ -0,0 +1,12 @@
#as: -march=rv32i_zksh
#source: zksh.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0

12
gas/testsuite/gas/riscv/zksh-64.d Normal file
View File

@ -0,0 +1,12 @@
#as: -march=rv64i_zksh
#source: zksh.s
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+.*:[ ]+.*[ ]+sm3p0[ ]+a0,a0
[ ]+.*:[ ]+.*[ ]+sm3p1[ ]+a0,a0

3
gas/testsuite/gas/riscv/zksh.s Normal file
View File

@ -0,0 +1,3 @@
target:
sm3p0 a0, a0
sm3p1 a0, a0