mirrors/binutils-gdb
1
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-25 11:04:18 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add Cirrus Maverick support to arm simulator

Browse Source
This commit is contained in:
Nick Clifton 2003-03-20 12:25:07 +00:00
parent c25cfdf8a2
commit f603c8fe44
12 changed files with 1486 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/gdb/ChangeLog
View File

@ -1,3 +1,8 @@
2003-03-20 Nick Clifton <nickc@redhat.com>
* sim-arm.h (sim_arm_regs): Add Maverick co-processor
registers.
2003-02-27 Andrew Cagney <cagney@redhat.com>
* remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename

21
include/gdb/sim-arm.h
View File

@ -1,6 +1,6 @@
/* This file defines the interface between the Arm simulator and GDB.
Copyright 2002 Free Software Foundation, Inc.
Copyright 2002, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
@ -55,7 +55,24 @@ enum sim_arm_regs
SIM_ARM_FP6_REGNUM,
SIM_ARM_FP7_REGNUM,
SIM_ARM_FPS_REGNUM,
SIM_ARM_PS_REGNUM
SIM_ARM_PS_REGNUM,
SIM_ARM_MAVERIC_COP0R0_REGNUM,
SIM_ARM_MAVERIC_COP0R1_REGNUM,
SIM_ARM_MAVERIC_COP0R2_REGNUM,
SIM_ARM_MAVERIC_COP0R3_REGNUM,
SIM_ARM_MAVERIC_COP0R4_REGNUM,
SIM_ARM_MAVERIC_COP0R5_REGNUM,
SIM_ARM_MAVERIC_COP0R6_REGNUM,
SIM_ARM_MAVERIC_COP0R7_REGNUM,
SIM_ARM_MAVERIC_COP0R8_REGNUM,
SIM_ARM_MAVERIC_COP0R9_REGNUM,
SIM_ARM_MAVERIC_COP0R10_REGNUM,
SIM_ARM_MAVERIC_COP0R11_REGNUM,
SIM_ARM_MAVERIC_COP0R12_REGNUM,
SIM_ARM_MAVERIC_COP0R13_REGNUM,
SIM_ARM_MAVERIC_COP0R14_REGNUM,
SIM_ARM_MAVERIC_COP0R15_REGNUM,
SIM_ARM_MAVERIC_DSPSC_REGNUM
};
#ifdef __cplusplus

24
sim/arm/ChangeLog
View File

@ -1,3 +1,27 @@
2003-02-10 Nick Clifton <nickc@redhat.com>
* Contribute support for Cirrus Maverick ARM co-processor,
written by Aldy Hernandez <aldyh@redhat.com> and
Andrew Cagney <cagney@redhat.com>:
* maverick.c: New file: Support for Maverick floating point
co-processor.
* Makefile.in: Add maverick.o target.
* configure.in (COPRO): Add maverick.o.
* configure: Regenerate.
* armcopro.c (ARMul_CoProInit): Only initialise co-processors
available on target processor. Add code to initialse Maverick
co-processor support code.
* armdefs.h (ARMul_state): Add is_ep9312 field.
(ARM_ep9312_Prop): Define.
* armemu.h: Add prototypes for Maverick co-processor
functions.
* arminit.c (ARMul_SelectProcessor): Initialise the
co-processor support once the chip has been selected.
* wrapper.c: Add support for Maverick co-processor.
(init): Do not call ARMul_CoProInit. Delays this until the
chip has been selected.
2003-03-02 Nick Clifton <nickc@redhat.com>
* armos.c (SWIWrite0): Catch big-endian bug when printing

1
sim/arm/Makefile.in
View File

@ -31,6 +31,7 @@ SIM_OBJS = armemu26.o armemu32.o arminit.o armos.o armsupp.o \
armos.o: armos.c armdefs.h armos.h armfpe.h
armcopro.o: armcopro.c armdefs.h
maverick.o: maverick.c armdefs.h
armemu26.o: armemu.c armdefs.h armemu.h
$(CC) -c $(srcdir)/armemu.c -o armemu26.o $(ALL_CFLAGS)

62
sim/arm/armcopro.c
View File

@ -1322,34 +1322,48 @@ ARMul_CoProInit (ARMul_State * state)
/* Install CoPro Instruction handlers here.
The format is:
ARMul_CoProAttach (state, CP Number,
Init routine, Exit routine
LDC routine, STC routine,
MRC routine, MCR routine,
CDP routine,
Read Reg routine, Write Reg routine). */
ARMul_CoProAttach (state, 4, NULL, NULL,
ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
LDC routine, STC routine, MRC routine, MCR routine,
CDP routine, Read Reg routine, Write Reg routine). */
if (state->is_ep9312)
{
ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4,
DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL);
ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5,
DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL);
ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL,
DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL);
}
else
{
ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC,
ValMRC, ValMCR, ValCDP, NULL, NULL);
ARMul_CoProAttach (state, 5, NULL, NULL,
NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL,
ValMRC, ValMCR, IntCDP, NULL, NULL);
}
ARMul_CoProAttach (state, 15, MMUInit, NULL,
NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
if (state->is_XScale)
{
ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
XScale_cp13_write_reg);
ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
XScale_cp13_write_reg);
ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
XScale_cp14_write_reg);
ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
XScale_cp14_write_reg);
ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
}
else
{
ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
}
/* No handlers below here. */

2
sim/arm/armdefs.h
View File

@ -135,6 +135,7 @@ struct ARMul_State
unsigned is_v5; /* Are we emulating a v5 architecture ? */
unsigned is_v5e; /* Are we emulating a v5e architecture ? */
unsigned is_XScale; /* Are we emulating an XScale architecture ? */
unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
unsigned verbose; /* Print various messages like the banner */
};
@ -162,6 +163,7 @@ struct ARMul_State
#define ARM_v5_Prop 0x80
#define ARM_v5e_Prop 0x100
#define ARM_XScale_Prop 0x200
#define ARM_ep9312_Prop 0x400
/***************************************************************************\
* Macros to extract instruction fields *

13
sim/arm/armemu.h
View File

@ -530,3 +530,16 @@ extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, A
extern void ARMul_CoProDetach (ARMul_State *, unsigned);
extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);

5
sim/arm/arminit.c
View File

@ -157,6 +157,11 @@ ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
/* Only initialse the coprocessor support once we
know what kind of chip we are dealing with. */
ARMul_CoProInit (state);
}
/***************************************************************************\

3
sim/arm/configure vendored
View File

@ -3534,7 +3534,8 @@ fi
done
COPRO=armcopro.o
COPRO="armcopro.o maverick.o"

3
sim/arm/configure.in
View File

@ -7,7 +7,8 @@ SIM_AC_COMMON
AC_CHECK_HEADERS(unistd.h)
COPRO=armcopro.o
COPRO="armcopro.o maverick.o"
AC_SUBST(COPRO)
SIM_AC_OUTPUT

1291
sim/arm/maverick.c Normal file
View File

File diff suppressed because it is too large Load Diff

85
sim/arm/wrapper.c
View File

@ -59,6 +59,38 @@ static int big_endian;
int stop_simulator;
/* Cirrus DSP registers.
We need to define these registers outside of maverick.c because
maverick.c might not be linked in unless --target=arm9e-* in which
case wrapper.c will not compile because it tries to access Cirrus
registers. This should all go away once we get the Cirrus and ARM
Coprocessor to coexist in armcopro.c-- aldyh. */
struct maverick_regs
{
union
{
int i;
float f;
} upper;
union
{
int i;
float f;
} lower;
};
union maverick_acc_regs
{
long double ld; /* Acc registers are 72-bits. */
};
struct maverick_regs DSPregs[16];
union maverick_acc_regs DSPacc[4];
ARMword DSPsc;
static void
init ()
{
@ -71,7 +103,6 @@ init ()
state->bigendSig = (big_endian ? HIGH : LOW);
ARMul_MemoryInit (state, mem_size);
ARMul_OSInit (state);
ARMul_CoProInit (state);
state->verbose = verbosity;
done = 1;
}
@ -236,6 +267,10 @@ sim_create_inferior (sd, abfd, argv, env)
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
break;
case bfd_mach_arm_ep9312:
ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
break;
case bfd_mach_arm_5:
if (bfd_family_coff (abfd))
{
@ -422,6 +457,30 @@ sim_store_register (sd, rn, memory, length)
ARMul_CPSRAltered (state);
break;
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
memory, sizeof (struct maverick_regs));
return sizeof (struct maverick_regs);
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
memcpy (&DSPsc, memory, sizeof DSPsc);
return sizeof DSPsc;
default:
return 0;
}
@ -477,6 +536,30 @@ sim_fetch_register (sd, rn, memory, length)
regval = ARMul_GetCPSR (state);
break;
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
sizeof (struct maverick_regs));
return sizeof (struct maverick_regs);
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
memcpy (memory, & DSPsc, sizeof DSPsc);
return sizeof DSPsc;
default:
return 0;
}