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[gas/ChangeLog]
* config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400, -m7410, -m7450 and -m7455 options. [gas/testsuite/ChangeLog] * gas/ppc/altivec.s: New test for AltiVec. * gas/ppc/altivec.d: New file. * gas/ppc/ppc.exp: Test altivec.s [include/opcode/ChangeLog] * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. [opcodes/ChangeLog] * ppc-opc.c (STRM): New AltiVec operand. (XDSS): New AltiVec instruction form. (mtvscr): Correct operand list. (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
This commit is contained in:
Matthew Green
parent
973ffd6335
commit
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@ -1,3 +1,8 @@
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2001-10-17 matthew green <mrg@redhat.com>
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* config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400,
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-m7410, -m7450 and -m7455 options.
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2001-10-17 Alan Modra <amodra@bigpond.net.au>
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* config/tc-ppc.c (PPC_HA, PPC_HIGHERA, PPC_HIGHESTA): Simplify.
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@ -1028,10 +1028,13 @@ PowerPC options:\n\
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-mppc, -mppc32, -m603, -m604\n\
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generate code for Motorola PowerPC 603/604\n\
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-m403, -m405 generate code for Motorola PowerPC 403/405\n\
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-m7400, -m7410, -m7450, -m7455\n\
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generate code For Motorola PowerPC 7400/7410/7450/7455\n\
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-mppc64, -m620 generate code for Motorola PowerPC 620\n\
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-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
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-mbooke64 generate code for 64-bit Motorola BookE\n\
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-mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\
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-mbooke64 generate code for 64-bit Motorola BookE\n\
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-mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\
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-maltivec generate code for AltiVec\n\
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-mcom generate code Power/PowerPC common instructions\n\
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-many generate code for any architecture (PWR/PWRX/PPC)\n\
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-mregnames Allow symbolic names for registers\n\
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@ -1,3 +1,9 @@
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2001-10-17 matthew green <mrg@redhat.com>
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* gas/ppc/altivec.s: New test for AltiVec.
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* gas/ppc/altivec.d: New file.
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* gas/ppc/ppc.exp: Test altivec.s
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2001-10-16 Hans-Peter Nilsson <hp@bitrange.com>
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* gas/sh/err-le.s, gas/sh/err-be.s: New tests.
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16
gas/testsuite/gas/ppc/altivec.d
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16
gas/testsuite/gas/ppc/altivec.d
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@ -0,0 +1,16 @@
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#as: -m601 -maltivec
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#objdump: -Dr
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#name: AltiVec tests
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.*: +file format elf32-powerpc
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Disassembly of section \.text:
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00000000 <start>:
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0: 7c 60 06 6c dss 3
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4: 7e 40 06 6c dssall 2
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8: 7c 25 22 ac dst r5,r4,1
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c: 7e 08 3a ac dstt r8,r7,0
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10: 7c 65 32 ec dstst r5,r6,3
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14: 7e 44 2a ec dststt r4,r5,2
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Disassembly of section \.data:
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10
gas/testsuite/gas/ppc/altivec.s
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10
gas/testsuite/gas/ppc/altivec.s
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@ -0,0 +1,10 @@
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# PowerPC AltiVec tests
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#as: -m601 -maltivec
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.section ".text"
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start:
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dss 3
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dssall 2
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dst 5,4,1
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dstt 8,7,0
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dstst 5,6,3
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dststt 4,5,2
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@ -27,4 +27,5 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
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if { [istarget powerpc*-*-*] } then {
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run_dump_test "simpshft"
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run_dump_test "booke"
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run_dump_test "altivec"
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}
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@ -1,3 +1,7 @@
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2001-10-17 matthew green <mrg@redhat.com>
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* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
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2001-10-12 matthew green <mrg@redhat.com>
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* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
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@ -98,7 +98,7 @@ extern const int powerpc_num_opcodes;
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#define PPC_OPCODE_BOOKE (04000)
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/* Opcode is only supported by 64-bit Motorola BookE processor. */
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#define PPC_OPCODE_BOOKE64 (001000)
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#define PPC_OPCODE_BOOKE64 (010000)
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@ -1,3 +1,10 @@
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2001-10-17 matthew green <mrg@redhat.com>
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* ppc-opc.c (STRM): New AltiVec operand.
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(XDSS): New AltiVec instruction form.
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(mtvscr): Correct operand list.
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(dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
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2001-10-17 Alan Modra <amodra@bigpond.net.au>
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* po/POTFILES.in: Regenerate.
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@ -403,8 +403,13 @@ const struct powerpc_operand powerpc_operands[] =
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#define SR SPRG + 1
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{ 4, 16, 0, 0, 0 },
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/* The STRM field in an X AltiVec form instruction. */
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#define STRM SR + 1
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#define STRM_MASK (0x3 << 21)
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{ 2, 21, 0, 0, 0 },
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/* The SV field in a POWER SC form instruction. */
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#define SV SR + 1
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#define SV STRM + 1
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{ 14, 2, 0, 0, 0 },
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/* The TBR field in an XFX form instruction. This is like the SPR
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@ -1289,6 +1294,10 @@ extract_tbr (insn, invalid)
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/* An X form sync instruction with everything filled in except the LS field. */
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#define XSYNC_MASK (0xff9fffff)
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/* An X form AltiVec dss instruction. */
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#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
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#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
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/* An XFL form instruction. */
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#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
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#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
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@ -1584,7 +1593,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
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@ -2972,10 +2981,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
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{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
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{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
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{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
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{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
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{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
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{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
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{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
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{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
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@ -3366,6 +3381,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
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{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
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{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } },
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{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
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{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
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{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
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