mirrors/binutils-gdb
1
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-23 18:14:13 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

RISC-V: Fix riscv gas/ld testsuites failures for big endian.

Browse Source 
Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct
linker script rather than set elf[32|64]lriscv directly.

gas/
    * testsuite/gas/riscv/li32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/gas/riscv/li64.d: Likewise.
    * testsuite/gas/riscv/lla32.d: Likewise.
    * testsuite/gas/riscv/lla64.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
    * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
    * testsuite/gas/riscv/march-ok-two-nse.d: Likewise.

ld/
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
    riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
    * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
    riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
    * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui.d: Likewise.
    * testsuite/ld-riscv-elf/call-relax.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
    * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/ld-riscv-elf/weakref64.d: Likewise.
This commit is contained in:
Marcus Comstedt 2021-01-05 22:50:39 +01:00 committed by Nelson Chu
parent fbc09e7af7
commit f36ce378b4
26 changed files with 85 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
gas/ChangeLog
View File

@ -1,3 +1,18 @@
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* testsuite/gas/riscv/li32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/gas/riscv/li64.d: Likewise.
* testsuite/gas/riscv/lla32.d: Likewise.
* testsuite/gas/riscv/lla64.d: Likewise.
* testsuite/gas/riscv/march-ok-g2.d: Likewise.
* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
* testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
2021-01-06 Marcus Comstedt <marcus@mc.pp.se> 2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and

2
gas/testsuite/gas/riscv/li32.d
View File

@ -1,7 +1,7 @@
#as: -march=rv32ic -mabi=ilp32 #as: -march=rv32ic -mabi=ilp32
#objdump: -dr #objdump: -dr
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv
Disassembly of section .text: Disassembly of section .text:

2
gas/testsuite/gas/riscv/li64.d
View File

@ -1,7 +1,7 @@
#as: -march=rv64ic -mabi=lp64 #as: -march=rv64ic -mabi=lp64
#objdump: -dr #objdump: -dr
.*: file format elf64-littleriscv .*: file format elf64-(little|big)riscv
Disassembly of section .text: Disassembly of section .text:

2
gas/testsuite/gas/riscv/lla32.d
View File

@ -1,7 +1,7 @@
#as: -march=rv32i -mabi=ilp32 #as: -march=rv32i -mabi=ilp32
#objdump: -dr #objdump: -dr
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv
Disassembly of section .text: Disassembly of section .text:

2
gas/testsuite/gas/riscv/lla64.d
View File

@ -1,7 +1,7 @@
#as: -march=rv64i -mabi=lp64 #as: -march=rv64i -mabi=lp64
#objdump: -dr #objdump: -dr
.*: file format elf64-littleriscv .*: file format elf64-(little|big)riscv
Disassembly of section .text: Disassembly of section .text:

2
gas/testsuite/gas/riscv/march-ok-g2.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-g2_p1.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-g2p0.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-i2p0.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-nse-with-version.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

2
gas/testsuite/gas/riscv/march-ok-two-nse.d
View File

@ -2,4 +2,4 @@
#objdump: -dr #objdump: -dr
#source: empty.s #source: empty.s
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv

19
ld/ChangeLog
View File

@ -1,3 +1,22 @@
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
* testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
* testsuite/ld-riscv-elf/c-lui.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
* testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
* testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 Marcus Comstedt <marcus@mc.pp.se> 2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*, * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,

2
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
View File

@ -1,7 +1,7 @@
#source: attr-merge-arch-01a.s #source: attr-merge-arch-01a.s
#source: attr-merge-arch-01b.s #source: attr-merge-arch-01b.s
#as: #as:
#ld: -r -melf32lriscv #ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A #readelf: -A
Attribute Section: riscv Attribute Section: riscv

2
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
View File

@ -1,7 +1,7 @@
#source: attr-merge-arch-02a.s #source: attr-merge-arch-02a.s
#source: attr-merge-arch-02b.s #source: attr-merge-arch-02b.s
#as: #as:
#ld: -r -melf32lriscv #ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A #readelf: -A
Attribute Section: riscv Attribute Section: riscv

2
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
View File

@ -1,7 +1,7 @@
#source: attr-merge-arch-03a.s #source: attr-merge-arch-03a.s
#source: attr-merge-arch-03b.s #source: attr-merge-arch-03b.s
#as: #as:
#ld: -r -melf32lriscv #ld: -r -m[riscv_choose_ilp32_emul]
#readelf: -A #readelf: -A
Attribute Section: riscv Attribute Section: riscv

2
ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
View File

@ -1,7 +1,7 @@
#source: attr-merge-arch-failed-01a.s #source: attr-merge-arch-failed-01a.s
#source: attr-merge-arch-failed-01b.s #source: attr-merge-arch-failed-01b.s
#as: -march-attr #as: -march-attr
#ld: -r -melf32lriscv #ld: -r -m[riscv_choose_ilp32_emul]
#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
#readelf: -A #readelf: -A

2
ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
View File

@ -3,7 +3,7 @@
#source: attr-merge-arch-failed-02c.s #source: attr-merge-arch-failed-02c.s
#source: attr-merge-arch-failed-02d.s #source: attr-merge-arch-failed-02d.s
#as: -march-attr #as: -march-attr
#ld: -r -melf32lriscv #ld: -r -m[riscv_choose_ilp32_emul]
#warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0
#warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0
#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0

2
ld/testsuite/ld-riscv-elf/c-lui-2.d
View File

@ -1,7 +1,7 @@
#name: c.lui to c.li relaxation #name: c.lui to c.li relaxation
#source: c-lui-2.s #source: c-lui-2.s
#as: -march=rv32ic #as: -march=rv32ic
#ld: -melf32lriscv -Tc-lui-2.ld #ld: -m[riscv_choose_ilp32_emul] -Tc-lui-2.ld
#objdump: -d -M no-aliases,numeric #objdump: -d -M no-aliases,numeric
.*: file format .* .*: file format .*

2
ld/testsuite/ld-riscv-elf/c-lui.d
View File

@ -1,7 +1,7 @@
#name: lui to c.lui relaxation #name: lui to c.lui relaxation
#source: c-lui.s #source: c-lui.s
#as: -march=rv32ic #as: -march=rv32ic
#ld: -melf32lriscv #ld: -m[riscv_choose_ilp32_emul]
#objdump: -d -M no-aliases,numeric #objdump: -d -M no-aliases,numeric
.*: file format .* .*: file format .*

2
ld/testsuite/ld-riscv-elf/call-relax.d
View File

@ -4,6 +4,6 @@
#source: call-relax-2.s #source: call-relax-2.s
#source: call-relax-3.s #source: call-relax-3.s
#as: -march=rv32ic -mno-arch-attr #as: -march=rv32ic -mno-arch-attr
#ld: -melf32lriscv #ld: -m[riscv_choose_ilp32_emul]
#objdump: -d #objdump: -d
#pass #pass

39
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
View File

@ -19,6 +19,24 @@
# MA 02110-1301, USA. # MA 02110-1301, USA.
# #
proc riscv_choose_ilp32_emul {} {
if { [istarget "riscvbe-*"] \
|| [istarget "riscv32be-*"] \
|| [istarget "riscv64be-*"] } {
return "elf32briscv"
}
return "elf32lriscv"
}
proc riscv_choose_lp64_emul {} {
if { [istarget "riscvbe-*"] \
|| [istarget "riscv32be-*"] \
|| [istarget "riscv64be-*"] } {
return "elf64briscv"
}
return "elf64lriscv"
}
# target: rv32 or rv64. # target: rv32 or rv64.
# output: Which output you want? (exe, pie, .so) # output: Which output you want? (exe, pie, .so)
proc run_dump_test_ifunc { name target output} { proc run_dump_test_ifunc { name target output} {
@ -42,11 +60,11 @@ proc run_dump_test_ifunc { name target output} {
switch -- $target { switch -- $target {
rv32 { rv32 {
set asflags "$asflags -march=rv32i -mabi=ilp32" set asflags "$asflags -march=rv32i -mabi=ilp32"
set ldflags "$ldflags -melf32lriscv" set ldflags "$ldflags -m[riscv_choose_ilp32_emul]"
} }
rv64 { rv64 {
set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1" set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1"
set ldflags "$ldflags -melf64lriscv" set ldflags "$ldflags -m[riscv_choose_lp64_emul]"
} }
} }
@ -89,21 +107,20 @@ if [istarget "riscv*-*-*"] {
run_dump_test "attr-merge-priv-spec-failed-04" run_dump_test "attr-merge-priv-spec-failed-04"
run_dump_test "attr-merge-priv-spec-failed-05" run_dump_test "attr-merge-priv-spec-failed-05"
run_dump_test "attr-merge-priv-spec-failed-06" run_dump_test "attr-merge-priv-spec-failed-06"
run_ld_link_tests { run_ld_link_tests [list \
{ "Weak reference 32" "-T weakref.ld -melf32lriscv" "" [list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
"-march=rv32i -mabi=ilp32" {weakref32.s} "-march=rv32i -mabi=ilp32" {weakref32.s} \
{{objdump -d weakref32.d}} "weakref32"} {{objdump -d weakref32.d}} "weakref32"] \
{ "Weak reference 64" "-T weakref.ld -melf64lriscv" "" [list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \
"-march=rv64i -mabi=lp64" {weakref64.s} "-march=rv64i -mabi=lp64" {weakref64.s} \
{{objdump -d weakref64.d}} "weakref64"} {{objdump -d weakref64.d}} "weakref64"]]
}
# The following tests require shared library support. # The following tests require shared library support.
if ![check_shared_lib_support] { if ![check_shared_lib_support] {
return return
} }
set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv } set abis [list rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul]]
foreach { arch abi emul } $abis { foreach { arch abi emul } $abis {
# This checks whether our linker scripts handle __global_pointer$ # This checks whether our linker scripts handle __global_pointer$
# correctly. It should be defined in executables and PIE, but not # correctly. It should be defined in executables and PIE, but not

2
ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d
View File

@ -1,5 +1,5 @@
#name: %pcrel_lo overflow with an addend #name: %pcrel_lo overflow with an addend
#source: pcrel-lo-addend-2.s #source: pcrel-lo-addend-2.s
#as: -march=rv32ic #as: -march=rv32ic
#ld: -melf32lriscv --no-relax #ld: -m[riscv_choose_ilp32_emul] --no-relax
#error: .*dangerous relocation: %pcrel_lo overflow with an addend #error: .*dangerous relocation: %pcrel_lo overflow with an addend

2
ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
View File

@ -1,5 +1,5 @@
#name: %pcrel_lo section symbol with an addend #name: %pcrel_lo section symbol with an addend
#source: pcrel-lo-addend.s #source: pcrel-lo-addend.s
#as: -march=rv32ic #as: -march=rv32ic
#ld: -melf32lriscv #ld: -m[riscv_choose_ilp32_emul]
#error: .*dangerous relocation: %pcrel_lo section symbol with an addend #error: .*dangerous relocation: %pcrel_lo section symbol with an addend

2
ld/testsuite/ld-riscv-elf/weakref32.d
View File

@ -1,5 +1,5 @@
.*: file format elf32-littleriscv .*: file format elf32-(little|big)riscv
Disassembly of section \.text: Disassembly of section \.text:

2
ld/testsuite/ld-riscv-elf/weakref64.d
View File

@ -1,5 +1,5 @@
.*: file format elf64-littleriscv .*: file format elf64-(little|big)riscv
Disassembly of section \.text: Disassembly of section \.text: