mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-26 11:33:45 +08:00
2004-02-09 Andrew Cagney <cagney@redhat.com>
* Makefile.in (mips-tdep.o): Update dependencies. * mips-tdep.c: Include "frame-unwind.h", "frame-base.h" and "trad-frame.h". (mips_unwind_pc): Return the pseudo PC register. (mips_unwind_dummy_id): New function. (mips16_fetch_instruction): New function. (mips32_fetch_instruction): New function. (struct mips_frame_cache): Define. (mips_mdebug_frame_cache): New function. (mips_mdebug_frame_this_id): New function. (mips_mdebug_frame_prev_register): New function. (mips_mdebug_frame_unwind): Define. (mips_mdebug_frame_sniffer): New function. (mips_mdebug_frame_base_address): New function. (mips_mdebug_frame_base): Define. (mips_mdebug_frame_base_sniffer): New function. (mips_gdbarch_init): Append unwind and base sniffers. Set unwind_dummy_id.
This commit is contained in:
Andrew Cagney
parent
6764ddad5a
commit
edfae06341
@ -1,3 +1,24 @@
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2004-02-09 Andrew Cagney <cagney@redhat.com>
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* Makefile.in (mips-tdep.o): Update dependencies.
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* mips-tdep.c: Include "frame-unwind.h", "frame-base.h" and
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"trad-frame.h".
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(mips_unwind_pc): Return the pseudo PC register.
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(mips_unwind_dummy_id): New function.
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(mips16_fetch_instruction): New function.
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(mips32_fetch_instruction): New function.
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(struct mips_frame_cache): Define.
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(mips_mdebug_frame_cache): New function.
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(mips_mdebug_frame_this_id): New function.
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(mips_mdebug_frame_prev_register): New function.
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(mips_mdebug_frame_unwind): Define.
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(mips_mdebug_frame_sniffer): New function.
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(mips_mdebug_frame_base_address): New function.
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(mips_mdebug_frame_base): Define.
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(mips_mdebug_frame_base_sniffer): New function.
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(mips_gdbarch_init): Append unwind and base sniffers. Set
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unwind_dummy_id.
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2004-02-08 Andrew Cagney <cagney@redhat.com>
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* frame.c: Print both the register number and name.
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@ -2082,10 +2082,12 @@ mipsread.o: mipsread.c $(defs_h) $(gdb_string_h) $(bfd_h) $(symtab_h) \
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$(libecoff_h) $(elf_common_h) $(elf_mips_h)
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mips-tdep.o: mips-tdep.c $(defs_h) $(gdb_string_h) $(gdb_assert_h) \
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$(frame_h) $(inferior_h) $(symtab_h) $(value_h) $(gdbcmd_h) \
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$(language_h) $(gdbcore_h) $(symfile_h) $(objfiles_h) $(gdbtypes_h) \
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$(target_h) $(arch_utils_h) $(regcache_h) $(osabi_h) $(mips_tdep_h) \
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$(block_h) $(reggroups_h) $(opcode_mips_h) $(elf_mips_h) \
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$(elf_bfd_h) $(symcat_h) $(sim_regno_h) $(dis_asm_h)
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$(language_h) $(gdbcore_h) $(symfile_h) $(objfiles_h) \
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$(gdbtypes_h) $(target_h) $(arch_utils_h) $(regcache_h) \
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$(osabi_h) $(mips_tdep_h) $(block_h) $(reggroups_h) \
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$(opcode_mips_h) $(elf_mips_h) $(elf_bfd_h) $(symcat_h) \
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$(sim_regno_h) $(dis_asm_h) $(frame_unwind_h) $(frame_base_h) \
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$(trad_frame_h)
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mipsv4-nat.o: mipsv4-nat.c $(defs_h) $(inferior_h) $(gdbcore_h) $(target_h) \
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$(regcache_h) $(gregset_h)
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mn10300-tdep.o: mn10300-tdep.c $(defs_h) $(frame_h) $(inferior_h) \
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299
gdb/mips-tdep.c
299
gdb/mips-tdep.c
@ -50,6 +50,9 @@
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#include "symcat.h"
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#include "sim-regno.h"
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#include "dis-asm.h"
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#include "frame-unwind.h"
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#include "frame-base.h"
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#include "trad-frame.h"
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static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
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static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
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@ -813,7 +816,20 @@ mips_read_pc (ptid_t ptid)
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static CORE_ADDR
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mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
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{
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return frame_unwind_register_signed (next_frame, mips_regnum (gdbarch)->pc);
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return frame_unwind_register_signed (next_frame,
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NUM_REGS + mips_regnum (gdbarch)->pc);
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}
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/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
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dummy frame. The frame ID's base needs to match the TOS value
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saved by save_dummy_frame_tos(), and the PC match the dummy frame's
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breakpoint. */
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static struct frame_id
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mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
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{
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return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM),
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frame_pc_unwind (next_frame));
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}
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static void
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@ -942,6 +958,34 @@ mips_fetch_instruction (CORE_ADDR addr)
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return extract_unsigned_integer (buf, instlen);
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}
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static ULONGEST
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mips16_fetch_instruction (CORE_ADDR addr)
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{
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char buf[MIPS_INSTLEN];
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int instlen;
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int status;
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instlen = MIPS16_INSTLEN;
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addr = unmake_mips16_addr (addr);
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status = read_memory_nobpt (addr, buf, instlen);
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if (status)
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memory_error (status, addr);
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return extract_unsigned_integer (buf, instlen);
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}
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static ULONGEST
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mips32_fetch_instruction (CORE_ADDR addr)
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{
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char buf[MIPS_INSTLEN];
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int instlen;
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int status;
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instlen = MIPS_INSTLEN;
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status = read_memory_nobpt (addr, buf, instlen);
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if (status)
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memory_error (status, addr);
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return extract_unsigned_integer (buf, instlen);
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}
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/* These the fields of 32 bit mips instructions */
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#define mips32_op(x) (x >> 26)
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@ -1656,6 +1700,254 @@ mips_find_saved_regs (struct frame_info *fci)
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set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
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}
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struct mips_frame_cache
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{
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CORE_ADDR base;
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struct trad_frame_saved_reg *saved_regs;
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};
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static struct mips_frame_cache *
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mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache)
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{
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mips_extra_func_info_t proc_desc;
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struct mips_frame_cache *cache;
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struct gdbarch *gdbarch = get_frame_arch (next_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* r0 bit means kernel trap */
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int kernel_trap;
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/* What registers have been saved? Bitmasks. */
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unsigned long gen_mask, float_mask;
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if ((*this_cache) != NULL)
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return (*this_cache);
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cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
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(*this_cache) = cache;
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cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
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/* Get the mdebug proc descriptor. */
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proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
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if (proc_desc == NULL)
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/* I'm not sure how/whether this can happen. Normally when we
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can't find a proc_desc, we "synthesize" one using
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heuristic_proc_desc and set the saved_regs right away. */
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return cache;
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/* Extract the frame's base. */
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cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
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+ PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
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float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
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/* In any frame other than the innermost or a frame interrupted by a
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signal, we assume that all registers have been saved. This
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assumes that all register saves in a function happen before the
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first function call. */
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if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
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/* Not sure exactly what kernel_trap means, but if it means the
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kernel saves the registers without a prologue doing it, we
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better not examine the prologue to see whether registers
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have been saved yet. */
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&& !kernel_trap)
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{
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/* We need to figure out whether the registers that the
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proc_desc claims are saved have been saved yet. */
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CORE_ADDR addr;
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/* Bitmasks; set if we have found a save for the register. */
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unsigned long gen_save_found = 0;
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unsigned long float_save_found = 0;
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int mips16;
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/* If the address is odd, assume this is MIPS16 code. */
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addr = PROC_LOW_ADDR (proc_desc);
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mips16 = pc_is_mips16 (addr);
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/* Scan through this function's instructions preceding the
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current PC, and look for those that save registers. */
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while (addr < frame_pc_unwind (next_frame))
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{
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if (mips16)
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{
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mips16_decode_reg_save (mips16_fetch_instruction (addr),
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&gen_save_found);
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addr += MIPS16_INSTLEN;
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}
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else
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{
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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}
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/* Fill in the offsets for the registers which gen_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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int ireg;
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for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
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if (gen_mask & 0x80000000)
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{
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cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
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reg_position -= mips_saved_regsize (tdep);
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}
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
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order of that normally used by gcc. Therefore, we have to fetch
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the first instruction of the function, and if it's an entry
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instruction that saves $s0 or $s1, correct their saved addresses. */
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if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
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{
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ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
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if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
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/* entry */
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{
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int reg;
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int sreg_count = (inst >> 6) & 3;
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/* Check if the ra register was pushed on the stack. */
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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if (inst & 0x20)
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reg_position -= mips_saved_regsize (tdep);
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/* Check if the s0 and s1 registers were pushed on the
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stack. */
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/* NOTE: cagney/2004-02-08: Huh? This is doing no such
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check. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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cache->saved_regs[NUM_REGS + reg].addr = reg_position;
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reg_position -= mips_saved_regsize (tdep);
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}
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}
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}
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/* Fill in the offsets for the registers which float_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_FREG_OFFSET (proc_desc));
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int ireg;
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/* Fill in the offsets for the float registers which float_mask
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says were saved. */
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for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
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if (float_mask & 0x80000000)
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{
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if (mips_saved_regsize (tdep) == 4
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&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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/* On a big endian 32 bit ABI, floating point registers
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are paired to form doubles such that the most
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significant part is in $f[N+1] and the least
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significant in $f[N] vis: $f[N+1] ||| $f[N]. The
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registers are also spilled as a pair and stored as a
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double.
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When little-endian the least significant part is
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stored first leading to the memory order $f[N] and
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then $f[N+1].
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Unfortunately, when big-endian the most significant
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part of the double is stored first, and the least
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significant is stored second. This leads to the
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registers being ordered in memory as firt $f[N+1] and
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then $f[N].
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For the big-endian case make certain that the
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addresses point at the correct (swapped) locations
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$f[N] and $f[N+1] pair (keep in mind that
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reg_position is decremented each time through the
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loop). */
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if ((ireg & 1))
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position - mips_saved_regsize (tdep);
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position + mips_saved_regsize (tdep);
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}
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position;
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reg_position -= mips_saved_regsize (tdep);
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}
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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/* SP_REGNUM, contains the value and not the address. */
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trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base);
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return (*this_cache);
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}
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static void
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mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache,
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struct frame_id *this_id)
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{
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struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
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this_cache);
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(*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
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}
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static void
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mips_mdebug_frame_prev_register (struct frame_info *next_frame,
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void **this_cache,
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int regnum, int *optimizedp,
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enum lval_type *lvalp, CORE_ADDR *addrp,
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int *realnump, void *valuep)
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{
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struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
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this_cache);
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trad_frame_prev_register (next_frame, info->saved_regs, regnum,
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optimizedp, lvalp, addrp, realnump, valuep);
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}
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static const struct frame_unwind mips_mdebug_frame_unwind =
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{
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NORMAL_FRAME,
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mips_mdebug_frame_this_id,
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mips_mdebug_frame_prev_register
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};
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static const struct frame_unwind *
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mips_mdebug_frame_sniffer (struct frame_info *next_frame)
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{
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return &mips_mdebug_frame_unwind;
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}
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static CORE_ADDR
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mips_mdebug_frame_base_address (struct frame_info *next_frame,
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void **this_cache)
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{
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struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
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this_cache);
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return info->base;
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}
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static const struct frame_base mips_mdebug_frame_base = {
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&mips_mdebug_frame_unwind,
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mips_mdebug_frame_base_address,
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mips_mdebug_frame_base_address,
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mips_mdebug_frame_base_address
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};
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static const struct frame_base *
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mips_mdebug_frame_base_sniffer (struct frame_info *next_frame)
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{
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return &mips_mdebug_frame_base;
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}
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static CORE_ADDR
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read_next_frame_reg (struct frame_info *fi, int regno)
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{
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@ -6036,9 +6328,12 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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ensure that all 32 bit addresses are sign extended to 64 bits. */
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set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
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#if 1
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/* Unwind the frame. */
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set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
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#if 0
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frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer);
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set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
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frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer);
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#else
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set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
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/* Initialize a frame */
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