mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-27 20:14:06 +08:00
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
This commit is contained in:
Chris Demetriou
parent
47b667dea5
commit
e70cb6cd9a
@ -1,3 +1,16 @@
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2005-05-26 David Ung <davidu@mips.com>
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* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
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tags to all instructions which are applicable to the new ISAs.
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(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
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vr.igen.
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* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
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instructions.
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* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
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to mips.igen.
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* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
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* configure: Regenerate.
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2005-03-23 Mark Kettenis <kettenis@gnu.org>
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* configure: Regenerate.
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10
sim/mips/configure
vendored
10
sim/mips/configure
vendored
@ -7821,11 +7821,21 @@ case "${target}" in
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sim_igen_filter="32,64,f"
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sim_m16_filter="16"
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;;
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mipsisa32r2*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips32r2"
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sim_igen_filter="32,f"
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sim_mach_default="mipsisa32r2"
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;;
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mipsisa32*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips32"
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sim_igen_filter="32,f"
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sim_mach_default="mipsisa32"
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;;
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mipsisa64r2*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64r2,mips3d"
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sim_igen_filter="32,64,f"
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sim_mach_default="mipsisa64r2"
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;;
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mipsisa64sb1*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64,mips3d,sb1"
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sim_igen_filter="32,64,f"
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@ -145,11 +145,21 @@ case "${target}" in
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sim_igen_filter="32,64,f"
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sim_m16_filter="16"
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;;
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mipsisa32r2*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips32r2"
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sim_igen_filter="32,f"
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sim_mach_default="mipsisa32r2"
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;;
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mipsisa32*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips32"
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sim_igen_filter="32,f"
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sim_mach_default="mipsisa32"
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;;
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mipsisa64r2*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64r2,mips3d"
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sim_igen_filter="32,64,f"
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sim_mach_default="mipsisa64r2"
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;;
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mipsisa64sb1*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64,mips3d,sb1"
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sim_igen_filter="32,64,f"
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File diff suppressed because it is too large
Load Diff
260
sim/mips/mips3264r2.igen
Normal file
260
sim/mips/mips3264r2.igen
Normal file
@ -0,0 +1,260 @@
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// -*- C -*-
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// Simulator definition for the MIPS 32/64 revision 2 instructions.
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// Copyright (C) 2004 Free Software Foundation, Inc.
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// Contributed by David Ung, of MIPS Technologies.
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
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"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
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"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
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"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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010000,01011,5.RT,01100,00000,0,00,000::32::DI
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"di":RT == 0
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"di r<RT>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT0 ();
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GPR[RT] = EXTEND32 (SR);
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SR &= ~status_IE;
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
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"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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if (LSB <= MSB)
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GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
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"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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if (LSB <= MSB + 32)
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GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
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"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
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*mips64r2:
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{
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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if (LSB <= MSB)
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GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32)))
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& MASK64 (MSB + 32, LSB + 32);
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,00000,5.RT,5.RD,00010,100100::64::DSBH
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"dsbh r<RD>, r<RT>"
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*mips64r2:
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{
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union { unsigned64 d; unsigned16 h[4]; } u;
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT1 (GPR[RT]);
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u.d = GPR[RT];
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u.h[0] = SWAP_2 (u.h[0]);
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u.h[1] = SWAP_2 (u.h[1]);
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u.h[2] = SWAP_2 (u.h[2]);
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u.h[3] = SWAP_2 (u.h[3]);
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GPR[RD] = u.d;
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TRACE_ALU_RESULT1 (GPR[RD]);
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}
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011111,00000,5.RT,5.RD,00101,100100::64::DSHD
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"dshd r<RD>, r<RT>"
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*mips64r2:
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{
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unsigned64 d;
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check_u64 (SD_, instruction_0);
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TRACE_ALU_INPUT1 (GPR[RT]);
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d = GPR[RT];
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GPR[RD] = ((d >> 48)
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| (d << 48)
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| ((d & 0x0000ffff00000000) >> 16)
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| ((d & 0x00000000ffff0000) << 16));
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TRACE_ALU_RESULT1 (GPR[RD]);
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}
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010000,01011,5.RT,01100,00000,1,00,000::32::EI
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"ei":RT == 0
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"ei r<RT>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT0 ();
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GPR[RT] = EXTEND32 (SR);
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SR |= status_IE;
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
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"ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB));
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
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"mfhc1 r<RT>, f<FS>"
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*mips32r2:
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*mips64r2:
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{
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check_fpu (SD_);
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if (SizeFGR() == 64)
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GPR[RT] = EXTEND32 (WORD64HI (FGR[FS]));
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else if ((FS & 0x1) == 0)
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GPR[RT] = EXTEND32 (FGR[FS + 1]);
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else
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{
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD,
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"Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
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(long) CIA);
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GPR[RT] = EXTEND32 (0xBADF00D);
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}
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TRACE_ALU_RESULT (GPR[RT]);
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}
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010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
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"mthc1 r<RT>, f<FS>"
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*mips32r2:
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*mips64r2:
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{
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check_fpu (SD_);
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if (SizeFGR() == 64)
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StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS]));
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else if ((FS & 0x1) == 0)
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StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
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else
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{
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD,
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"Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
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(long) CIA);
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StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE);
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}
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TRACE_FP_RESULT (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
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"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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if (LSB <= MSB)
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GPR[RT] = EXTEND32 (GPR[RT] ^
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((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB)));
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TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,00000,5.RT,5.RD,10000,100000::32::SEB
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"seb r<RD>, r<RT>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT1 (GPR[RT]);
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GPR[RD] = EXTEND8 (GPR[RT]);
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TRACE_ALU_RESULT1 (GPR[RD]);
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}
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011111,00000,5.RT,5.RD,11000,100000::32::SEH
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"seh r<RD>, r<RT>"
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*mips32r2:
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*mips64r2:
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{
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TRACE_ALU_INPUT1 (GPR[RT]);
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GPR[RD] = EXTEND16 (GPR[RT]);
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TRACE_ALU_RESULT1 (GPR[RD]);
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}
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000001,5.BASE,11111,16.OFFSET::32::SYNCI
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"synci <OFFSET>(r<BASE>)"
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*mips32r2:
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*mips64r2:
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{
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// sync i-cache - nothing to do currently
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}
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011111,00000,5.RT,5.RD,00010,100000::32::WSBH
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"wsbh r<RD>, r<RT>"
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*mips32r2:
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*mips64r2:
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{
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union { unsigned32 w; unsigned16 h[2]; } u;
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TRACE_ALU_INPUT1 (GPR[RT]);
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u.w = GPR[RT];
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u.h[0] = SWAP_2 (u.h[0]);
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u.h[1] = SWAP_2 (u.h[1]);
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GPR[RD] = EXTEND32 (u.w);
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TRACE_ALU_RESULT1 (GPR[RD]);
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}
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@ -100,35 +100,6 @@
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GPR[rd] = store_hi_p ? HI : LO;
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}
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// 32-bit rotate right of X by Y bits.
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:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
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*vr5400:
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*vr5500:
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{
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unsigned64 result;
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y &= 31;
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TRACE_ALU_INPUT2 (x, y);
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result = EXTEND32 (ROTR32 (x, y));
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TRACE_ALU_RESULT (result);
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return result;
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}
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// Likewise 64-bit
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:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
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*vr5400:
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*vr5500:
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{
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unsigned64 result;
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y &= 63;
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TRACE_ALU_INPUT2 (x, y);
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result = ROTR64 (x, y);
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TRACE_ALU_RESULT (result);
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return result;
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}
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// VR4100 instructions.
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000000,5.RS,5.RT,00000,00000,101000::32::MADD16
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@ -246,45 +217,6 @@
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0 /* single */);
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}
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000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
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"ror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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*vr5500:
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{
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GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
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}
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000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
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"rorv r<RD>, r<RT>, r<RS>"
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*vr5400:
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*vr5500:
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{
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GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
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}
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000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
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"dror r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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*vr5500:
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{
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GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
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}
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000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
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"dror32 r<RD>, r<RT>, <SHIFT>"
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*vr5400:
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*vr5500:
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{
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GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
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}
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000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
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"drorv r<RD>, r<RT>, r<RS>"
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*vr5400:
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*vr5500:
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{
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GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
|
||||
}
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010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
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"luxc1 f<FD>, r<INDEX>(r<BASE>)"
|
||||
|
||||
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