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[binutils][Arm] Fix Branch Future relocation handling and testisms
bfd/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR/target 24460 * elf32-arm.c (get_value_helper): Remove. (elf32_arm_final_link_relocate): Fix branch future relocations. gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming conventions. * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise. * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise. * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test. ld/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm-elf.exp: Add tests * testsuite/ld-arm/bfs-0.s: New test. * testsuite/ld-arm/bfs-1.s: New test. * testsuite/ld-arm/branch-futures.d: New test.
This commit is contained in:
Andre Vieira
parent
739b5c9c77
commit
e6f65e7573
@ -1,3 +1,9 @@
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2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
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PR 24460
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* elf32-arm.c (get_value_helper): Remove.
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(elf32_arm_final_link_relocate): Fix branch future relocations.
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2019-05-21 Tamar Christina <tamar.christina@arm.com>
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PR ld/24373
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@ -10293,59 +10293,6 @@ identify_add_or_sub (bfd_vma insn)
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return 0;
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}
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/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
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static bfd_vma
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get_value_helper (bfd_vma plt_offset,
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asection *splt,
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asection *input_section,
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asection *sym_sec,
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struct elf_link_hash_entry * h,
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struct bfd_link_info *info,
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bfd *input_bfd,
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Elf_Internal_Rela *rel,
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const char *sym_name,
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unsigned char st_type,
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struct elf32_arm_link_hash_table *globals,
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bfd_boolean *unresolved_reloc_p)
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{
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bfd_vma value = 0;
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enum arm_st_branch_type branch_type;
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enum elf32_arm_stub_type stub_type = arm_stub_none;
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struct elf32_arm_stub_hash_entry *stub_entry;
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struct elf32_arm_link_hash_entry *hash
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= (struct elf32_arm_link_hash_entry *)h;
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if (plt_offset != (bfd_vma) -1)
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{
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value = (splt->output_section->vma
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+ splt->output_offset
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+ plt_offset);
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value -= PLT_THUMB_STUB_SIZE;
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*unresolved_reloc_p = FALSE;
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}
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stub_type = arm_type_of_stub (info, input_section, rel,
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st_type, &branch_type,
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hash, value, sym_sec,
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input_bfd, sym_name);
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if (stub_type != arm_stub_none)
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{
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stub_entry = elf32_arm_get_stub_entry (input_section,
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sym_sec, h,
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rel, globals,
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stub_type);
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if (stub_entry != NULL)
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{
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value = (stub_entry->stub_offset
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+ stub_entry->stub_sec->output_offset
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+ stub_entry->stub_sec->output_section->vma);
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}
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}
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return value;
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}
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/* Perform a relocation as part of a final link. */
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static bfd_reloc_status_type
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@ -12968,14 +12915,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
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addend |= (immC << 1);
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addend |= 1;
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/* Sign extend. */
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addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
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signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
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}
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value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
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info, input_bfd, rel, sym_name, st_type,
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globals, unresolved_reloc_p);
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relocation = value + addend;
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relocation = value + signed_addend;
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relocation -= (input_section->output_section->vma
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+ input_section->output_offset
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+ rel->r_offset);
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@ -13014,13 +12957,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
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addend |= 1;
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/* Sign extend. */
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addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
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signed_addend = addend;
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}
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value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
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info, input_bfd, rel, sym_name, st_type,
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globals, unresolved_reloc_p);
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relocation = value + addend;
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relocation = value + signed_addend;
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relocation -= (input_section->output_section->vma
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+ input_section->output_offset
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+ rel->r_offset);
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@ -13059,13 +12999,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
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addend |= 1;
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/* Sign extend. */
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addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
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signed_addend = addend;
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}
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value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
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info, input_bfd, rel, sym_name, st_type,
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globals, unresolved_reloc_p);
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relocation = value + addend;
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relocation = value + signed_addend;
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relocation -= (input_section->output_section->vma
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+ input_section->output_offset
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+ rel->r_offset);
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@ -1,3 +1,15 @@
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2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
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conventions.
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* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
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* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
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* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
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* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
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* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
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* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
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* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
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2019-05-21 John Darrington <john@darrington.wattle.id.au>
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* expr.c (literal_prefix_dollar_hex): New variable.
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@ -1,7 +1,7 @@
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#name: Valid Armv8.1-M Mainline BF instruction with relocation
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#name: Valid Armv8.1-M Mainline BF instruction with REL
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-*
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#skip: *-*-pe *-wince-* *-vxworks
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.*: +file format .*arm.*
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12
gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
Normal file
12
gas/testsuite/gas/arm/armv8_1-m-bf-rela.d
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@ -0,0 +1,12 @@
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#name: Valid Armv8.1-M Mainline BF instruction with RELA
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#source:armv8_1-m-bf-rel.s
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#noskip: *-vxworks
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f0c0 e001 bf 2, 00000004 <.target\+0x4>
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0: R_ARM_THM_BF16 .target-0x4
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@ -5,9 +5,9 @@
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
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0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <.*>
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0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
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0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <foo\+0xc>
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0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <.*>
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0[0-9a-f]+ <[^>]+> 460a mov r2, r1
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
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@ -5,8 +5,8 @@
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <foo\+0xa>, 4, eq
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0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <.*>, 4, eq
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0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
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0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <foo\+0xa>
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0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <.*>
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
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@ -1,7 +1,7 @@
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#name: Valid Armv8.1-M Mainline BFL instruction with relocation
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#name: Valid Armv8.1-M Mainline BFL instruction with REL
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-*
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#skip: *-*-pe *-wince-* *-vxworks
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.*: +file format .*arm.*
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12
gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
Normal file
12
gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d
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@ -0,0 +1,12 @@
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#name: Valid Armv8.1-M Mainline BFL instruction with RELA
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#source: armv8_1-m-bfl-rel.s
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#noskip: *-vxworks
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f080 c001 bfl 2, 00000004 <.target\+0x4>
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0: R_ARM_THM_BF18 .target-0x4
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@ -5,9 +5,9 @@
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <foo\+0xa>
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0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <.*>
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0[0-9a-f]+ <[^>]+> 4608 mov r0, r1
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0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <foo\+0xc>
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0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <.*>
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0[0-9a-f]+ <[^>]+> 460a mov r2, r1
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
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@ -6,12 +6,12 @@
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c>
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0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <.*>
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0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2
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0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr
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0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo>
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0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo>
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0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84>
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0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10>
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0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <.*>
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0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <.*>
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0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <.*>
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0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <.*>
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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#...
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@ -1,3 +1,10 @@
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2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* testsuite/ld-arm/arm-elf.exp: Add tests
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* testsuite/ld-arm/bfs-0.s: New test.
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* testsuite/ld-arm/bfs-1.s: New test.
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* testsuite/ld-arm/branch-futures.d: New test.
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2019-05-21 Tamar Christina <tamar.christina@arm.com>
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PR ld/24373
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@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} {
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"" {vxworks2.s}
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{{readelf --segments vxworks2-static.sd}}
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"vxworks2"}
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{"Branch future relocations for armv8.1-m.main target"
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"-static -T arm.ld"
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"" "" {bfs-0.s bfs-1.s}
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{{objdump -dw branch-futures.d}}
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"branch-futures"}
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}
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run_ld_link_tests $armvxworkstests
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run_dump_test "vxworks1-static"
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@ -260,6 +265,10 @@ set armelftests_common_3 {
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{"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s}
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{{objdump -dw thumb1-adds.d}}
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"thumb1-adds"}
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{"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld"
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"" "" {bfs-0.s bfs-1.s}
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{{objdump -dw branch-futures.d}}
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"branch-futures"}
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}
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run_ld_link_tests $armelftests_common_1
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12
ld/testsuite/ld-arm/bfs-0.s
Normal file
12
ld/testsuite/ld-arm/bfs-0.s
Normal file
@ -0,0 +1,12 @@
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.arch armv8.1-m.main
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.text
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.syntax unified
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.thumb
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future:
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bf branch, target
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bfcsel branch, target, else, eq
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bfl branch, target
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add r0, r0, r1
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branch:
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b target
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else:
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9
ld/testsuite/ld-arm/bfs-1.s
Normal file
9
ld/testsuite/ld-arm/bfs-1.s
Normal file
@ -0,0 +1,9 @@
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.arch armv8.1-m.main
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.text
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.syntax unified
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.thumb
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.global _start
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.global target
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_start:
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target:
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add r0, r0, r1
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17
ld/testsuite/ld-arm/branch-futures.d
Normal file
17
ld/testsuite/ld-arm/branch-futures.d
Normal file
@ -0,0 +1,17 @@
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.*: file format elf32-.*
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Disassembly of section .text:
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0[0-9a-f]+ <future>:
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[0-9a-f]+: f2c0 e807 bf a, 8012 <_start>
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[0-9a-f]+: f182 e805 bfcsel 6, 8012 <_start>, a, eq
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[0-9a-f]+: f080 c803 bfl 2, 8012 <_start>
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[0-9a-f]+: 4408 add r0, r1
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0[0-9a-f]+ <branch>:
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[0-9a-f]+: f000 b800 b.w 8012 <_start>
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0[0-9a-f]+ <_start>:
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[0-9a-f]+: 4408 add r0, r1
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