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* sim-main.h: Delete inclusion of ansidecl.h.

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* cpu.h: Regenerate.
	* cpux.h: Regenerate.
This commit is contained in:
Doug Evans 1999-01-12 00:25:41 +00:00
parent 5dddc35ca9
commit e64b6cd434
3 changed files with 78 additions and 66 deletions
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8
sim/m32r/ChangeLog
View File

@ -1,3 +1,11 @@
1999-01-11 Doug Evans <devans@casey.cygnus.com>
* sim-main.h: Delete inclusion of ansidecl.h.
* cpu.h: Regenerate.
start-sanitize-m32rx
* cpux.h: Regenerate.
end-sanitize-m32rx
1999-01-06 Doug Evans <devans@casey.cygnus.com>
* cpu.h: Regenerate.

68
sim/m32r/cpu.h
View File

@ -118,17 +118,7 @@ typedef struct {
int empty;
} MODEL_TEST_DATA;
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
PCADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* cpu specific data follows */
union sem semantic;
int written;
union {
union sem_fields {
struct { /* empty format for unspecified field list */
int empty;
} fmt_empty;
@ -440,29 +430,41 @@ struct argbuf {
#endif
} cti;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
} chain;
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
} chain;
#endif
} fields;
};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
PCADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* cpu specific data follows */
union sem semantic;
int written;
union sem_fields fields;
};
/* A cached insn.

68
sim/m32r/cpux.h
View File

@ -114,17 +114,7 @@ typedef struct {
int empty;
} MODEL_M32RX_DATA;
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
PCADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* cpu specific data follows */
union sem semantic;
int written;
union {
union sem_fields {
struct { /* empty format for unspecified field list */
int empty;
} fmt_empty;
@ -494,29 +484,41 @@ struct argbuf {
#endif
} cti;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
} chain;
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
} chain;
#endif
} fields;
};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
PCADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* cpu specific data follows */
union sem semantic;
int written;
union sem_fields fields;
};
/* A cached insn.