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RISC-V: PR28733, add missing extension info to 'unrecognized opcode' error
Currently we report errors as "unrecognized opcode `fence.i'" when the opcode isn't part of the selected extensions. This patch expands that error message to include the missing extension information. For example, now the error message would be "unrecognized opcode `fence.i', extension `zifencei' required". If the opcode is not a part of any extension, the error message reverts to "unrecognized opcode `<op statement>'". Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> bfd/ pr 28733 * elfxx-riscv.c (riscv_multi_subset_supports_ext): New function, used to return the extension string for each INSN_CLASS_*. * elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext. gas/ pr 28733 * config/tc-riscv.c (struct riscv_ip_error): New structure, contains information about errors that occur within the riscv_ip. (riscv_ip): Use struct riscv_ip_error to report more detailed errors. * testsuite/gas/riscv/c-fld-fsd-fail.l: Updated. * testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
This commit is contained in:
Patrick O'Neill
Nelson Chu
parent
df0a549ebd
commit
e4028336b1
@ -2402,3 +2402,97 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return false;
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}
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}
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/* Each instuction is belonged to an instruction class INSN_CLASS_*.
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Call riscv_subset_supports_ext to determine the missing extension. */
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const char *
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riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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enum riscv_insn_class insn_class)
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{
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switch (insn_class)
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{
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case INSN_CLASS_I:
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return "i";
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case INSN_CLASS_ZICSR:
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return "zicsr";
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case INSN_CLASS_ZIFENCEI:
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return "zifencei";
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case INSN_CLASS_ZIHINTPAUSE:
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return "zihintpause";
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case INSN_CLASS_M:
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return "m";
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case INSN_CLASS_A:
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return "a";
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case INSN_CLASS_F:
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return "f";
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case INSN_CLASS_D:
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return "d";
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case INSN_CLASS_Q:
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return "q";
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case INSN_CLASS_C:
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return "c";
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case INSN_CLASS_F_AND_C:
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if (!riscv_subset_supports (rps, "f")
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&& !riscv_subset_supports (rps, "c"))
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return "f' and `c";
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else if (!riscv_subset_supports (rps, "f"))
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return "f";
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else
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return "c";
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case INSN_CLASS_D_AND_C:
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if (!riscv_subset_supports (rps, "d")
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&& !riscv_subset_supports (rps, "c"))
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return "d' and `c";
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else if (!riscv_subset_supports (rps, "d"))
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return "d";
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else
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return "c";
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case INSN_CLASS_F_OR_ZFINX:
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return "f' or `zfinx";
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case INSN_CLASS_D_OR_ZDINX:
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return "d' or `zdinx";
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case INSN_CLASS_Q_OR_ZQINX:
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return "q' or `zqinx";
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case INSN_CLASS_ZBA:
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return "zba";
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case INSN_CLASS_ZBB:
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return "zbb";
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case INSN_CLASS_ZBC:
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return "zbc";
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case INSN_CLASS_ZBS:
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return "zbs";
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case INSN_CLASS_ZBKB:
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return "zbkb";
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case INSN_CLASS_ZBKC:
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return "zbkc";
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case INSN_CLASS_ZBKX:
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return "zbkx";
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case INSN_CLASS_ZBB_OR_ZBKB:
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return "zbb' or `zbkb";
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case INSN_CLASS_ZBC_OR_ZBKC:
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return "zbc' or `zbkc";
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case INSN_CLASS_ZKND:
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return "zknd";
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case INSN_CLASS_ZKNE:
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return "zkne";
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case INSN_CLASS_ZKNH:
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return "zknh";
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case INSN_CLASS_ZKND_OR_ZKNE:
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return "zknd' or `zkne";
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case INSN_CLASS_ZKSED:
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return "zksed";
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case INSN_CLASS_ZKSH:
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return "zksh";
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case INSN_CLASS_V:
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return "v' or `zve64x' or `zve32x";
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case INSN_CLASS_ZVEF:
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return "v' or `zve64d' or `zve64f' or `zve32f";
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case INSN_CLASS_SVINVAL:
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return "svinval";
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default:
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rps->error_handler
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(_("internal: unreachable INSN_CLASS_*"));
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return NULL;
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}
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}
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@ -104,6 +104,9 @@ riscv_subset_supports (riscv_parse_subset_t *, const char *);
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extern bool
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riscv_multi_subset_supports (riscv_parse_subset_t *, enum riscv_insn_class);
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extern const char *
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riscv_multi_subset_supports_ext (riscv_parse_subset_t *, enum riscv_insn_class);
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extern void
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bfd_elf32_riscv_set_data_segment_info (struct bfd_link_info *, int *);
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extern void
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@ -89,6 +89,20 @@ struct riscv_csr_extra
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struct riscv_csr_extra *next;
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};
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/* This structure contains information about errors that occur within the
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riscv_ip function */
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struct riscv_ip_error
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{
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/* General error message */
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const char* msg;
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/* Statement that caused the error */
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char* statement;
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/* Missing extension that needs to be enabled */
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const char* missing_ext;
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};
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#ifndef DEFAULT_ARCH
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#define DEFAULT_ARCH "riscv64"
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#endif
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@ -2221,7 +2235,7 @@ riscv_is_priv_insn (insn_t insn)
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side effect, it sets the global variable imm_reloc to the type of
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relocation to do if one of the operands is an address expression. */
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static const char *
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static struct riscv_ip_error
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riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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bfd_reloc_code_real_type *imm_reloc, htab_t hash)
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{
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@ -2234,7 +2248,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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unsigned int regno;
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int argnum;
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const struct percent_op_match *p;
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const char *error = "unrecognized opcode";
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struct riscv_ip_error error;
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error.msg = "unrecognized opcode";
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error.statement = str;
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error.missing_ext = NULL;
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/* Indicate we are assembling instruction with CSR. */
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bool insn_with_csr = false;
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@ -2257,10 +2274,15 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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continue;
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if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class))
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continue;
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{
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error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
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insn->insn_class);
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continue;
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}
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/* Reset error message of the previous round. */
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error = _("illegal operands");
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error.msg = _("illegal operands");
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error.missing_ext = NULL;
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create_insn (ip, insn);
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argnum = 1;
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@ -2310,14 +2332,14 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
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&& riscv_subset_supports (&riscv_rps_as, "zve32x")
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&& !riscv_subset_supports (&riscv_rps_as, "zve64x"))
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{
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error = _("illegal opcode for zve32x");
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error.msg = _("illegal opcode for zve32x");
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break;
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}
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}
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if (*asarg != '\0')
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break;
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/* Successful assembly. */
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error = NULL;
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error.msg = NULL;
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insn_with_csr = false;
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goto out;
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@ -3253,11 +3275,16 @@ md_assemble (char *str)
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riscv_mapping_state (MAP_INSN, 0);
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const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
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const struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr,
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&imm_reloc, op_hash);
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if (error)
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if (error.msg)
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{
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as_bad ("%s `%s'", error, str);
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if (error.missing_ext)
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as_bad ("%s `%s', extension `%s' required", error.msg,
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error.statement, error.missing_ext);
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else
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as_bad ("%s `%s'", error.msg, error.statement);
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return;
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}
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@ -4266,17 +4293,23 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
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riscv_mapping_state (MAP_INSN, 0);
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const char *error = riscv_ip (str, &insn, &imm_expr,
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struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr,
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&imm_reloc, insn_type_hash);
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if (error)
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if (error.msg)
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{
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char *save_in = input_line_pointer;
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error = riscv_ip_hardcode (str, &insn, &imm_expr, error);
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error.msg = riscv_ip_hardcode (str, &insn, &imm_expr, error.msg);
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input_line_pointer = save_in;
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}
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if (error)
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as_bad ("%s `%s'", error, str);
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if (error.msg)
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{
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if (error.missing_ext)
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as_bad ("%s `%s', extension `%s' required", error.msg, error.statement,
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error.missing_ext);
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else
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as_bad ("%s `%s'", error.msg, error.statement);
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}
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else
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{
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gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
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@ -1,3 +1,3 @@
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.*: Assembler messages:
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.*: Error: unrecognized opcode `fld fa0,0\(a0\)'
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.*: Error: unrecognized opcode `fsd fa0,0\(a0\)'
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.*: Error: unrecognized opcode `fld fa0,0\(a0\)', extension `d' required
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.*: Error: unrecognized opcode `fsd fa0,0\(a0\)', extension `d' required
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@ -1,21 +1,21 @@
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.*Assembler messages:
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.*Error: unrecognized opcode `csrr t0,ustatus'
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.*Error: unrecognized opcode `csrwi ustatus,0x0'
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.*Error: unrecognized opcode `csrsi ustatus,0x0'
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.*Error: unrecognized opcode `csrci ustatus,0x0'
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.*Error: unrecognized opcode `csrw ustatus,t0'
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.*Error: unrecognized opcode `csrw ustatus,0x0'
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.*Error: unrecognized opcode `csrs ustatus,t0'
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.*Error: unrecognized opcode `csrs ustatus,0x0'
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.*Error: unrecognized opcode `csrc ustatus,t0'
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.*Error: unrecognized opcode `csrc ustatus,0x0'
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.*Error: unrecognized opcode `csrrwi t0,ustatus,0x0'
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.*Error: unrecognized opcode `csrrsi t0,ustatus,0x0'
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.*Error: unrecognized opcode `csrrci t0,ustatus,0x0'
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.*Error: unrecognized opcode `csrrw t0,ustatus,t0'
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.*Error: unrecognized opcode `csrrw t0,ustatus,0x0'
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.*Error: unrecognized opcode `csrrs t0,ustatus,t0'
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.*Error: unrecognized opcode `csrrs t0,ustatus,0x0'
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.*Error: unrecognized opcode `csrrc t0,ustatus,t0'
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.*Error: unrecognized opcode `csrrc t0,ustatus,0x0'
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.*Error: unrecognized opcode `fence.i'
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.*Error: unrecognized opcode `csrr t0,ustatus', extension `zicsr' required
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.*Error: unrecognized opcode `csrwi ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrsi ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrci ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrw ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrw ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrs ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrs ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrc ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrc ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrwi t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrsi t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrci t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrw t0,ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrw t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrs t0,ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrs t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrc t0,ustatus,t0', extension `zicsr' required
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.*Error: unrecognized opcode `csrrc t0,ustatus,0x0', extension `zicsr' required
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.*Error: unrecognized opcode `fence.i', extension `zifencei' required
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