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include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. opcodes/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. * aarch64-asm.c (convert_xtl_to_shll): New function. (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_xtl_to_shll. * aarch64-dis.c (convert_shll_to_xtl): New function. (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_shll_to_xtl. * aarch64-gen.c: Update copyright year. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Re-generate. * aarch64-opc-2.c: Re-generate. gas/testsuite/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/alias.s: Add new tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update.
This commit is contained in:
Yufeng Zhang
parent
f9b2d5449a
commit
e30181a58d
@ -1,3 +1,9 @@
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2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/alias.s: Add new tests.
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* gas/aarch64/alias.d: Update.
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* gas/aarch64/no-aliases.d: Update.
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2013-01-30 Markos Chandras <markos.chandras@imgtec.com>
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* gas/metag/metacore21-invalid.s: Add invalid SWAP testcases.
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@ -72,3 +72,27 @@ Disassembly of section \.text:
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100: b13ffdff cmn x15, #0xfff
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104: f13fffef subs x15, sp, #0xfff
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108: b13ffdff cmn x15, #0xfff
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10c: 0f08a448 sxtl v8.8h, v2.8b
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110: 0f08a448 sxtl v8.8h, v2.8b
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114: 4f08a448 sxtl2 v8.8h, v2.16b
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118: 4f08a448 sxtl2 v8.8h, v2.16b
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11c: 0f10a448 sxtl v8.4s, v2.4h
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120: 0f10a448 sxtl v8.4s, v2.4h
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124: 4f10a448 sxtl2 v8.4s, v2.8h
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128: 4f10a448 sxtl2 v8.4s, v2.8h
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12c: 0f20a448 sxtl v8.2d, v2.2s
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130: 0f20a448 sxtl v8.2d, v2.2s
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134: 4f20a448 sxtl2 v8.2d, v2.4s
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138: 4f20a448 sxtl2 v8.2d, v2.4s
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13c: 2f08a448 uxtl v8.8h, v2.8b
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140: 2f08a448 uxtl v8.8h, v2.8b
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144: 6f08a448 uxtl2 v8.8h, v2.16b
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148: 6f08a448 uxtl2 v8.8h, v2.16b
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14c: 2f10a448 uxtl v8.4s, v2.4h
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150: 2f10a448 uxtl v8.4s, v2.4h
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154: 6f10a448 uxtl2 v8.4s, v2.8h
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158: 6f10a448 uxtl2 v8.4s, v2.8h
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15c: 2f20a448 uxtl v8.2d, v2.2s
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160: 2f20a448 uxtl v8.2d, v2.2s
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164: 6f20a448 uxtl2 v8.2d, v2.4s
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168: 6f20a448 uxtl2 v8.2d, v2.4s
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@ -2,7 +2,7 @@
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preference. It is also used to test the -Mno-aliases option in
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the disassemler.
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Copyright 2012 Free Software Foundation, Inc.
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Copyright 2012, 2013 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GAS.
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@ -99,3 +99,21 @@
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adds xzr, x15, #0xfff
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subs x15, sp, #0xfff
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cmn x15, #0xfff
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.macro asimdshll s
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\s\()xtl v8.8h, v2.8b
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\s\()shll v8.8h, v2.8b, #0
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\s\()xtl2 v8.8h, v2.16b
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\s\()shll2 v8.8h, v2.16b, #0
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\s\()xtl v8.4s, v2.4h
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\s\()shll v8.4s, v2.4h, #0
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\s\()xtl2 v8.4s, v2.8h
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\s\()shll2 v8.4s, v2.8h, #0
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\s\()xtl v8.2d, v2.2s
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\s\()shll v8.2d, v2.2s, #0
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\s\()xtl2 v8.2d, v2.4s
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\s\()shll2 v8.2d, v2.4s, #0
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.endm
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asimdshll s
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asimdshll u
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@ -73,3 +73,27 @@ Disassembly of section \.text:
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100: b13ffdff adds xzr, x15, #0xfff
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104: f13fffef subs x15, sp, #0xfff
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108: b13ffdff adds xzr, x15, #0xfff
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10c: 0f08a448 sshll v8.8h, v2.8b, #0
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110: 0f08a448 sshll v8.8h, v2.8b, #0
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114: 4f08a448 sshll2 v8.8h, v2.16b, #0
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118: 4f08a448 sshll2 v8.8h, v2.16b, #0
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11c: 0f10a448 sshll v8.4s, v2.4h, #0
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120: 0f10a448 sshll v8.4s, v2.4h, #0
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124: 4f10a448 sshll2 v8.4s, v2.8h, #0
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128: 4f10a448 sshll2 v8.4s, v2.8h, #0
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12c: 0f20a448 sshll v8.2d, v2.2s, #0
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130: 0f20a448 sshll v8.2d, v2.2s, #0
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134: 4f20a448 sshll2 v8.2d, v2.4s, #0
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138: 4f20a448 sshll2 v8.2d, v2.4s, #0
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13c: 2f08a448 ushll v8.8h, v2.8b, #0
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140: 2f08a448 ushll v8.8h, v2.8b, #0
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144: 6f08a448 ushll2 v8.8h, v2.16b, #0
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148: 6f08a448 ushll2 v8.8h, v2.16b, #0
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14c: 2f10a448 ushll v8.4s, v2.4h, #0
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150: 2f10a448 ushll v8.4s, v2.4h, #0
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154: 6f10a448 ushll2 v8.4s, v2.8h, #0
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158: 6f10a448 ushll2 v8.4s, v2.8h, #0
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15c: 2f20a448 ushll v8.2d, v2.2s, #0
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160: 2f20a448 ushll v8.2d, v2.2s, #0
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164: 6f20a448 ushll2 v8.2d, v2.4s, #0
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168: 6f20a448 ushll2 v8.2d, v2.4s, #0
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@ -1,3 +1,7 @@
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2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
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2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
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PR gas/15069
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@ -1,6 +1,6 @@
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/* AArch64 assembler/disassembler support.
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Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
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Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GNU Binutils.
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@ -424,6 +424,11 @@ enum aarch64_op
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OP_ROR_IMM,
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OP_SXTL,
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OP_SXTL2,
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OP_UXTL,
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OP_UXTL2,
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OP_TOTAL_NUM, /* Pseudo. */
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};
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@ -1,3 +1,18 @@
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2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
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ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
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* aarch64-asm.c (convert_xtl_to_shll): New function.
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(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
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calling convert_xtl_to_shll.
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* aarch64-dis.c (convert_shll_to_xtl): New function.
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(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
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calling convert_shll_to_xtl.
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* aarch64-gen.c: Update copyright year.
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* aarch64-asm-2.c: Re-generate.
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* aarch64-dis-2.c: Re-generate.
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* aarch64-opc-2.c: Re-generate.
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2013-01-24 Nick Clifton <nickc@redhat.com>
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* v850-dis.c: Add support for e3v5 architecture.
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@ -1,5 +1,5 @@
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/* This file is automatically generated by aarch64-gen. Do not edit! */
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/* Copyright 2012 Free Software Foundation, Inc.
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/* Copyright 2012, 2013 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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@ -76,147 +76,159 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 259: /* mov */
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value = 258; /* --> orr. */
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break;
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case 427: /* mov */
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value = 426; /* --> dup. */
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case 314: /* sxtl */
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value = 313; /* --> sshll. */
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break;
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case 494: /* sxtw */
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case 493: /* sxth */
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case 492: /* sxtb */
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case 495: /* asr */
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case 491: /* sbfx */
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case 490: /* sbfiz */
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value = 489; /* --> sbfm. */
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case 316: /* sxtl2 */
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value = 315; /* --> sshll2. */
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break;
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case 498: /* bfxil */
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case 497: /* bfi */
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value = 496; /* --> bfm. */
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case 336: /* uxtl */
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value = 335; /* --> ushll. */
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break;
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case 503: /* uxth */
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case 502: /* uxtb */
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case 505: /* lsr */
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case 504: /* lsl */
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case 501: /* ubfx */
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case 500: /* ubfiz */
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value = 499; /* --> ubfm. */
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case 338: /* uxtl2 */
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value = 337; /* --> ushll2. */
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break;
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case 523: /* cset */
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case 522: /* cinc */
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value = 521; /* --> csinc. */
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case 431: /* mov */
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value = 430; /* --> dup. */
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break;
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case 526: /* csetm */
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case 525: /* cinv */
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value = 524; /* --> csinv. */
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case 498: /* sxtw */
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case 497: /* sxth */
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case 496: /* sxtb */
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case 499: /* asr */
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case 495: /* sbfx */
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case 494: /* sbfiz */
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value = 493; /* --> sbfm. */
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break;
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case 528: /* cneg */
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value = 527; /* --> csneg. */
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case 502: /* bfxil */
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case 501: /* bfi */
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value = 500; /* --> bfm. */
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break;
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case 553: /* lsl */
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value = 552; /* --> lslv. */
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case 507: /* uxth */
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case 506: /* uxtb */
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case 509: /* lsr */
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case 508: /* lsl */
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case 505: /* ubfx */
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case 504: /* ubfiz */
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value = 503; /* --> ubfm. */
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break;
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case 555: /* lsr */
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value = 554; /* --> lsrv. */
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case 527: /* cset */
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case 526: /* cinc */
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value = 525; /* --> csinc. */
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break;
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case 557: /* asr */
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value = 556; /* --> asrv. */
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case 530: /* csetm */
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case 529: /* cinv */
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value = 528; /* --> csinv. */
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break;
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case 559: /* ror */
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value = 558; /* --> rorv. */
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case 532: /* cneg */
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value = 531; /* --> csneg. */
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break;
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case 561: /* mul */
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value = 560; /* --> madd. */
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case 557: /* lsl */
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value = 556; /* --> lslv. */
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break;
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case 563: /* mneg */
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value = 562; /* --> msub. */
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case 559: /* lsr */
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value = 558; /* --> lsrv. */
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break;
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case 565: /* smull */
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value = 564; /* --> smaddl. */
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case 561: /* asr */
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value = 560; /* --> asrv. */
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break;
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case 567: /* smnegl */
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value = 566; /* --> smsubl. */
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case 563: /* ror */
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value = 562; /* --> rorv. */
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break;
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case 570: /* umull */
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value = 569; /* --> umaddl. */
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case 565: /* mul */
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value = 564; /* --> madd. */
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break;
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case 572: /* umnegl */
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value = 571; /* --> umsubl. */
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case 567: /* mneg */
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value = 566; /* --> msub. */
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break;
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case 583: /* ror */
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value = 582; /* --> extr. */
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case 569: /* smull */
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value = 568; /* --> smaddl. */
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break;
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case 683: /* strb */
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value = 681; /* --> sturb. */
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case 571: /* smnegl */
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value = 570; /* --> smsubl. */
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break;
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case 684: /* ldrb */
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value = 682; /* --> ldurb. */
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case 574: /* umull */
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value = 573; /* --> umaddl. */
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break;
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case 686: /* ldrsb */
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value = 685; /* --> ldursb. */
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case 576: /* umnegl */
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value = 575; /* --> umsubl. */
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break;
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case 689: /* str */
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value = 687; /* --> stur. */
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case 587: /* ror */
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value = 586; /* --> extr. */
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break;
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case 690: /* ldr */
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value = 688; /* --> ldur. */
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case 687: /* strb */
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value = 685; /* --> sturb. */
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break;
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case 693: /* strh */
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value = 691; /* --> sturh. */
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case 688: /* ldrb */
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value = 686; /* --> ldurb. */
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break;
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case 694: /* ldrh */
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value = 692; /* --> ldurh. */
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case 690: /* ldrsb */
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value = 689; /* --> ldursb. */
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break;
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case 696: /* ldrsh */
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value = 695; /* --> ldursh. */
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case 693: /* str */
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value = 691; /* --> stur. */
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break;
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case 699: /* str */
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value = 697; /* --> stur. */
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case 694: /* ldr */
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value = 692; /* --> ldur. */
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break;
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case 700: /* ldr */
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value = 698; /* --> ldur. */
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case 697: /* strh */
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value = 695; /* --> sturh. */
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break;
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case 702: /* ldrsw */
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value = 701; /* --> ldursw. */
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case 698: /* ldrh */
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value = 696; /* --> ldurh. */
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break;
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case 704: /* prfm */
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value = 703; /* --> prfum. */
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case 700: /* ldrsh */
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value = 699; /* --> ldursh. */
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break;
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case 746: /* bic */
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value = 745; /* --> and. */
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case 703: /* str */
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value = 701; /* --> stur. */
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break;
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case 748: /* mov */
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value = 747; /* --> orr. */
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case 704: /* ldr */
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value = 702; /* --> ldur. */
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break;
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case 751: /* tst */
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value = 750; /* --> ands. */
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case 706: /* ldrsw */
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value = 705; /* --> ldursw. */
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break;
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case 756: /* uxtw */
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case 755: /* mov */
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value = 754; /* --> orr. */
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case 708: /* prfm */
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value = 707; /* --> prfum. */
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break;
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case 758: /* mvn */
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value = 757; /* --> orn. */
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case 750: /* bic */
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||||
value = 749; /* --> and. */
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break;
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case 762: /* tst */
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value = 761; /* --> ands. */
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case 752: /* mov */
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||||
value = 751; /* --> orr. */
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||||
break;
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case 765: /* mov */
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value = 764; /* --> movn. */
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||||
case 755: /* tst */
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||||
value = 754; /* --> ands. */
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||||
break;
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case 767: /* mov */
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value = 766; /* --> movz. */
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case 760: /* uxtw */
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||||
case 759: /* mov */
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value = 758; /* --> orr. */
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||||
break;
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case 778: /* sevl */
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case 777: /* sev */
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||||
case 776: /* wfi */
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case 775: /* wfe */
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case 774: /* yield */
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case 773: /* nop */
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value = 772; /* --> hint. */
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case 762: /* mvn */
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value = 761; /* --> orn. */
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break;
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case 787: /* tlbi */
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case 786: /* ic */
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case 785: /* dc */
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||||
case 784: /* at */
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value = 783; /* --> sys. */
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||||
case 766: /* tst */
|
||||
value = 765; /* --> ands. */
|
||||
break;
|
||||
case 769: /* mov */
|
||||
value = 768; /* --> movn. */
|
||||
break;
|
||||
case 771: /* mov */
|
||||
value = 770; /* --> movz. */
|
||||
break;
|
||||
case 782: /* sevl */
|
||||
case 781: /* sev */
|
||||
case 780: /* wfi */
|
||||
case 779: /* wfe */
|
||||
case 778: /* yield */
|
||||
case 777: /* nop */
|
||||
value = 776; /* --> hint. */
|
||||
break;
|
||||
case 791: /* tlbi */
|
||||
case 790: /* ic */
|
||||
case 789: /* dc */
|
||||
case 788: /* at */
|
||||
value = 787; /* --> sys. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* aarch64-asm.c -- AArch64 assembler support.
|
||||
Copyright 2012 Free Software Foundation, Inc.
|
||||
Copyright 2012, 2013 Free Software Foundation, Inc.
|
||||
Contributed by ARM Ltd.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
@ -958,6 +958,16 @@ convert_ror_to_extr (aarch64_inst *inst)
|
||||
copy_operand_info (inst, 2, 1);
|
||||
}
|
||||
|
||||
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
|
||||
is equivalent to:
|
||||
USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
|
||||
static void
|
||||
convert_xtl_to_shll (aarch64_inst *inst)
|
||||
{
|
||||
inst->operands[2].qualifier = inst->operands[1].qualifier;
|
||||
inst->operands[2].imm.value = 0;
|
||||
}
|
||||
|
||||
/* Convert
|
||||
LSR <Xd>, <Xn>, #<shift>
|
||||
to
|
||||
@ -1167,6 +1177,12 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
|
||||
case OP_ROR_IMM:
|
||||
convert_ror_to_extr (inst);
|
||||
break;
|
||||
case OP_SXTL:
|
||||
case OP_SXTL2:
|
||||
case OP_UXTL:
|
||||
case OP_UXTL2:
|
||||
convert_xtl_to_shll (inst);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
||||
/* aarch64-dis.c -- AArch64 disassembler.
|
||||
Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
|
||||
Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
|
||||
Contributed by ARM Ltd.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
@ -1478,6 +1478,20 @@ convert_extr_to_ror (aarch64_inst *inst)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
|
||||
is equivalent to:
|
||||
USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
|
||||
static int
|
||||
convert_shll_to_xtl (aarch64_inst *inst)
|
||||
{
|
||||
if (inst->operands[2].imm.value == 0)
|
||||
{
|
||||
inst->operands[2].type = AARCH64_OPND_NIL;
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Convert
|
||||
UBFM <Xd>, <Xn>, #<shift>, #63.
|
||||
to
|
||||
@ -1731,6 +1745,11 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
|
||||
return convert_movebitmask_to_mov (inst);
|
||||
case OP_ROR_IMM:
|
||||
return convert_extr_to_ror (inst);
|
||||
case OP_SXTL:
|
||||
case OP_SXTL2:
|
||||
case OP_UXTL:
|
||||
case OP_UXTL2:
|
||||
return convert_shll_to_xtl (inst);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* aarch64-gen.c -- Generate tables and routines for opcode lookup and
|
||||
instruction encoding and decoding.
|
||||
Copyright 2012 Free Software Foundation, Inc.
|
||||
Copyright 2012, 2013 Free Software Foundation, Inc.
|
||||
Contributed by ARM Ltd.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
@ -1242,7 +1242,7 @@ main (int argc, char **argv)
|
||||
print_divide_result (decoder_tree);
|
||||
|
||||
printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n");
|
||||
printf ("/* Copyright 2012 Free Software Foundation, Inc.\n\
|
||||
printf ("/* Copyright 2012, 2013 Free Software Foundation, Inc.\n\
|
||||
Contributed by ARM Ltd.\n\
|
||||
\n\
|
||||
This file is part of the GNU opcodes library.\n\
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* This file is automatically generated by aarch64-gen. Do not edit! */
|
||||
/* Copyright 2012 Free Software Foundation, Inc.
|
||||
/* Copyright 2012, 2013 Free Software Foundation, Inc.
|
||||
Contributed by ARM Ltd.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
@ -119,70 +119,73 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
static const unsigned op_enum_table [] =
|
||||
{
|
||||
0,
|
||||
648,
|
||||
649,
|
||||
650,
|
||||
652,
|
||||
653,
|
||||
654,
|
||||
655,
|
||||
656,
|
||||
657,
|
||||
651,
|
||||
652,
|
||||
658,
|
||||
659,
|
||||
681,
|
||||
682,
|
||||
660,
|
||||
661,
|
||||
655,
|
||||
656,
|
||||
662,
|
||||
663,
|
||||
685,
|
||||
686,
|
||||
689,
|
||||
695,
|
||||
696,
|
||||
699,
|
||||
701,
|
||||
702,
|
||||
691,
|
||||
692,
|
||||
695,
|
||||
697,
|
||||
698,
|
||||
687,
|
||||
688,
|
||||
701,
|
||||
703,
|
||||
741,
|
||||
742,
|
||||
743,
|
||||
744,
|
||||
705,
|
||||
707,
|
||||
745,
|
||||
746,
|
||||
747,
|
||||
748,
|
||||
12,
|
||||
510,
|
||||
511,
|
||||
768,
|
||||
770,
|
||||
772,
|
||||
752,
|
||||
771,
|
||||
769,
|
||||
259,
|
||||
499,
|
||||
509,
|
||||
508,
|
||||
750,
|
||||
505,
|
||||
502,
|
||||
495,
|
||||
494,
|
||||
501,
|
||||
504,
|
||||
506,
|
||||
507,
|
||||
764,
|
||||
766,
|
||||
768,
|
||||
748,
|
||||
767,
|
||||
765,
|
||||
259,
|
||||
495,
|
||||
505,
|
||||
504,
|
||||
746,
|
||||
501,
|
||||
498,
|
||||
491,
|
||||
490,
|
||||
497,
|
||||
500,
|
||||
502,
|
||||
503,
|
||||
756,
|
||||
125,
|
||||
522,
|
||||
525,
|
||||
528,
|
||||
523,
|
||||
760,
|
||||
526,
|
||||
614,
|
||||
529,
|
||||
532,
|
||||
527,
|
||||
530,
|
||||
618,
|
||||
160,
|
||||
161,
|
||||
162,
|
||||
163,
|
||||
416,
|
||||
583,
|
||||
420,
|
||||
587,
|
||||
314,
|
||||
316,
|
||||
336,
|
||||
338,
|
||||
};
|
||||
|
||||
/* Given the opcode enumerator OP, return the pointer to the corresponding
|
||||
|
||||
@ -1534,8 +1534,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
{"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
|
||||
{"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
|
||||
{"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
|
||||
{"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
|
||||
{"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
|
||||
{"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
|
||||
{"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
|
||||
{"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
|
||||
{"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
|
||||
{"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
|
||||
{"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
|
||||
{"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
|
||||
@ -1554,8 +1556,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
||||
{"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
|
||||
{"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
|
||||
{"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
|
||||
{"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
|
||||
{"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
|
||||
{"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
|
||||
{"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
|
||||
{"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
|
||||
{"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
|
||||
{"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
|
||||
{"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
|
||||
/* AdvSIMD TBL/TBX. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user