mirrors/binutils-gdb
0
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-27 03:54:41 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

drop XC16x bits

Browse Source 
Commit 04f096fb9e ("Move the xc16x target to the obsolete list") moved
the architecture from the "obsolete but still available" to the
"obsolete / support removed" list in config.bfd, making the architecture
impossible to enable (except maybe via "enable everything" options").

Note that I didn't touch */po/*.po{,t} on the assumption that these
would be updated by some (half)automatic means.
This commit is contained in:
Jan Beulich 2022-06-27 11:11:46 +02:00
parent 2d1388e73c
commit ddd7bf3e28
107 changed files with 7 additions and 18085 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
bfd/Makefile.am
View File

@ -171,7 +171,6 @@ ALL_MACHINES = \
cpu-vax.lo \
cpu-visium.lo \
cpu-wasm32.lo \
cpu-xc16x.lo \
cpu-xgate.lo \
cpu-xstormy16.lo \
cpu-xtensa.lo \
@ -255,7 +254,6 @@ ALL_MACHINES_CFILES = \
cpu-vax.c \
cpu-visium.c \
cpu-wasm32.c \
cpu-xc16x.c \
cpu-xgate.c \
cpu-xstormy16.c \
cpu-xtensa.c \
@ -352,7 +350,6 @@ BFD32_BACKENDS = \
elf32-vax.lo \
elf32-visium.lo \
elf32-wasm32.lo \
elf32-xc16x.lo \
elf32-xgate.lo \
elf32-xstormy16.lo \
elf32-xtensa.lo \
@ -485,7 +482,6 @@ BFD32_BACKENDS_CFILES = \
elf32-vax.c \
elf32-visium.c \
elf32-wasm32.c \
elf32-xc16x.c \
elf32-xgate.c \
elf32-xstormy16.c \
elf32-xtensa.c \

6
bfd/Makefile.in
View File

@ -633,7 +633,6 @@ ALL_MACHINES = \
cpu-vax.lo \
cpu-visium.lo \
cpu-wasm32.lo \
cpu-xc16x.lo \
cpu-xgate.lo \
cpu-xstormy16.lo \
cpu-xtensa.lo \
@ -717,7 +716,6 @@ ALL_MACHINES_CFILES = \
cpu-vax.c \
cpu-visium.c \
cpu-wasm32.c \
cpu-xc16x.c \
cpu-xgate.c \
cpu-xstormy16.c \
cpu-xtensa.c \
@ -815,7 +813,6 @@ BFD32_BACKENDS = \
elf32-vax.lo \
elf32-visium.lo \
elf32-wasm32.lo \
elf32-xc16x.lo \
elf32-xgate.lo \
elf32-xstormy16.lo \
elf32-xtensa.lo \
@ -948,7 +945,6 @@ BFD32_BACKENDS_CFILES = \
elf32-vax.c \
elf32-visium.c \
elf32-wasm32.c \
elf32-xc16x.c \
elf32-xgate.c \
elf32-xstormy16.c \
elf32-xtensa.c \
@ -1549,7 +1545,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-visium.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-wasm32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xc16x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xgate.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xtensa.Plo@am__quote@
@ -1632,7 +1627,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-vax.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-visium.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-wasm32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xc16x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xgate.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@

6
bfd/archures.c
View File

@ -487,10 +487,6 @@ DESCRIPTION
.#define bfd_mach_msp46 46
.#define bfd_mach_msp47 47
.#define bfd_mach_msp54 54
. bfd_arch_xc16x, {* Infineon's XC16X Series. *}
.#define bfd_mach_xc16x 1
.#define bfd_mach_xc16xl 2
.#define bfd_mach_xc16xs 3
. bfd_arch_xgate, {* Freescale XGATE. *}
.#define bfd_mach_xgate 1
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
@ -698,7 +694,6 @@ extern const bfd_arch_info_type bfd_visium_arch;
extern const bfd_arch_info_type bfd_wasm32_arch;
extern const bfd_arch_info_type bfd_xstormy16_arch;
extern const bfd_arch_info_type bfd_xtensa_arch;
extern const bfd_arch_info_type bfd_xc16x_arch;
extern const bfd_arch_info_type bfd_xgate_arch;
extern const bfd_arch_info_type bfd_z80_arch;
extern const bfd_arch_info_type bfd_z8k_arch;
@ -785,7 +780,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_wasm32_arch,
&bfd_xstormy16_arch,
&bfd_xtensa_arch,
&bfd_xc16x_arch,
&bfd_xgate_arch,
&bfd_z80_arch,
&bfd_z8k_arch,

10
bfd/bfd-in2.h
View File

@ -1824,10 +1824,6 @@ enum bfd_architecture
#define bfd_mach_msp46 46
#define bfd_mach_msp47 47
#define bfd_mach_msp54 54
bfd_arch_xc16x, /* Infineon's XC16X Series. */
#define bfd_mach_xc16x 1
#define bfd_mach_xc16xl 2
#define bfd_mach_xc16xs 3
bfd_arch_xgate, /* Freescale XGATE. */
#define bfd_mach_xgate 1
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
@ -5028,12 +5024,6 @@ then it may be truncated to 8 bits. */
BFD_RELOC_RELC,
/* Infineon Relocations. */
BFD_RELOC_XC16X_PAG,
BFD_RELOC_XC16X_POF,
BFD_RELOC_XC16X_SEG,
BFD_RELOC_XC16X_SOF,
/* Relocations used by VAX ELF. */
BFD_RELOC_VAX_GLOB_DAT,
BFD_RELOC_VAX_JMP_SLOT,

4
bfd/config.bfd
View File

@ -1431,10 +1431,6 @@ case "${targ}" in
targ_selvecs="wasm_vec"
;;
xc16x-*-elf)
targ_defvec=xc16x_elf32_vec
;;
xgate-*-*)
targ_defvec=xgate_elf32_vec
targ_selvecs="xgate_elf32_vec"

1
bfd/configure vendored
View File

@ -13587,7 +13587,6 @@ do
x86_64_pe_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pe_big_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pei_vec) tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
xc16x_elf32_vec) tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
xgate_elf32_vec) tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
xstormy16_elf32_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
xtensa_elf32_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;

1
bfd/configure.ac
View File

@ -665,7 +665,6 @@ do
x86_64_pe_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pe_big_vec) tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
x86_64_pei_vec) tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
xc16x_elf32_vec) tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
xgate_elf32_vec) tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
xstormy16_elf32_vec) tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
xtensa_elf32_be_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;

53
bfd/cpu-xc16x.c
View File

@ -1,53 +0,0 @@
/* BFD support for the Infineon XC16X Microcontroller.
Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems
This file is part of BFD, the Binary File Descriptor library.
Contributed by Anil Paranjpe(anilp1@kpitcummins.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#define N(BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
{ \
16, /* Bits in a word. */ \
BITS_ADDR, /* Bits in an address. */ \
8, /* Bits in a byte. */ \
bfd_arch_xc16x, \
NUMBER, \
"xc16x", \
PRINT, \
1, /* Section alignment power. */ \
DEFAULT, \
bfd_default_compatible, \
bfd_default_scan, \
bfd_arch_default_fill, \
NEXT, \
0 /* Maximum offset of a reloc from the start of an insn. */ \
}
const bfd_arch_info_type xc16xs_info_struct =
N (16, bfd_mach_xc16xs, "xc16xs", false, NULL);
const bfd_arch_info_type xc16xl_info_struct =
N (32, bfd_mach_xc16xl, "xc16xl", false, & xc16xs_info_struct);
const bfd_arch_info_type bfd_xc16x_arch =
N (16, bfd_mach_xc16x, "xc16x", true, & xc16xl_info_struct);

487
bfd/elf32-xc16x.c
View File

@ -1,487 +0,0 @@
/* Infineon XC16X-specific support for 16-bit ELF.
Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/xc16x.h"
#include "dwarf2.h"
#include "libiberty.h"
static reloc_howto_type xc16x_elf_howto_table [] =
{
/* This reloc does nothing. */
HOWTO (R_XC16X_NONE, /* type */
0, /* rightshift */
0, /* size */
0, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_NONE", /* name */
false, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
false), /* pcrel_offset */
/* An 8 bit absolute relocation. */
HOWTO (R_XC16X_ABS_8, /* type */
0, /* rightshift */
1, /* size */
8, /* bitsize */
false, /* pc_relative */
8, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_ABS_8", /* name */
true, /* partial_inplace */
0x0000, /* src_mask */
0x00ff, /* dst_mask */
false), /* pcrel_offset */
/* A 16 bit absolute relocation. */
HOWTO (R_XC16X_ABS_16, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_ABS_16", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
HOWTO (R_XC16X_ABS_32, /* type */
0, /* rightshift */
4, /* size */
32, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_ABS_32", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0xffffffff, /* dst_mask */
false), /* pcrel_offset */
/* A PC relative 8 bit relocation. */
HOWTO (R_XC16X_8_PCREL, /* type */
0, /* rightshift */
1, /* size */
8, /* bitsize */
true, /* pc_relative */
8, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_8_PCREL", /* name */
false, /* partial_inplace */
0x0000, /* src_mask */
0x00ff, /* dst_mask */
true), /* pcrel_offset */
/* Relocation regarding page number. */
HOWTO (R_XC16X_PAG, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_PAG", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
/* Relocation regarding page number. */
HOWTO (R_XC16X_POF, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_POF", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
/* Relocation regarding segment number. */
HOWTO (R_XC16X_SEG, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_SEG", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
/* Relocation regarding segment offset. */
HOWTO (R_XC16X_SOF, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_XC16X_SOF", /* name */
true, /* partial_inplace */
0x00000000, /* src_mask */
0x0000ffff, /* dst_mask */
false) /* pcrel_offset */
};
/* Map BFD reloc types to XC16X ELF reloc types. */
struct xc16x_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned int xc16x_reloc_val;
};
static const struct xc16x_reloc_map xc16x_reloc_map [] =
{
{ BFD_RELOC_NONE, R_XC16X_NONE },
{ BFD_RELOC_8, R_XC16X_ABS_8 },
{ BFD_RELOC_16, R_XC16X_ABS_16 },
{ BFD_RELOC_32, R_XC16X_ABS_32 },
{ BFD_RELOC_8_PCREL, R_XC16X_8_PCREL },
{ BFD_RELOC_XC16X_PAG, R_XC16X_PAG},
{ BFD_RELOC_XC16X_POF, R_XC16X_POF},
{ BFD_RELOC_XC16X_SEG, R_XC16X_SEG},
{ BFD_RELOC_XC16X_SOF, R_XC16X_SOF},
};
/* This function is used to search for correct relocation type from
howto structure. */
static reloc_howto_type *
xc16x_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = ARRAY_SIZE (xc16x_reloc_map); --i;)
if (xc16x_reloc_map [i].bfd_reloc_val == code)
return & xc16x_elf_howto_table [xc16x_reloc_map[i].xc16x_reloc_val];
return NULL;
}
static reloc_howto_type *
xc16x_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
if (xc16x_elf_howto_table[i].name != NULL
&& strcasecmp (xc16x_elf_howto_table[i].name, r_name) == 0)
return &xc16x_elf_howto_table[i];
return NULL;
}
static reloc_howto_type *
elf32_xc16x_rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED, unsigned r_type)
{
if (r_type < ARRAY_SIZE (xc16x_elf_howto_table))
return & xc16x_elf_howto_table[r_type];
return NULL;
}
/* For a particular operand this function is
called to finalise the type of relocation. */
static bool
elf32_xc16x_info_to_howto (bfd *abfd, arelent *bfd_reloc,
Elf_Internal_Rela *elf_reloc)
{
unsigned int r;
unsigned int i;
r = ELF32_R_TYPE (elf_reloc->r_info);
for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
if (xc16x_elf_howto_table[i].type == r)
{
bfd_reloc->howto = &xc16x_elf_howto_table[i];
return true;
}
/* xgettext:c-format */
_bfd_error_handler (_("%pB: unsupported relocation type %#x"), abfd, r);
bfd_set_error (bfd_error_bad_value);
return false;
}
static bfd_reloc_status_type
elf32_xc16x_final_link_relocate (unsigned long r_type,
bfd *input_bfd,
bfd *output_bfd ATTRIBUTE_UNUSED,
asection *input_section ATTRIBUTE_UNUSED,
bfd_byte *contents,
bfd_vma offset,
bfd_vma value,
bfd_vma addend,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
asection *sym_sec ATTRIBUTE_UNUSED,
int is_local ATTRIBUTE_UNUSED)
{
bfd_byte *hit_data = contents + offset;
bfd_vma val1;
switch (r_type)
{
case R_XC16X_NONE:
return bfd_reloc_ok;
case R_XC16X_ABS_16:
value += addend;
bfd_put_16 (input_bfd, value, hit_data);
return bfd_reloc_ok;
case R_XC16X_8_PCREL:
bfd_put_8 (input_bfd, value, hit_data);
return bfd_reloc_ok;
/* Following case is to find page number from actual
address for this divide value by 16k i.e. page size. */
case R_XC16X_PAG:
value += addend;
value /= 0x4000;
bfd_put_16 (input_bfd, value, hit_data);
return bfd_reloc_ok;
/* Following case is to find page offset from actual address
for this take modulo of value by 16k i.e. page size. */
case R_XC16X_POF:
value += addend;
value %= 0x4000;
bfd_put_16 (input_bfd, value, hit_data);
return bfd_reloc_ok;
/* Following case is to find segment number from actual
address for this divide value by 64k i.e. segment size. */
case R_XC16X_SEG:
value += addend;
value /= 0x10000;
bfd_put_16 (input_bfd, value, hit_data);
return bfd_reloc_ok;
/* Following case is to find segment offset from actual address
for this take modulo of value by 64k i.e. segment size. */
case R_XC16X_SOF:
value += addend;
value %= 0x10000;
bfd_put_16 (input_bfd, value, hit_data);
return bfd_reloc_ok;
case R_XC16X_ABS_32:
if (!strstr (input_section->name,".debug"))
{
value += addend;
val1 = value;
value %= 0x4000;
val1 /= 0x4000;
val1 = val1 << 16;
value += val1;
bfd_put_32 (input_bfd, value, hit_data);
}
else
{
value += addend;
bfd_put_32 (input_bfd, value, hit_data);
}
return bfd_reloc_ok;
default:
return bfd_reloc_notsupported;
}
}
static int
elf32_xc16x_relocate_section (bfd *output_bfd,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *relocs,
Elf_Internal_Sym *local_syms,
asection **local_sections)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes;
Elf_Internal_Rela *rel, *relend;
symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
sym_hashes = elf_sym_hashes (input_bfd);
rel = relocs;
relend = relocs + input_section->reloc_count;
for (; rel < relend; rel++)
{
unsigned int r_type;
unsigned long r_symndx;
Elf_Internal_Sym *sym;
asection *sec;
struct elf_link_hash_entry *h;
bfd_vma relocation;
/* This is a final link. */
r_symndx = ELF32_R_SYM (rel->r_info);
r_type = ELF32_R_TYPE (rel->r_info);
h = NULL;
sym = NULL;
sec = NULL;
if (r_symndx < symtab_hdr->sh_info)
{
sym = local_syms + r_symndx;
sec = local_sections[r_symndx];
relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
}
else
{
bool unresolved_reloc, warned, ignored;
RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
r_symndx, symtab_hdr, sym_hashes,
h, sec, relocation,
unresolved_reloc, warned, ignored);
}
if (sec != NULL && discarded_section (sec))
{
/* For relocs against symbols from removed linkonce sections,
or sections discarded by a linker script, we just want the
section contents cleared. Avoid any special processing. */
reloc_howto_type *howto;
howto = elf32_xc16x_rtype_to_howto (input_bfd, r_type);
RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
rel, 1, relend, howto, 0, contents);
}
if (bfd_link_relocatable (info))
continue;
elf32_xc16x_final_link_relocate (r_type, input_bfd, output_bfd,
input_section,
contents, rel->r_offset,
relocation, rel->r_addend,
info, sec, h == NULL);
}
return true;
}
static bool
elf32_xc16x_final_write_processing (bfd *abfd)
{
unsigned long val;
switch (bfd_get_mach (abfd))
{
default:
case bfd_mach_xc16x:
val = 0x1000;
break;
case bfd_mach_xc16xl:
val = 0x1001;
break;
case bfd_mach_xc16xs:
val = 0x1002;
break;
}
elf_elfheader (abfd)->e_flags |= val;
return _bfd_elf_final_write_processing (abfd);
}
static unsigned long
elf32_xc16x_mach (flagword flags)
{
switch (flags)
{
case 0x1000:
default:
return bfd_mach_xc16x;
case 0x1001:
return bfd_mach_xc16xl;
case 0x1002:
return bfd_mach_xc16xs;
}
}
static bool
elf32_xc16x_object_p (bfd *abfd)
{
bfd_default_set_arch_mach (abfd, bfd_arch_xc16x,
elf32_xc16x_mach (elf_elfheader (abfd)->e_flags));
return true;
}
#define ELF_ARCH bfd_arch_xc16x
#define ELF_MACHINE_CODE EM_XC16X
#define ELF_MAXPAGESIZE 0x100
#define TARGET_LITTLE_SYM xc16x_elf32_vec
#define TARGET_LITTLE_NAME "elf32-xc16x"
#define elf_backend_final_write_processing elf32_xc16x_final_write_processing
#define elf_backend_object_p elf32_xc16x_object_p
#define elf_backend_can_gc_sections 1
#define bfd_elf32_bfd_reloc_type_lookup xc16x_reloc_type_lookup
#define bfd_elf32_bfd_reloc_name_lookup xc16x_reloc_name_lookup
#define elf_info_to_howto elf32_xc16x_info_to_howto
#define elf_info_to_howto_rel elf32_xc16x_info_to_howto
#define elf_backend_relocate_section elf32_xc16x_relocate_section
#define elf_backend_rela_normal 1
#include "elf32-target.h"

4
bfd/libbfd.h
View File

@ -2791,10 +2791,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_XSTORMY16_FPTR16",
"BFD_RELOC_RELC",
"BFD_RELOC_XC16X_PAG",
"BFD_RELOC_XC16X_POF",
"BFD_RELOC_XC16X_SEG",
"BFD_RELOC_XC16X_SOF",
"BFD_RELOC_VAX_GLOB_DAT",
"BFD_RELOC_VAX_JMP_SLOT",
"BFD_RELOC_VAX_RELATIVE",

2
bfd/po/SRC-POTFILES.in
View File

@ -122,7 +122,6 @@ cpu-v850_rh850.c
cpu-vax.c
cpu-visium.c
cpu-wasm32.c
cpu-xc16x.c
cpu-xgate.c
cpu-xstormy16.c
cpu-xtensa.c
@ -231,7 +230,6 @@ elf32-v850.h
elf32-vax.c
elf32-visium.c
elf32-wasm32.c
elf32-xc16x.c
elf32-xgate.c
elf32-xstormy16.c
elf32-xtensa.c

11
bfd/reloc.c
View File

@ -6289,17 +6289,6 @@ ENUMDOC
Self-describing complex relocations.
COMMENT
ENUM
BFD_RELOC_XC16X_PAG
ENUMX
BFD_RELOC_XC16X_POF
ENUMX
BFD_RELOC_XC16X_SEG
ENUMX
BFD_RELOC_XC16X_SOF
ENUMDOC
Infineon Relocations.
ENUM
BFD_RELOC_VAX_GLOB_DAT
ENUMX

3
bfd/targets.c
View File

@ -933,7 +933,6 @@ extern const bfd_target x86_64_mach_o_vec;
extern const bfd_target x86_64_pe_vec;
extern const bfd_target x86_64_pe_big_vec;
extern const bfd_target x86_64_pei_vec;
extern const bfd_target xc16x_elf32_vec;
extern const bfd_target xgate_elf32_vec;
extern const bfd_target xstormy16_elf32_vec;
extern const bfd_target xtensa_elf32_be_vec;
@ -1344,8 +1343,6 @@ static const bfd_target * const _bfd_target_vector[] =
&x86_64_pei_vec,
#endif
&xc16x_elf32_vec,
&xgate_elf32_vec,
&xstormy16_elf32_vec,

14
binutils/readelf.c
View File

@ -163,7 +163,6 @@
#include "elf/visium.h"
#include "elf/wasm32.h"
#include "elf/x86-64.h"
#include "elf/xc16x.h"
#include "elf/xgate.h"
#include "elf/xstormy16.h"
#include "elf/xtensa.h"
@ -1882,11 +1881,6 @@ dump_relocations (Filedata * filedata,
rtype = elf_metag_reloc_type (type);
break;
case EM_XC16X:
case EM_C166:
rtype = elf_xc16x_reloc_type (type);
break;
case EM_TI_C6000:
rtype = elf_tic6x_reloc_type (type);
break;
@ -14343,9 +14337,6 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_L1OM:
case EM_K1OM:
return reloc_type == 10; /* R_X86_64_32. */
case EM_XC16X:
case EM_C166:
return reloc_type == 3; /* R_XC16C_ABS_32. */
case EM_XGATE:
return reloc_type == 4; /* R_XGATE_32. */
case EM_XSTORMY16:
@ -14607,9 +14598,6 @@ is_16bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
return reloc_type == 2; /* R_C6000_ABS16. */
case EM_VISIUM:
return reloc_type == 2; /* R_VISIUM_16. */
case EM_XC16X:
case EM_C166:
return reloc_type == 2; /* R_XC16C_ABS_16. */
case EM_XGATE:
return reloc_type == 3; /* R_XGATE_16. */
case EM_Z80:
@ -14811,7 +14799,6 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_ARC_COMPACT2: /* R_ARC_NONE. */
case EM_ARC_COMPACT: /* R_ARC_NONE. */
case EM_ARM: /* R_ARM_NONE. */
case EM_C166: /* R_XC16X_NONE. */
case EM_CRIS: /* R_CRIS_NONE. */
case EM_FT32: /* R_FT32_NONE. */
case EM_IA_64: /* R_IA64_NONE. */
@ -14837,7 +14824,6 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_TILEPRO: /* R_TILEPRO_NONE. */
case EM_TI_C6000:/* R_C6000_NONE. */
case EM_X86_64: /* R_X86_64_NONE. */
case EM_XC16X:
case EM_Z80: /* R_Z80_NONE. */
case EM_WEBASSEMBLY: /* R_WASM32_NONE. */
return reloc_type == 0;

3146
cpu/xc16x.cpu
View File

File diff suppressed because it is too large Load Diff

290
cpu/xc16x.opc
View File

@ -1,290 +0,0 @@
/* XC16X opcode support. -*- C -*-
Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
from Infineon Systems, GMBH , Germany.
This file is part of the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* This file is an addendum to xc16x.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
Such things aren't really part of the specification of the cpu, per se,
so .cpu files provide the general framework and .opc files handle the
nitty-gritty details as necessary.
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
/* -- */
/* -- opc.c */
/* -- */
/* -- asm.c */
/* Handle '#' prefixes (i.e. skip over them). */
static const char *
parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (**strp == '#')
{
++*strp;
return NULL;
}
return _("Missing '#' prefix");
}
/* Handle '.' prefixes (i.e. skip over them). */
static const char *
parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (**strp == '.')
{
++*strp;
return NULL;
}
return _("Missing '.' prefix");
}
/* Handle 'pof:' prefixes (i.e. skip over them). */
static const char *
parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (strncasecmp (*strp, "pof:", 4) == 0)
{
*strp += 4;
return NULL;
}
return _("Missing 'pof:' prefix");
}
/* Handle 'pag:' prefixes (i.e. skip over them). */
static const char *
parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (strncasecmp (*strp, "pag:", 4) == 0)
{
*strp += 4;
return NULL;
}
return _("Missing 'pag:' prefix");
}
/* Handle 'sof' prefixes (i.e. skip over them). */
static const char *
parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (strncasecmp (*strp, "sof:", 4) == 0)
{
*strp += 4;
return NULL;
}
return _("Missing 'sof:' prefix");
}
/* Handle 'seg' prefixes (i.e. skip over them). */
static const char *
parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (strncasecmp (*strp, "seg:", 4) == 0)
{
*strp += 4;
return NULL;
}
return _("Missing 'seg:' prefix");
}
/* -- */
/* -- dis.c */
/* Print an operand with a "." prefix.
NOTE: This prints the operand in hex.
??? This exists to maintain disassembler compatibility with previous
versions. Ideally we'd print the "." in print_dot. */
static void
print_with_dot_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, ".");
info->fprintf_func (info->stream, "0x%lx", value);
}
/* Print an operand with a "#pof:" prefix.
NOTE: This prints the operand as an address.
??? This exists to maintain disassembler compatibility with previous
versions. Ideally we'd print "#pof:" in print_pof. */
static void
print_with_pof_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
bfd_vma value,
unsigned attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "#pof:");
info->fprintf_func (info->stream, "0x%lx", (long) value);
}
/* Print an operand with a "#pag:" prefix.
NOTE: This prints the operand in hex.
??? This exists to maintain disassembler compatibility with previous
versions. Ideally we'd print "#pag:" in print_pag. */
static void
print_with_pag_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "#pag:");
info->fprintf_func (info->stream, "0x%lx", value);
}
/* Print a 'pof:' prefix to an operand. */
static void
print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
}
/* Print a 'pag:' prefix to an operand. */
static void
print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
}
/* Print a 'sof:' prefix to an operand. */
static void
print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "sof:");
}
/* Print a 'seg:' prefix to an operand. */
static void
print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "seg:");
}
/* Print a '#' prefix to an operand. */
static void
print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
info->fprintf_func (info->stream, "#");
}
/* Print a '.' prefix to an operand. */
static void
print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
}
/* -- */

2
gas/Makefile.am
View File

@ -200,7 +200,6 @@ TARGET_CPU_CFILES = \
config/tc-visium.c \
config/tc-wasm32.c \
config/tc-xstormy16.c \
config/tc-xc16x.c \
config/tc-xgate.c \
config/tc-xtensa.c \
config/tc-z80.c \
@ -274,7 +273,6 @@ TARGET_CPU_HFILES = \
config/tc-visium.h \
config/tc-wasm32.h \
config/tc-xstormy16.h \
config/tc-xc16x.h \
config/tc-xgate.h \
config/tc-xtensa.h \
config/tc-z80.h \

5
gas/Makefile.in
View File

@ -678,7 +678,6 @@ TARGET_CPU_CFILES = \
config/tc-visium.c \
config/tc-wasm32.c \
config/tc-xstormy16.c \
config/tc-xc16x.c \
config/tc-xgate.c \
config/tc-xtensa.c \
config/tc-z80.c \
@ -752,7 +751,6 @@ TARGET_CPU_HFILES = \
config/tc-visium.h \
config/tc-wasm32.h \
config/tc-xstormy16.h \
config/tc-xc16x.h \
config/tc-xgate.h \
config/tc-xtensa.h \
config/tc-z80.h \
@ -1203,8 +1201,6 @@ config/tc-wasm32.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xstormy16.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xc16x.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xgate.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-xtensa.$(OBJEXT): config/$(am__dirstamp) \
@ -1410,7 +1406,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-visium.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-wasm32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xc16x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xgate.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xstormy16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-xtensa.Po@am__quote@

350
gas/config/tc-xc16x.c
View File

@ -1,350 +0,0 @@
/* tc-xc16x.c -- Assembler for the Infineon XC16X.
Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
#include "symcat.h"
#include "opcodes/xc16x-desc.h"
#include "opcodes/xc16x-opc.h"
#include "cgen.h"
#include "dwarf2dbg.h"
#ifdef OBJ_ELF
#include "elf/xc16x.h"
#endif
/* Structure to hold all of the different components describing
an individual instruction. */
typedef struct
{
const CGEN_INSN * insn;
const CGEN_INSN * orig_insn;
CGEN_FIELDS fields;
#if CGEN_INT_INSN_P
CGEN_INSN_INT buffer [1];
#define INSN_VALUE(buf) (*(buf))
#else
unsigned char buffer [CGEN_MAX_INSN_SIZE];
#define INSN_VALUE(buf) (buf)
#endif
char * addr;
fragS * frag;
int num_fixups;
fixS * fixups [GAS_CGEN_MAX_FIXUPS];
int indices [MAX_OPERAND_INSTANCES];
}
xc16x_insn;
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
const char line_separator_chars[] = "";
const char EXP_CHARS[] = "eE";
const char FLT_CHARS[] = "dD";
#define XC16X_SHORTOPTS ""
const char * md_shortopts = XC16X_SHORTOPTS;
struct option md_longopts[] =
{
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
static void
xc16xlmode (int arg ATTRIBUTE_UNUSED)
{
if (stdoutput != NULL)
if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xl))
as_warn (_("could not set architecture and machine"));
}
static void
xc16xsmode (int arg ATTRIBUTE_UNUSED)
{
if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xs))
as_warn (_("could not set architecture and machine"));
}
static void
xc16xmode (int arg ATTRIBUTE_UNUSED)
{
if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16x))
as_warn (_("could not set architecture and machine"));
}
/* The target specific pseudo-ops which we support. */
const pseudo_typeS md_pseudo_table[] =
{
{ "word", cons, 2 },
{"xc16xl", xc16xlmode, 0},
{"xc16xs", xc16xsmode, 0},
{"xc16x", xc16xmode, 0},
{ NULL, NULL, 0 }
};
void
md_begin (void)
{
/* Initialize the `cgen' interface. */
/* Set the machine number and endian. */
gas_cgen_cpu_desc = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
CGEN_CPU_OPEN_ENDIAN,
CGEN_ENDIAN_LITTLE,
CGEN_CPU_OPEN_END);
xc16x_cgen_init_asm (gas_cgen_cpu_desc);
/* This is a callback from cgen to gas to parse operands. */
cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
}
void
md_assemble (char *str)
{
xc16x_insn insn;
char *errmsg;
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
insn.insn = xc16x_cgen_assemble_insn
(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
if (!insn.insn)
{
as_bad ("%s", errmsg);
return;
}
/* Doesn't really matter what we pass for RELAX_P here. */
gas_cgen_finish_insn (insn.insn, insn.buffer,
CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
}
/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
Returns BFD_RELOC_NONE if no reloc type can be found.
*FIXP may be modified if desired. */
bfd_reloc_code_real_type
md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
const CGEN_OPERAND *operand,
fixS *fixP)
{
switch (operand->type)
{
case XC16X_OPERAND_REL:
/* ??? Adjust size? */
fixP->fx_where += 1;
fixP->fx_pcrel = 1;
return BFD_RELOC_8_PCREL;
case XC16X_OPERAND_CADDR:
fixP->fx_size = 2;
fixP->fx_where += 2;
return BFD_RELOC_16;
case XC16X_OPERAND_UIMM7:
/* ??? Adjust size? */
fixP->fx_where += 1;
fixP->fx_pcrel = 1;
return BFD_RELOC_8_PCREL;
case XC16X_OPERAND_UIMM16:
case XC16X_OPERAND_MEMORY:
fixP->fx_size = 2;
fixP->fx_where += 2;
return BFD_RELOC_16;
case XC16X_OPERAND_UPOF16:
fixP->fx_size = 2;
fixP->fx_where += 2;
return BFD_RELOC_XC16X_POF;
case XC16X_OPERAND_UPAG16:
fixP->fx_size = 2;
fixP->fx_where += 2;
return BFD_RELOC_XC16X_PAG;
case XC16X_OPERAND_USEG8:
/* ??? This is an 8 bit field, why the 16 bit reloc? */
fixP->fx_where += 1;
return BFD_RELOC_XC16X_SEG;
case XC16X_OPERAND_USEG16:
case XC16X_OPERAND_USOF16:
fixP->fx_size = 2;
fixP->fx_where += 2;
return BFD_RELOC_XC16X_SOF;
default : /* Avoid -Wall warning. */
break;
}
return BFD_RELOC_NONE;
}
/* Write a value out to the object file, using the appropriate endianness. */
void
md_number_to_chars (char * buf, valueT val, int n)
{
number_to_chars_littleendian (buf, val, n);
}
void
md_show_usage (FILE * stream)
{
fprintf (stream, _(" XC16X specific command line options:\n"));
}
int
md_parse_option (int c ATTRIBUTE_UNUSED,
const char *arg ATTRIBUTE_UNUSED)
{
return 0;
}
const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, false);
}
valueT
md_section_align (segT segment, valueT size)
{
int align = bfd_section_alignment (segment);
return ((size + (1 << align) - 1) & -(1 << align));
}
symbolS *
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
{
return NULL;
}
int
md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
segT segment_type ATTRIBUTE_UNUSED)
{
printf (_("call to md_estimate_size_before_relax \n"));
abort ();
}
long
md_pcrel_from (fixS *fixP)
{
long temp_val;
temp_val=fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
return temp_val;
}
long
md_pcrel_from_section (fixS *fixP, segT sec)
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
|| S_GET_SEGMENT (fixP->fx_addsy) != sec
|| S_IS_EXTERNAL (fixP->fx_addsy)
|| S_IS_WEAK (fixP->fx_addsy)))
{
return 0;
}
return md_pcrel_from (fixP);
}
arelent *
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
{
arelent *rel;
bfd_reloc_code_real_type r_type;
if (fixp->fx_subsy)
{
if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
|| S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
{
as_bad_subtract (fixp);
return NULL;
}
}
rel = XNEW (arelent);
rel->sym_ptr_ptr = XNEW (asymbol *);
*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
rel->addend = fixp->fx_offset;
r_type = fixp->fx_r_type;
#define DEBUG 0
#if DEBUG
fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type));
fflush (stderr);
#endif
rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
if (rel->howto == NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
_("Cannot represent relocation type %s"),
bfd_get_reloc_code_name (r_type));
return NULL;
}
return rel;
}
void
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
{
/* FIXME: This absolute nonsense apparently is to make relative
jumps "work". Of course, it breaks any other type of fixup. */
if (!strstr (seg->name,".debug"))
{
if (*valP < 128)
*valP /= 2;
if (*valP>268435455)
{
*valP = *valP * (-1);
*valP /= 2;
*valP = 256 - (*valP);
}
}
gas_cgen_md_apply_fix (fixP, valP, seg);
return;
}
void
md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
fragS *fragP ATTRIBUTE_UNUSED)
{
printf (_("call to md_convert_frag \n"));
abort ();
}

59
gas/config/tc-xc16x.h
View File

@ -1,59 +0,0 @@
/* This file is tc-xc16x.h
Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#define TC_XC16X
#define TARGET_BYTES_BIG_ENDIAN 0
#define TARGET_ARCH bfd_arch_xc16x
#ifdef OBJ_ELF
#define TARGET_FORMAT "elf32-xc16x"
#define LOCAL_LABEL_PREFIX '.'
#define LOCAL_LABEL(NAME) (NAME[0] == '.' && NAME[1] == 'L')
#define FAKE_LABEL_NAME ".L0\001"
#endif
struct fix;
struct internal_reloc;
#define WORKING_DOT_WORD
#define BFD_ARCH bfd_arch_xc16x
#define TC_COUNT_RELOC(x) 1
#define IGNORE_NONSTANDARD_ESCAPES
#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
extern void tc_reloc_mangle (struct fix *, struct internal_reloc *, bfd_vma);
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
/* Minimum instruction is of 16 bits. */
#define DWARF2_LINE_MIN_INSN_LENGTH 2
#define DO_NOT_STRIP 0
#define LISTING_HEADER "Infineon XC16X GAS "
#define NEED_FX_R_TYPE 1
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
#define md_operand(x)

4
gas/configure vendored
View File

@ -12513,10 +12513,6 @@ $as_echo "$with_priv_spec" >&6; }
using_cgen=yes
;;
xc16x)
using_cgen=yes
;;
xtensa)
f=config/xtensa-relax.o
case " $extra_objects " in

4
gas/configure.ac
View File

@ -646,10 +646,6 @@ changequote([,])dnl
using_cgen=yes
;;
xc16x)
using_cgen=yes
;;
xtensa)
f=config/xtensa-relax.o
case " $extra_objects " in

1
gas/doc/all.texi
View File

@ -46,7 +46,6 @@
@set LM32
@set M32C
@set M32R
@set xc16x
@set M68HC11
@set S12Z
@set M680X0

80
gas/doc/c-xc16x.texi
View File

@ -1,80 +0,0 @@
@c Copyright (C) 2006-2022 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node xc16x-Dependent
@chapter Infineon xc16x Dependent Features
@cindex xc16x support
@menu
* xc16x Directives:: xc16x Machine Directives
* xc16x Syntax:: xc16x Syntax
@end menu
@node xc16x Directives
@section xc16x Machine Directives
The xc16x version of the assembler supports the following machine
directives:
@table @code
@cindex @code{align} directive, xc16x
@item .align
This directive aligns the section program counter on the next 2-byte
boundary.
@cindex @code{byte} directive, xc16x
@item .byte @var{expr}
This directive assembles a half-word (8-bit) constant.
@cindex @code{word} directive, xc16x
@item .word @var{expr}
This assembles a word (16-bit) constant.
@cindex @code{ascii} directive, xc16x
@item .ascii "@var{ascii}"
This directive used for copying @var{str} into the object file.
The string is terminated with a null byte.
@cindex @code{set} directive, xc16x
@item .set @var{symbol}, @var{value}
This directive creates a symbol named @var{symbol} which is an alias for
another symbol (possibly not yet defined). This should not be confused
with the mnemonic @code{set}, which is a legitimate xc16x instruction.
@cindex @code{bss} directive, xc16x
@item .bss @var{symbol}, @var{length}
Reserve @var{length} bytes in the bss section for a local @var{symbol},
aligned to the power of two specified by @var{align}. @var{length} and
@var{align} must be positive absolute expressions. This directive
differs from @samp{.lcomm} only in that it permits you to specify
an alignment.
@end table
@node xc16x Syntax
@section xc16x Syntax
@menu
* xc16x-Chars:: Special Characters
@end menu
@node xc16x-Chars
@subsection Special Characters
@cindex line comment character, xc16x
@cindex xc16c line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
@cindex line separator, xc16x
@cindex statement separator, xc16x
@cindex xc16x line separator
The XC16X assembler does not support a line separator character.

2
gas/po/POTFILES.in
View File

@ -171,8 +171,6 @@ config/tc-visium.c
config/tc-visium.h
config/tc-wasm32.c
config/tc-wasm32.h
config/tc-xc16x.c
config/tc-xc16x.h
config/tc-xgate.c
config/tc-xgate.h
config/tc-xstormy16.c

17
gas/testsuite/gas/xc16x/add.s
View File

@ -1,17 +0,0 @@
.text
xc16x_add:
add r0,r1
add r0,[r1]
add r0,[r1+]
add r0,#3
add r0,#1234
add r0,0xffed
add 0xffed,r0

92
gas/testsuite/gas/xc16x/add_test.s
View File

@ -1,92 +0,0 @@
.text
_start:
add r0,r1
add r0,r2
add r0,r3
add r0,r4
add r0,r5
add r0,r6
add r0,r7
add r0,r8
add r0,r9
add r0,r10
add r0,r11
add r0,r12
add r0,r13
add r0,r14
add r0,r15
add r1,r0
add r1,r2
add r1,r3
add r1,r4
add r1,r5
add r1,r6
add r1,r7
add r1,r8
add r1,r9
add r1,r10
add r1,r11
add r1,r12
add r1,r13
add r1,r14
add r1,r15
add r2,r0
add r2,r1
add r2,r3
add r2,r4
add r2,r5
add r2,r6
add r2,r7
add r2,r8
add r2,r9
add r2,r10
add r2,r11
add r2,r12
add r2,r13
add r2,r14
add r2,r15
add r3,r0
add r3,r1
add r3,r2
add r3,r4
add r3,r5
add r3,r6
add r3,r7
add r3,r8
add r3,r9
add r3,r10
add r3,r11
add r3,r12
add r3,r13
add r3,r14
add r3,r15
add r0,[r1]
add r0,[r1+]
add r0,#3
add r0,#0xffff
add r0,0xffff
add 0xffff,r0
addb rl0,rh0
addb rl0[r0]
addb rl0,#3
addb rl0,#0xff
addb r0,0xff10
addb 0xff10,r0
addc r0,r1
addc r0,[r1]
addc r0,#3
addc r0,#0xff12
addc r0,#0xff12
addc r0,0xff12
addc 0xff12,r0
addcb rl0,#3
addcb rl0,#0xff
addcb r0,0xff10
addcb 0xff10,r0

11
gas/testsuite/gas/xc16x/addb.s
View File

@ -1,11 +0,0 @@
.section .text
.global _fun
xc16x_add:
addb rl0,rl1
addb rl0,[r1]
addb rl0,[r1+]
addb rl0,#0x2
addb rl0,#0x33
addb rl0,0x2387
addb 0x2387,rl0

11
gas/testsuite/gas/xc16x/addc.s
View File

@ -1,11 +0,0 @@
.section .text
.global _fun
xc16x_add:
addc r0,r1
addc r0,[r1]
addc r0,[r1+]
addc r0,#0x34
addc r0,#0x3456
addc r0,0x2387
addc 0x2387,r0

17
gas/testsuite/gas/xc16x/addcb.s
View File

@ -1,17 +0,0 @@
.section .text
.global _fun
xc16x_add:
addcb rl0,rl1
addcb rl0,[r1]
addcb rl0,[r1+]
addcb rl0,#0x02
addcb rl0,#0x23
addcb 0x2387,rl0

14
gas/testsuite/gas/xc16x/and.s
View File

@ -1,14 +0,0 @@
.section .text
.global _fun
xc16x_and:
and r0,r1
and r0,[r1]
and r0,[r1+]
and r0,#3
and r0,#0xfcbe
and r0,0x0230
and 0x320,r0

10
gas/testsuite/gas/xc16x/andb.s
View File

@ -1,10 +0,0 @@
.section .text
.global _fun
xc16x_andb:
andb rl0,rl1
andb rl0,[r1]
andb rl0,[r1+]
andb rl0,#3
andb rl0,#0xbe
andb rl0,0x0230
andb 0x320,rl0

4
gas/testsuite/gas/xc16x/bfldl.s
View File

@ -1,4 +0,0 @@
.text
xc16x_bfldl:
BFLDL r0,#0x87,#0x0e
BFLDH r0,#0xff,#0x0e

11
gas/testsuite/gas/xc16x/bit.s
View File

@ -1,11 +0,0 @@
.text
xc16x_bit:
bclr r0.1
bset r0.1
bmov r0.2,r0.1
bmovn r0.3,r0.2
band r0.1,r0.4
bor r0.1,r0.2
bxor r0.1,r0.2
bcmp r0.1,r0.2

24
gas/testsuite/gas/xc16x/calla.s
View File

@ -1,24 +0,0 @@
.text
xc16x_calla:
calla cc_uc,0xaaaa
calla cc_z,0xaaaa
calla cc_nz,0xaaaa
calla cc_v,0xaaaa
calla cc_nv,0xaaaa
calla cc_n,0xaaaa
calla cc_nn,0xaaaa
calla cc_c,0xaaaa
calla cc_nc,0xaaaa
calla cc_eq,0xaaaa
calla cc_ne,0xaaaa
calla cc_ult,0xaaaa
calla cc_ule,0xaaaa
calla cc_uge,0xaaaa
calla cc_ugt,0xaaaa
calla cc_sle,0xaaaa
calla cc_sge,0xaaaa
calla cc_sgt,0xaaaa
calla cc_net,0xaaaa
calla cc_slt,0xaaaa

21
gas/testsuite/gas/xc16x/calli.s
View File

@ -1,21 +0,0 @@
.text
xc16x_calli:
calli cc_uc,[r1]
calli cc_z,[r1]
calli cc_nz,[r1]
calli cc_v,[r1]
calli cc_nv,[r1]
calli cc_n,[r1]
calli cc_nn,[r1]
calli cc_c,[r1]
calli cc_nc,[r1]
calli cc_eq,[r1]
calli cc_ne,[r1]
calli cc_ult,[r1]
calli cc_ule,[r1]
calli cc_uge,[r1]
calli cc_ugt,[r1]
calli cc_sle,[r1]
calli cc_sge,[r1]
calli cc_net,[r1]
calli cc_slt,[r1]

9
gas/testsuite/gas/xc16x/cmp.s
View File

@ -1,9 +0,0 @@
.text
xc16x_cmp:
cmp r0,r1
cmp r0,[r1]
cmp r0,[r1+]
cmp r0,#3
cmp r0,#0x0234
cmp r0,0x3452

45
gas/testsuite/gas/xc16x/cmp_test.s
View File

@ -1,45 +0,0 @@
.text
cmp r0,r1
cmp r0,[r1]
cmp r0,[r1+]
cmp r0,#3
cmp r0,#0x0234
cmp r0,0x3452
cmp r0,r1
cmp r0,[r1]
cmp r0,[r1+]
cmp r0,#3
cmp r0,#0xcdef
cmp r0,0xcdef
cmpb rl0,rl1
cmpb rl0,[r1]
cmpb rl0,[r1+]
cmpb rl0,#3
cmpb rl0,#cd
cmpb rl0,0x0234
cmpb rl0,rl1
cmpb rl0,[r1]
cmpb rl0,[r1+]
cmpb rl0,#3
cmpb rl0,#cd
cmpb rl0,0xcdef
cmpd1 r0,#0x0f
cmpd1 r0,#0x0fccb
cmpd1 r0,0xffcb
cmpd2 r0,#0x0f
cmpd2 r0,#0x0fccb
cmpd2 r0,0xffcb
cmpi1 r0,#0x0f
cmpi1 r0,#0x0fccb
cmpi1 r0,0xffcb
cmpi2 r0,#0x0f
cmpi2 r0,#0x0fccb
cmpi2 r0,0xffcb

8
gas/testsuite/gas/xc16x/cmpb.s
View File

@ -1,8 +0,0 @@
.text
xc16x_cmpb:
cmpb rl0,rl1
cmpb rl0,[r1]
cmpb rl0,[r1+]
cmpb rl0,#3
cmpb rl0,#34
cmpb rl0,0x0234

18
gas/testsuite/gas/xc16x/cmpi.s
View File

@ -1,18 +0,0 @@
.section .text
.global _fun
xc16x_cmpd:
cmpd1 r0,#0x0f
cmpd1 r0,#0x0fccb
cmpd1 r0,0xffcb
cmpd2 r0,#0x0f
cmpd2 r0,#0x0fccb
cmpd2 r0,0xffcb
cmpi1 r0,#0x0f
cmpi1 r0,#0x0fccb
cmpi1 r0,0xffcb
cmpi2 r0,#0x0f
cmpi2 r0,#0x0fccb
cmpi2 r0,0xffcb

7
gas/testsuite/gas/xc16x/cpl.s
View File

@ -1,7 +0,0 @@
.section .text
.global _fun
xc16x_cpl_cplb:
cpl r0
cplb rl0

8
gas/testsuite/gas/xc16x/div.s
View File

@ -1,8 +0,0 @@
.section .text
.global _fun
xc16x_div:
div r0
divl r0
divlu r0
divu r0

23
gas/testsuite/gas/xc16x/jmpa.s
View File

@ -1,23 +0,0 @@
.text
xc16x_jmpa:
jmpa cc_UC,0xaaaa
jmpa cc_Z,0xaaaa
jmpa cc_NZ,0xaaaa
jmpa cc_V,0xaaaa
jmpa cc_NV,0xaaaa
jmpa cc_N,0xaaaa
jmpa cc_NN,0xaaaa
jmpa cc_ULT,0xaaaa
jmpa cc_UGE,0xaaaa
jmpa cc_Z,0xaaaa
jmpa cc_NZ,0xaaaa
jmpa cc_ULT,0xaaaa
jmpa cc_ULE,0xaaaa
jmpa cc_UGE,0xaaaa
jmpa cc_UGT,0xaaaa
jmpa cc_SLE,0xaaaa
jmpa cc_SGE,0xaaaa
jmpa cc_SGT,0xaaaa
jmpa cc_NET,0xaaaa

24
gas/testsuite/gas/xc16x/jmpi.s
View File

@ -1,24 +0,0 @@
.section .text
.global _fun
xc16x_jmpi:
jmpi cc_UC, [r7]
jmpi cc_z, [r7]
jmpi cc_NZ, [r7]
jmpi cc_V, [r7]
jmpi cc_NV, [r7]
jmpi cc_N, [r7]
jmpi cc_NN, [r7]
jmpi cc_C, [r7]
jmpi cc_NC, [r7]
jmpi cc_EQ, [r7]
jmpi cc_NE, [r7]
jmpi cc_ULT,[r7]
jmpi cc_ULE,[r7]
jmpi cc_UGE,[r7]
jmpi cc_UGT,[r7]
jmpi cc_SLE,[r7]
jmpi cc_SGE,[r7]
jmpi cc_SGT,[r7]
jmpi cc_NET,[r7]

25
gas/testsuite/gas/xc16x/jmpr.s
View File

@ -1,25 +0,0 @@
.section .text
.global _fun
xc16x_jmpr:
jmpr cc_uc, xc16x_jmpr
jmpr cc_z, xc16x_jmpr
jmpr cc_nz, xc16x_jmpr
jmpr cc_v, xc16x_jmpr
jmpr cc_nv, xc16x_jmpr
jmpr cc_n, xc16x_jmpr
jmpr cc_nn, xc16x_jmpr
jmpr cc_c, xc16x_jmpr
jmpr cc_nc, xc16x_jmpr
jmpr cc_eq, xc16x_jmpr
jmpr cc_ne, xc16x_jmpr
jmpr cc_ult,xc16x_jmpr
jmpr cc_ule,xc16x_jmpr
jmpr cc_uge,xc16x_jmpr
jmpr cc_ugt,xc16x_jmpr
jmpr cc_sle,xc16x_jmpr
jmpr cc_sge,xc16x_jmpr
jmpr cc_sgt,xc16x_jmpr
jmpr cc_net,xc16x_jmpr
jmpr cc_slt,xc16x_jmpr

20
gas/testsuite/gas/xc16x/mov.s
View File

@ -1,20 +0,0 @@
.section .text
.global _fun
xc16x_mov:
mov r0,r1
mov r0,#02
mov r0,#0xfcbe
mov r0,[r1]
mov r0,[r1+]
mov [r0],r1
mov [-r0],r1
mov [r0],[r1]
mov [r0+],[r1]
mov [r0],[r1+]
mov r0,[r0+#0xffcb]
mov [r0+#0xffcb],r0
mov [r0],0xffcb
mov 0xffcb,[r0]
mov r0,0xffcb
mov 0xffcb,r0

85
gas/testsuite/gas/xc16x/mov_test.s
View File

@ -1,85 +0,0 @@
.xc16x
mov r0,r1
mov r0,#02
mov r0,#0x0001
mov r0,[r1]
mov r0,[r1+]
mov [r0],r1
mov [-r0],r1
mov [r0],[r1]
mov [r0+],[r1]
mov [r0],[r1+]
mov r0,[r0+#0x0001]
mov [r0+#0x0001],r0
mov [r0],0x0001
mov 0x0001,[r0]
mov r0,0x0001
mov 0x0001,r0
mov r0,r1
mov r0,#02
mov r0,#0xffff
mov r0,[r1]
mov r0,[r1+]
mov [r0],r1
mov [-r0],r1
mov [r0],[r1]
mov [r0+],[r1]
mov [r0],[r1+]
mov r0,[r0+#0xffff]
mov [r0+#0xffff],r0
mov [r0],0xffff
mov 0xffff,[r0]
mov r0,0xffff
mov 0xffff,r0
movb rl0,r2
movb rl0,#0x12
movb r3,[r2]
movb rl0,[r2+]
movb [-r2],rl0
movb [r3],[r2+]
movb [r3],[r2]
movb [r2+],[r3]
movb [r2],[r3+]
movb rl0,[r3+#0x1234]
movb [r3+#0x1234],rl0
movb [r3],0x1234
movb [r3],0x1234
movb 0x1234,[r3]
movb rl0,0x12
movb 0x12,rl0
movb rl0,r2
movb rl0,#0xff
movb r3,[r2]
movb rl0,[r2+]
movb [-r2],rl0
movb [r3],[r2+]
movb [r3],[r2]
movb [r2+],[r3]
movb [r2],[r3+]
movb rl0,[r3+#0xffff]
movb [r3+#0xffff],rl0
movb [r3],0xffff
movb [r3],0xffff
movb 0xffff,[r3]
movb rl0,0xff
movb 0xff,rl0
movbs r0,rl1
movbs r0,0x12
movbs 0x1234,rl0
movbs r0,rl1
movbs r0,0xff
movbs 0xffff,rl0
movbz r2,rl0
movbz r0,0x1234
movbz 0x1234,rl0
movbz r2,rl0
movbz r0,0xffff
movbz 0xffff,rl0

26
gas/testsuite/gas/xc16x/movb.s
View File

@ -1,26 +0,0 @@
.section .text
.global _fun
xc16x_movb:
movb rl0,r2
movb rl0,#0x12
movb r3,[r2]
movb rl0,[r2+]
movb [-r2],rl0
movb [r3],[r2+]
movb [r3],[r2]
movb [r2+],[r3]
movb [r2],[r3+]
movb rl0,[r3+#0x1234]
movb [r3+#0x1234],rl0
movb [r3],0x1234
movb [r3],0xeeff
movb 0x1234,[r3]
movb rl0,0x12
movb 0x12,rl0

8
gas/testsuite/gas/xc16x/movbs.s
View File

@ -1,8 +0,0 @@
.section .text
.global _fun
xc16x_movbs:
movbs r0,rl1
movbs r0,0xff
movbs 0xffcb,rl0

9
gas/testsuite/gas/xc16x/movbz.s
View File

@ -1,9 +0,0 @@
.section .text
.global _fun
xc16x_movbz:
movbz r2,rl0
movbz r0,0x23dd
movbz 0x23,rl0

6
gas/testsuite/gas/xc16x/mul.s
View File

@ -1,6 +0,0 @@
.section .text
.global _fun
xc16x_mul:
mul r0,r1
mulu r0,r1

6
gas/testsuite/gas/xc16x/neg.s
View File

@ -1,6 +0,0 @@
.section .text
.global _fun
xc16x_neg:
neg r0
negb rl0

6
gas/testsuite/gas/xc16x/nop.s
View File

@ -1,6 +0,0 @@
.section .text
.global _fun
xc16x_nop:
nop
nop

11
gas/testsuite/gas/xc16x/or.s
View File

@ -1,11 +0,0 @@
.section .text
.global _fun
xc16x_or:
or r0,r1
or r0,[r1]
or r0,[r1+]
or r0,#3
or r0,#0x0234
or r0,0x4536
or 0x4536,r0

10
gas/testsuite/gas/xc16x/orb.s
View File

@ -1,10 +0,0 @@
.section .text
.global _fun
xc16x_or:
orb rl0,rl1
orb rl0,[r1]
orb rl0,[r1+]
orb rl0,#3
orb rl0,#0x23
orb rl0,0x0234
orb 0x0234,rl0

5
gas/testsuite/gas/xc16x/prior.s
View File

@ -1,5 +0,0 @@
.section .text
.global _fun
xc16x_prior:
prior r0,r1

5
gas/testsuite/gas/xc16x/pushpop.s
View File

@ -1,5 +0,0 @@
.section .text
.global _fun
xc16x_pushpop:
pop r0
push r0

9
gas/testsuite/gas/xc16x/ret.s
View File

@ -1,9 +0,0 @@
.section .text
.global _fun
xc16x_ret:
ret
reti
rets
retp r5

6
gas/testsuite/gas/xc16x/scxt.s
View File

@ -1,6 +0,0 @@
.section .text
.global _fun
xc16x_scxt:
scxt r0,#0xffff
scxt r0,0xffff

14
gas/testsuite/gas/xc16x/shlrol.s
View File

@ -1,14 +0,0 @@
.section .text
.global _fun
xc16x_shlrol:
shl r0,r1
shl r0,#4
shr r0,r1
shr r0,#4
rol r0,r1
rol r0,#4
ror r0,r1
ror r0,#4
ashr r0,r1
ashr r0,#4

19
gas/testsuite/gas/xc16x/sub.s
View File

@ -1,19 +0,0 @@
.section .text
.global _fun
xc16x_sub:
sub r0,r1
sub r0,[r1]
sub r0,[r1+]
sub r0,#0x1
sub r0,#0x7643
sub r0,0x7643
sub 0x7643,r0

70
gas/testsuite/gas/xc16x/sub_test.s
View File

@ -1,70 +0,0 @@
.text
_start:
sub r0,r1
sub r0,[r1]
sub r0,[r1+]
sub r0,#0x1
sub r0,#0x7643
sub r0,0x7643
sub 0x7643,r0
sub r1,r0
sub r1,[r0]
sub r1,[r0+]
sub r1,#0x1
sub r1,#0xCDEF
sub r1,0xCDEF
sub 0xCDEF,r1
subb rl0,rl1
subb rl0,[r1]
subb rl0,[r1+]
subb rl0,#0x1
subb rl0,#0x43
subb rl0,0x7643
subb 0x7643,rl0
subb rl1,rl0
subb rl1,[r0]
subb rl1,[r0+]
subb rl1,#0x1
subb rl1,#0xCD
subb rl1,0xCDEF
subb 0xCDEF,rl1
subc r0,r1
subc r0,[r1]
subc r0,[r1+]
subc r0,#0x2
subc r0,#0x43
subc r0,0x7643
subc 0x7643,r0
subc r1,r0
subc r1,[r0]
subc r1,[r0+]
subc r1,#0xC
subc r1,#0xCD
subc r1,0xCDEF
subc 0xCDEF,r1
subcb rl0,rl1
subcb rl0,[r1]
subcb rl0,[r1+]
subcb rl0,#0x2
subcb rl0,#0x43
subcb rl0,0x7643
subcb 0x7643,rl0
subcb rl0,rl1
subcb rl0,[r1]
subcb rl0,[r1+]
subcb rl0,#0x2
subcb rl0,#0x43
subcb rl0,0x7643
subcb 0x7643,rl0

19
gas/testsuite/gas/xc16x/subb.s
View File

@ -1,19 +0,0 @@
.section .text
.global _fun
xc16x_subb:
subb rl0,rl1
subb rl0,[r1]
subb rl0,[r1+]
subb rl0,#0x1
subb rl0,#0x43
subb rl0,0x7643
subb 0x7643,rl0

19
gas/testsuite/gas/xc16x/subc.s
View File

@ -1,19 +0,0 @@
.section .text
.global _fun
xc16x_subc:
subc r0,r1
subc r0,[r1]
subc r0,[r1+]
subc r0,#0x2
subc r0,#0x43
subc r0,0x7643
subc 0x7643,r0

20
gas/testsuite/gas/xc16x/subcb.s
View File

@ -1,20 +0,0 @@
.section .text
.global _fun
xc16x_subcb:
subcb rl0,rl1
subcb rl0,[r1]
subcb rl0,[r1+]
subcb rl0,#0x2
subcb rl0,#0x43
subcb rl0,0x7643
subcb 0x7643,rl0

12
gas/testsuite/gas/xc16x/syscontrol1.s
View File

@ -1,12 +0,0 @@
.section .text
.global _fun
xc16x_syscontrol:
srst
sbrk
idle
pwrdn
srvwdt
diswdt
enwdt
einit

26
gas/testsuite/gas/xc16x/syscontrol2.s
View File

@ -1,26 +0,0 @@
.text
xc16x_syscontrol2:
extr #0x4
extr #0x3
extr #0x2
extr #0x1
atomic #0x4
atomic #0x3
atomic #0x2
atomic #0x1
extp r5,#0x4
extp #0x3ff,#0x4
extpr r5,#0x4
extpr #0x3ff,#0x4
exts r5,#0x4
exts #0x1,#0x4
extsr r5,#0x4
extsr #0x1,#0x4

6
gas/testsuite/gas/xc16x/trap.s
View File

@ -1,6 +0,0 @@
.section .text
.global _fun
xc16x_trap:
trap #0x02

1333
gas/testsuite/gas/xc16x/xc16x.exp
View File

File diff suppressed because it is too large Load Diff

10
gas/testsuite/gas/xc16x/xor.s
View File

@ -1,10 +0,0 @@
.section .text
.global _fun
xc16x_or:
xor r0,r1
xor r0,[r1]
xor r0,[r1+]
xor r0,#3
xor r0,#0x0234
xor r0,0x0234
xor 0x0234,r0

10
gas/testsuite/gas/xc16x/xorb.s
View File

@ -1,10 +0,0 @@
.section .text
.global _fun
xc16x_xorb:
xorb rl0,rl1
xorb rl0,[r1]
xorb rl0,[r1+]
xorb rl0,#3
xorb rl0,#0x34
xorb rl0,0x2403
xorb 0x2403,rl0

40
include/elf/xc16x.h
View File

@ -1,40 +0,0 @@
/* Infineon XC16X ELF support for BFD.
Copyright (C) 2006-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _ELF_XC16X_H
#define _ELF_XC16X_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_xc16x_reloc_type)
RELOC_NUMBER (R_XC16X_NONE, 0)
RELOC_NUMBER (R_XC16X_ABS_8, 1)
RELOC_NUMBER (R_XC16X_ABS_16, 2)
RELOC_NUMBER (R_XC16X_ABS_32, 3)
RELOC_NUMBER (R_XC16X_8_PCREL, 4)
RELOC_NUMBER (R_XC16X_PAG, 5)
RELOC_NUMBER (R_XC16X_POF, 6)
RELOC_NUMBER (R_XC16X_SEG, 7)
RELOC_NUMBER (R_XC16X_SOF, 8)
END_RELOC_NUMBERS (R_XC16X_max)
#endif /* _ELF_XC16X_H */

6
ld/Makefile.am
View File

@ -271,9 +271,6 @@ ALL_EMULATION_SOURCES = \
eelf32tilepro.c \
eelf32vax.c \
eelf32visium.c \
eelf32xc16x.c \
eelf32xc16xl.c \
eelf32xc16xs.c \
eelf32xstormy16.c \
eelf32xtensa.c \
eelf32z80.c \
@ -765,9 +762,6 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Pc@am__quote@

9
ld/Makefile.in
View File

@ -768,9 +768,6 @@ ALL_EMULATION_SOURCES = \
eelf32tilepro.c \
eelf32vax.c \
eelf32visium.c \
eelf32xc16x.c \
eelf32xc16xl.c \
eelf32xc16xs.c \
eelf32xstormy16.c \
eelf32xtensa.c \
eelf32z80.c \
@ -1407,9 +1404,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Po@am__quote@
@ -2434,9 +2428,6 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32visium.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xl.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Pc@am__quote@

3
ld/configure.tgt
View File

@ -1021,9 +1021,6 @@ x86_64-*-mingw*) targ_emul=i386pep ;
targ_extra_emuls=i386pe
targ_extra_ofiles="deffilep.o pep-dll.o pe-dll.o"
;;
xc16x-*-elf) targ_emul=elf32xc16x
targ_extra_emuls="elf32xc16xl elf32xc16xs"
;;
xgate-*-*) targ_emul=xgateelf
targ_extra_ofiles=ldelfgen.o
;;

8
ld/emulparams/elf32xc16x.sh
View File

@ -1,8 +0,0 @@
SCRIPT_NAME=elf32xc16x
TEMPLATE_NAME=elf
OUTPUT_FORMAT="elf32-xc16x"
TEXT_START_ADDR=0x00400
ARCH=xc16x
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ENTRY=_start
EMBEDDED=yes

8
ld/emulparams/elf32xc16xl.sh
View File

@ -1,8 +0,0 @@
SCRIPT_NAME=elf32xc16xl
TEMPLATE_NAME=elf
OUTPUT_FORMAT="elf32-xc16x"
TEXT_START_ADDR=0xc00300
ARCH=xc16x:xc16xl
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ENTRY=_start
EMBEDDED=yes

8
ld/emulparams/elf32xc16xs.sh
View File

@ -1,8 +0,0 @@
SCRIPT_NAME=elf32xc16xs
TEMPLATE_NAME=elf
OUTPUT_FORMAT="elf32-xc16x"
TEXT_START_ADDR=0xc00300
ARCH=xc16x:xc16xs
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ENTRY=_start
EMBEDDED=yes

3
ld/po/BLD-POTFILES.in
View File

@ -160,9 +160,6 @@ eelf32tilegx_be.c
eelf32tilepro.c
eelf32vax.c
eelf32visium.c
eelf32xc16x.c
eelf32xc16xl.c
eelf32xc16xs.c
eelf32xstormy16.c
eelf32xtensa.c
eelf32z80.c

80
ld/scripttempl/elf32xc16x.sc
View File

@ -1,80 +0,0 @@
# Copyright (C) 2014-2022 Free Software Foundation, Inc.
#
# Copying and distribution of this file, with or without modification,
# are permitted in any medium without royalty provided the copyright
# notice and this notice are preserved.
cat <<EOF
/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
EOF
test -n "${RELOCATING}" && cat <<EOF
ENTRY ("_start")
MEMORY
{
vectarea : o =0x00000, l = 0x0300
introm : o = 0x00400, l = 0x16000
/* The stack starts at the top of main ram. */
dram : o = 0x8000 , l = 0xffff
/* At the very top of the address space is the 8-bit area. */
ldata : o =0x4000 ,l = 0x0200
}
EOF
cat <<EOF
SECTIONS
{
.init :
{
KEEP (*(SORT_NONE(.init)))
${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
} ${RELOCATING+ >introm}
.text :
{
${RELOCATING+*(.rodata)}
${RELOCATING+*(.text.*)}
*(.text)
${RELOCATING+ _etext = . ; }
} ${RELOCATING+ > introm}
.data :
{
*(.data)
${RELOCATING+*(.data.*)}
${RELOCATING+ _edata = . ; }
} ${RELOCATING+ > dram}
.bss :
{
${RELOCATING+ _bss_start = . ;}
*(.bss)
${RELOCATING+*(COMMON)}
${RELOCATING+ _end = . ; }
} ${RELOCATING+ > dram}
.ldata :
{
*(.ldata)
} ${RELOCATING+ > ldata}
.vects :
{
*(.vects)
} ${RELOCATING+ > vectarea}
}
EOF

80
ld/scripttempl/elf32xc16xl.sc
View File

@ -1,80 +0,0 @@
# Copyright (C) 2014-2022 Free Software Foundation, Inc.
#
# Copying and distribution of this file, with or without modification,
# are permitted in any medium without royalty provided the copyright
# notice and this notice are preserved.
cat <<EOF
/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
EOF
test -n "${RELOCATING}" && cat <<EOF
ENTRY ("_start")
MEMORY
{
vectarea : o =0xc00000, l = 0x0300
introm : o = 0xc00300, l = 0x16000
/* The stack starts at the top of main ram. */
dram : o = 0x8000 , l = 0xffff
/* At the very top of the address space is the 8-bit area. */
ldata : o =0x4000 ,l = 0x0200
}
EOF
cat <<EOF
SECTIONS
{
/*.vects :
{
*(.vects)
} ${RELOCATING+ > vectarea} */
.init :
{
KEEP (*(SORT_NONE(.init)))
${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
} ${RELOCATING+ >introm}
.text :
{
${RELOCATING+*(.rodata)}
${RELOCATING+*(.text.*)}
*(.text)
${RELOCATING+ _etext = . ; }
} ${RELOCATING+ > introm}
.data :
{
*(.data)
${RELOCATING+*(.data.*)}
${RELOCATING+ _edata = . ; }
} ${RELOCATING+ > dram}
.bss :
{
${RELOCATING+ _bss_start = . ;}
*(.bss)
${RELOCATING+*(COMMON)}
${RELOCATING+ _end = . ; }
} ${RELOCATING+ > dram}
.ldata :
{
*(.ldata)
} ${RELOCATING+ > ldata}
.vects :
{
*(.vects)
} ${RELOCATING+ > vectarea}
}
EOF

81
ld/scripttempl/elf32xc16xs.sc
View File

@ -1,81 +0,0 @@
# Copyright (C) 2014-2022 Free Software Foundation, Inc.
#
# Copying and distribution of this file, with or without modification,
# are permitted in any medium without royalty provided the copyright
# notice and this notice are preserved.
cat <<EOF
/* Copyright (C) 2014-2022 Free Software Foundation, Inc.
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
EOF
test -n "${RELOCATING}" && cat <<EOF
ENTRY ("_start")
MEMORY
{
vectarea : o =0xc00000, l = 0x0300
introm : o = 0xc00300, l = 0x16000
/* The stack starts at the top of main ram. */
dram : o = 0x8000 , l = 0xffff
/* At the very top of the address space is the 8-bit area. */
ldata : o =0x4000 ,l = 0x0200
}
EOF
cat <<EOF
SECTIONS
{
/*.vects :
{
*(.vects)
} ${RELOCATING+ > vectarea} */
.init :
{
KEEP (*(SORT_NONE(.init)))
${RELOCATING+KEEP (*(SORT_NONE(.fini)))}
} ${RELOCATING+ >introm}
.text :
{
${RELOCATING+*(.rodata)}
${RELOCATING+*(.text.*)}
*(.text)
${RELOCATING+ _etext = . ; }
} ${RELOCATING+ > introm}
.data :
{
*(.data)
${RELOCATING+*(.data.*)}
${RELOCATING+ _edata = . ; }
} ${RELOCATING+ > dram}
.bss :
{
${RELOCATING+ _bss_start = . ;}
*(.bss)
${RELOCATING+*(COMMON)}
${RELOCATING+ _end = . ; }
} ${RELOCATING+ > dram}
.ldata :
{
*(.ldata)
} ${RELOCATING+ > ldata}
.vects :
{
*(.vects)
} ${RELOCATING+ > vectarea}
}
EOF

1
ld/testsuite/ld-elf/elf.exp
View File

@ -99,7 +99,6 @@ if [is_elf64 tmpdir/symbol3w.a] {
|| [istarget h8300-*-*]
|| [istarget ip2k-*-*]
|| [istarget m68hc11-*]
|| [istarget "xc16x-*"]
|| [istarget "z80-*-*"] } {
set pr25490_2_exp "pr25490-2-16.rd"
set pr25490_3_exp "pr25490-3-16.rd"

4
ld/testsuite/ld-elf/pr22450.d
View File

@ -1,9 +1,9 @@
#source: pr22450.s
#readelf: --notes --wide
#ld: -r
#xfail: avr-*-* crx-*-* h8300-*-* ip2k-*-* m68hc11-*-* xc16x-*-* z80-*-*
#xfail: avr-*-* crx-*-* h8300-*-* ip2k-*-* m68hc11-*-* z80-*-*
# Fails on H8300 because it does not generate the correct relocs for the size fields.
# Fails on AVR, IP2K, M68HC11, XC16C because the assembler does not calculate the correct values for the differences of local symbols.
# Fails on AVR, IP2K, and M68HC11 because the assembler does not calculate the correct values for the differences of local symbols.
# Fails on CRX because readelf does not know how to apply CRX reloc number 20 (R_CRX_SWITCH32).
#...

2
ld/testsuite/ld-elf/pr23658-1a.d
View File

@ -10,7 +10,7 @@
#xfail: [uses_genelf]
#xfail: m68hc12-*
# The following targets don't support --build-id.
#xfail: cr16-* crx-* visium-* xc16x-*
#xfail: cr16-* crx-* visium-*
# The following targets place .note.gnu.build-id in unusual places.
#xfail: pru-*

28
ld/testsuite/ld-xc16x/absrel.d
View File

@ -1,28 +0,0 @@
.*: file format elf32-xc16x
Disassembly of section .text:
00000400 <_start>:
400: e0 f5 mov r5,#0xf
402: e0 f6 mov r6,#0xf
00000404 <.12>:
404: f2 f5 1c 04 mov r5,0x41c
408: e0 d6 mov r6,#0xd
40a: f2 f7 1c 04 mov r7,0x41c
40e: e0 d8 mov r8,#0xd
00000410 <.13>:
410: f2 f5 1c 04 mov r5,0x41c
414: e0 f6 mov r6,#0xf
416: f2 f7 1c 04 mov r7,0x41c
41a: e0 f8 mov r8,#0xf
0000041c <.end>:
.*: ca 09 04 04 calla- cc_nusr0,404 <.12>
.*: ca 19 04 04 calla- cc_nusr1,404 <.12>
.*: ca 29 04 04 calla- cc_usr0,404 <.12>
.*: ea 09 04 04 jmpa- cc_nusr0,404 <.12>
.*: ea 19 04 04 jmpa- cc_nusr1,404 <.12>
.*: ea 29 04 04 jmpa- cc_usr0,404 <.12>

31
ld/testsuite/ld-xc16x/absrel.s
View File

@ -1,31 +0,0 @@
.global _start
_start:
mov r5,#0xf
mov r6,#0xf
.12:
mov r5,.end
mov r6,#0xd
mov r7,.end
mov r8,#0xd
.13:
mov r5,.end
mov r6,#0xf
mov r7,.end
mov r8,#0xf
.end:
;calla cc_UC,.13
;calla cc_usr1,.12
;calla+ cc_UGT,.12
calla- cc_nusr0,.12
calla- cc_nusr1,.12
calla- cc_usr0,.12
;jmpa cc_UGT,.end
;jmpa cc_nusr0,.end
;jmpa+ cc_UGT,.12
jmpa- cc_nusr0,.12
jmpa- cc_nusr1,.12
jmpa- cc_usr0,.12

18
ld/testsuite/ld-xc16x/offset.d
View File

@ -1,18 +0,0 @@
.*: file format elf32-xc16x
Disassembly of section .text:
00000400 <_start>:
400: e0 f8 mov r8,#0xf
402: fa 00 08 04 jmps #seg:0x0,#sof:0x408
406: e0 f9 mov r9,#0xf
00000408 <.12>:
408: e0 f5 mov r5,#0xf
40a: e0 f7 mov r7,#0xf
40c: da 00 10 04 calls #seg:0x0,#sof:0x410
00000410 <.13>:
410: e0 f6 mov r6,#0xf
412: e0 f8 mov r8,#0xf

13
ld/testsuite/ld-xc16x/offset.s
View File

@ -1,13 +0,0 @@
.global _start
_start:
mov r8,#0xf
jmps #seg:.12,#sof:.12
mov r9,#0xf
.12:
mov r5,#0xf
mov r7,#0xf
calls #seg:.13,#sof:.13
.13:
mov r6,#0xf
mov r8,#0xf

34
ld/testsuite/ld-xc16x/pcreloc.d
View File

@ -1,34 +0,0 @@
.*: file format elf32-xc16x
Disassembly of section .text:
00000400 <_start>:
400: e0 f5 mov r5,#0xf
402: e0 f6 mov r6,#0xf
404: e0 f7 mov r7,#0xf
406: e0 f8 mov r8,#0xf
408: e0 f9 mov r9,#0xf
40a: e0 fa mov r10,#0xf
40c: e0 fb mov r11,#0xf
40e: e0 fc mov r12,#0xf
00000410 <.12>:
410: 2d 07 jmpr cc_Z,7
412: 3d fe jmpr cc_NZ,254
414: 8d fd jmpr cc_ULT,253
416: 8d 45 jmpr cc_ULT,69
418: 9d 06 jmpr cc_UGE,6
41a: 0d 05 jmpr cc_UC,5
41c: 2d 04 jmpr cc_Z,4
41e: 3d 03 jmpr cc_NZ,3
00000420 <.13>:
420: fd 02 jmpr cc_ULE,2
422: dd 01 jmpr cc_SGE,1
424: bd 00 jmpr cc_SLE,0
00000426 <.end>:
426: 1d f4 jmpr cc_NET,244
428: bb fe callr 254
42a: bb fd callr 253

27
ld/testsuite/ld-xc16x/pcreloc.s
View File

@ -1,27 +0,0 @@
.global _start
_start:
mov r5,#0xf
mov r6,#0xf
mov r7,#0xf
mov r8,#0xf
mov r9,#0xf
mov r10,#0xf
mov r11,#0xf
mov r12,#0xf
.12:
jmpr cc_Z,.13
jmpr cc_NZ,.12
jmpr cc_C,.12
jmpr cc_C,0x45
jmpr cc_NC,.end
jmpr cc_UC,.end
jmpr cc_EQ,.end
jmpr cc_NE,.end
.13:
jmpr cc_ULE,.end
jmpr cc_SGE,.end
jmpr cc_SLE,.end
.end:
jmpr cc_NET,.12
callr .end
callr .end

34
ld/testsuite/ld-xc16x/pcrelocl.d
View File

@ -1,34 +0,0 @@
.*: file format elf32-xc16x
Disassembly of section .text:
00c00300 <_start>:
c00300: e0 f5 mov r5,#0xf
c00302: e0 f6 mov r6,#0xf
c00304: e0 f7 mov r7,#0xf
c00306: e0 f8 mov r8,#0xf
c00308: e0 f9 mov r9,#0xf
c0030a: e0 fa mov r10,#0xf
c0030c: e0 fb mov r11,#0xf
c0030e: e0 fc mov r12,#0xf
00c00310 <.12>:
c00310: 2d 07 jmpr cc_Z,7
c00312: 3d fe jmpr cc_NZ,254
c00314: 8d fd jmpr cc_ULT,253
c00316: 8d 45 jmpr cc_ULT,69
c00318: 9d 06 jmpr cc_UGE,6
c0031a: 0d 05 jmpr cc_UC,5
c0031c: 2d 04 jmpr cc_Z,4
c0031e: 3d 03 jmpr cc_NZ,3
00c00320 <.13>:
c00320: fd 02 jmpr cc_ULE,2
c00322: dd 01 jmpr cc_SGE,1
c00324: bd 00 jmpr cc_SLE,0
00c00326 <.end>:
c00326: 1d f4 jmpr cc_NET,244
c00328: bb fe callr 254
c0032a: bb fd callr 253

68
ld/testsuite/ld-xc16x/xc16x.exp
View File

@ -1,68 +0,0 @@
# Expect script for ld-xstormy16 tests
# Copyright (C) 2003-2022 Free Software Foundation, Inc.
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
# Test xc16x linking of pc-relative relocs. This tests the assembler and
# tools like objdump as well as the linker.
if {!([istarget "xc16x*-*-*"]) } {
return
}
# Set up a list as described in ld-lib.exp
set xc16x_tests {
{
"xc16x pc-relative relocs linker test"
"" ""
""
{ "pcreloc.s" }
{ {objdump -Dz pcreloc.d} }
"pcreloc"
}
}
set xc16xabs_tests {
{
"xc16x absolute relative address linker test"
"" ""
""
{ "absrel.s" }
{ {objdump -Dz absrel.d} }
"absrel"
}
}
set xc16xoffset_tests {
{
"xc16x offset linker test"
"" ""
""
{ "offset.s" }
{ {objdump -Dz offset.d} }
"offset"
}
}
run_ld_link_tests $xc16x_tests
run_ld_link_tests $xc16xabs_tests
run_ld_link_tests $xc16xoffset_tests

21
opcodes/Makefile.am
View File

@ -82,7 +82,6 @@ HFILES = \
score-opc.h \
sh-opc.h \
sysdep.h \
xc16x-desc.h xc16x-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
@ -262,11 +261,6 @@ TARGET32_LIBOPCODES_CFILES = \
visium-dis.c \
visium-opc.c \
wasm32-dis.c \
xc16x-asm.c \
xc16x-desc.c \
xc16x-dis.c \
xc16x-ibld.c \
xc16x-opc.c \
xstormy16-asm.c \
xstormy16-desc.c \
xstormy16-dis.c \
@ -357,8 +351,7 @@ po/POTFILES.in: @MAINT@ Makefile
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
stamp-or1k stamp-xc16x stamp-xstormy16 \
stamp-m32c stamp-m32r stamp-mep stamp-mt stamp-or1k stamp-xstormy16 \
libopcodes.a stamp-lib
@ -375,7 +368,7 @@ CGENDEPS = \
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
if CGEN_MAINT
BPF_DEPS = stamp-bpf
@ -391,7 +384,6 @@ M32R_DEPS = stamp-m32r
MEP_DEPS = stamp-mep
MT_DEPS = stamp-mt
OR1K_DEPS = stamp-or1k
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
BPF_DEPS =
@ -407,7 +399,6 @@ M32R_DEPS =
MEP_DEPS =
MT_DEPS =
OR1K_DEPS =
XC16X_DEPS =
XSTORMY16_DEPS =
endif
@ -524,14 +515,6 @@ stamp-or1k: $(CGENDEPS) $(CPUDIR)/or1k.cpu $(CPUDIR)/or1k.opc $(CPUDIR)/or1kcomm
$(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \
archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst
$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
@true
stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
$(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
archfile=$(CPUDIR)/xc16x.cpu \
opcfile=$(CPUDIR)/xc16x.opc \
extrafiles=
$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
@true
stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc

26
opcodes/Makefile.in
View File

@ -473,7 +473,6 @@ HFILES = \
score-opc.h \
sh-opc.h \
sysdep.h \
xc16x-desc.h xc16x-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
@ -654,11 +653,6 @@ TARGET32_LIBOPCODES_CFILES = \
visium-dis.c \
visium-opc.c \
wasm32-dis.c \
xc16x-asm.c \
xc16x-desc.c \
xc16x-dis.c \
xc16x-ibld.c \
xc16x-opc.c \
xstormy16-asm.c \
xstormy16-desc.c \
xstormy16-dis.c \
@ -718,8 +712,7 @@ libopcodes_a_SOURCES =
POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
stamp-or1k stamp-xc16x stamp-xstormy16 \
stamp-m32c stamp-m32r stamp-mep stamp-mt stamp-or1k stamp-xstormy16 \
libopcodes.a stamp-lib
CGENDIR = @cgendir@
@ -734,7 +727,7 @@ CGENDEPS = \
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
@CGEN_MAINT_FALSE@BPF_DEPS =
@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@CRIS_DEPS =
@ -761,8 +754,6 @@ CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x
@CGEN_MAINT_TRUE@MT_DEPS = stamp-mt
@CGEN_MAINT_FALSE@OR1K_DEPS =
@CGEN_MAINT_TRUE@OR1K_DEPS = stamp-or1k
@CGEN_MAINT_FALSE@XC16X_DEPS =
@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
@CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
MOSTLYCLEANFILES = aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_BUILD) \
@ -1071,11 +1062,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/visium-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/visium-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/wasm32-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-desc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-ibld.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xc16x-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xgate-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xgate-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xstormy16-asm.Plo@am__quote@
@ -1515,14 +1501,6 @@ stamp-or1k: $(CGENDEPS) $(CPUDIR)/or1k.cpu $(CPUDIR)/or1k.opc $(CPUDIR)/or1kcomm
$(MAKE) run-cgen arch=or1k prefix=or1k options=opinst \
archfile=$(CPUDIR)/or1k.cpu opcfile=$(CPUDIR)/or1k.opc extrafiles=opinst
$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
@true
stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
$(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
archfile=$(CPUDIR)/xc16x.cpu \
opcfile=$(CPUDIR)/xc16x.opc \
extrafiles=
$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS)
@true
stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc

1
opcodes/configure vendored
View File

@ -12574,7 +12574,6 @@ if test x${all_targets} = xfalse ; then
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_visium_arch) ta="$ta visium-dis.lo visium-opc.lo" ;;
bfd_wasm32_arch) ta="$ta wasm32-dis.lo" ;;
bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
bfd_xgate_arch) ta="$ta xgate-dis.lo xgate-opc.lo" ;;
bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;

1
opcodes/configure.ac
View File

@ -340,7 +340,6 @@ if test x${all_targets} = xfalse ; then
bfd_vax_arch) ta="$ta vax-dis.lo" ;;
bfd_visium_arch) ta="$ta visium-dis.lo visium-opc.lo" ;;
bfd_wasm32_arch) ta="$ta wasm32-dis.lo" ;;
bfd_xc16x_arch) ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
bfd_xgate_arch) ta="$ta xgate-dis.lo xgate-opc.lo" ;;
bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;

6
opcodes/disassemble.c
View File

@ -98,7 +98,6 @@
#define ARCH_visium
#define ARCH_wasm32
#define ARCH_xstormy16
#define ARCH_xc16x
#define ARCH_xgate
#define ARCH_xtensa
#define ARCH_z80
@ -490,11 +489,6 @@ disassembler (enum bfd_architecture a,
disassemble = print_insn_xstormy16;
break;
#endif
#ifdef ARCH_xc16x
case bfd_arch_xc16x:
disassemble = print_insn_xc16x;
break;
#endif
#ifdef ARCH_xtensa
case bfd_arch_xtensa:
disassemble = print_insn_xtensa;

1
opcodes/disassemble.h
View File

@ -93,7 +93,6 @@ extern int print_insn_v850 (bfd_vma, disassemble_info *);
extern int print_insn_vax (bfd_vma, disassemble_info *);
extern int print_insn_visium (bfd_vma, disassemble_info *);
extern int print_insn_wasm32 (bfd_vma, disassemble_info *);
extern int print_insn_xc16x (bfd_vma, disassemble_info *);
extern int print_insn_xgate (bfd_vma, disassemble_info *);
extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
extern int print_insn_xtensa (bfd_vma, disassemble_info *);

7
opcodes/po/POTFILES.in
View File

@ -221,13 +221,6 @@ vax-dis.c
visium-dis.c
visium-opc.c
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c

Some files were not shown because too many files have changed in this diff Show More