mirrors/binutils-gdb
0
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-28 20:43:45 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

POWER9 add scv/rfscv instruction support

Browse Source 
opcodes/
	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.

gas/
	* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
This commit is contained in:
Nicholas Piggin 2017-02-10 14:18:23 +10:00 committed by Alan Modra
parent 53f7e8ea7f
commit dce75bf984
5 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
* testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-02 Maciej W. Rozycki <macro@imgtec.com>
* doc/as.texinfo (Overview): Select MIPS options for man page

3
gas/testsuite/gas/ppc/power9.d
View File

@ -391,4 +391,7 @@ Disassembly of section \.text:
.*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0
.*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3
.*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31
.*: (01 00 00 44|44 00 00 01) scv 0
.*: (e1 0f 00 44|44 00 0f e1) scv 127
.*: (a4 00 00 4c|4c 00 00 a4) rfscv
#pass

3
gas/testsuite/gas/ppc/power9.s
View File

@ -382,3 +382,6 @@ power9:
mffscrni 30,0
mffscrni 30,3
mffsl 31
scv 0
scv 127
rfscv

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2017-02-10 Nicholas Piggin <npiggin@gmail.com>
* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
2017-02-03 Nick Clifton <nickc@redhat.com>
PR 21096

4
opcodes/ppc-opc.c
View File

@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] =
#define L2OPT L32OPT + 1
{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SVC form instruction. */
/* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
#define SVC_LEV L2OPT + 1
{ 0x7f, 5, NULL, NULL, 0 },
@ -4142,6 +4142,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
@ -4391,6 +4392,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},