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aarch64: Treat operand ADDR_SIMPLE as address with base register

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The AArch64 instruction table (aarch64-tbl.h) defines the operand
ADDR_SIMPLE as "address with base register (no offset)". During assembly
it is correctly encoded as address with base register (addr.base_regno)
in parse_operands. In warn_unpredictable_ldst it is erroneously treated
as register number (reg.regno).

This resolves the assembler test case "Diagnostics Quality" to
erroneously fail when changing the union in struct aarch64_opnd_info
from union to struct for debugging purposes.

gas/
	* config/tc-aarch64.c: Treat operand ADDR_SIMPLE as address with
	base register.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
This commit is contained in:
Jens Remus 2024-06-25 17:25:55 +02:00
parent 64daf9abd9
commit da47588db1
1 changed files with 3 additions and 3 deletions
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6
gas/config/tc-aarch64.c
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@ -8509,7 +8509,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
(_("unpredictable: identical transfer and status registers"
" --`%s'"),str);
if (opnds[0].reg.regno == opnds[2].reg.regno)
if (opnds[0].reg.regno == opnds[2].addr.base_regno)
{
if (!(opcode->opcode & (1 << 21)))
/* Store-Exclusive is unpredictable if Rn == Rs. */
@ -8526,8 +8526,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
/* Store-Exclusive pair is unpredictable if Rn == Rs. */
if ((opcode->opcode & (1 << 21))
&& opnds[0].reg.regno == opnds[3].reg.regno
&& opnds[3].reg.regno != REG_SP)
&& opnds[0].reg.regno == opnds[3].addr.base_regno
&& opnds[3].addr.base_regno != REG_SP)
as_warn (_("unpredictable: identical base and status registers"
" --`%s'"),str);
}