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Replace rdrnd with rdrand.
gas/testsuite/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/rdrnd.s: Replace rdrnd with rdrand. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. opcodes/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (mod_table): Replace rdrnd with rdrand. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
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@ -1,3 +1,13 @@
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2010)
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* gas/i386/rdrnd.s: Replace rdrnd with rdrand.
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* gas/i386/rdrnd-intel.d: Likewise.
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* gas/i386/rdrnd.d: Likewise.
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* gas/i386/x86-64-rdrnd-intel.d: Likewise.
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* gas/i386/x86-64-rdrnd.d: Likewise.
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* gas/i386/x86-64-rdrnd.s: Likewise.
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/10531
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@ -8,8 +8,8 @@
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
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#pass
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@ -7,8 +7,8 @@
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
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#pass
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@ -2,9 +2,9 @@
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.text
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foo:
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rdrnd %bx
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rdrnd %ebx
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rdrand %bx
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rdrand %ebx
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.intel_syntax noprefix
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rdrnd bx
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rdrnd ebx
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rdrand bx
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rdrand ebx
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@ -8,16 +8,16 @@
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand r8
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#pass
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@ -7,16 +7,16 @@
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrnd %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrnd %ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrnd %rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrnd %r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrnd %r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrnd %r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand %rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand %r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand %r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand %r8
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[ ]*[a-f0-9]+: 66 0f c7 f3 rdrand %bx
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[ ]*[a-f0-9]+: 0f c7 f3 rdrand %ebx
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[ ]*[a-f0-9]+: 48 0f c7 f3 rdrand %rbx
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[ ]*[a-f0-9]+: 66 41 0f c7 f0 rdrand %r8w
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[ ]*[a-f0-9]+: 41 0f c7 f0 rdrand %r8d
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[ ]*[a-f0-9]+: 49 0f c7 f0 rdrand %r8
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#pass
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@ -2,17 +2,17 @@
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.text
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foo:
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rdrnd %bx
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rdrnd %ebx
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rdrnd %rbx
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rdrnd %r8w
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rdrnd %r8d
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rdrnd %r8
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rdrand %bx
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rdrand %ebx
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rdrand %rbx
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rdrand %r8w
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rdrand %r8d
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rdrand %r8
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.intel_syntax noprefix
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rdrnd bx
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rdrnd ebx
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rdrnd rbx
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rdrnd r8w
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rdrnd r8d
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rdrnd r8
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rdrand bx
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rdrand ebx
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rdrand rbx
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rdrand r8w
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rdrand r8d
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rdrand r8
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@ -1,3 +1,10 @@
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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AVX Programming Reference (June, 2010)
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* i386-dis.c (mod_table): Replace rdrnd with rdrand.
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* i386-opc.tbl: Likewise.
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* i386-tbl.h: Regenerated.
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2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
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@ -10450,7 +10450,7 @@ static const struct dis386 mod_table[][2] = {
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{
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/* MOD_0FC7_REG_6 */
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{ PREFIX_TABLE (PREFIX_0FC7_REG_6) },
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{ "rdrnd", { Ev } },
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{ "rdrand", { Ev } },
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},
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{
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/* MOD_0FC7_REG_7 */
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@ -2394,7 +2394,7 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVV
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rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
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rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
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rdrnd, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
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rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
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wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
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wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
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vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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@ -27311,7 +27311,7 @@ const insn_template i386_optab[] =
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{ { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "rdrnd", 1, 0xfc7, 0x6, 2,
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{ "rdrand", 1, 0xfc7, 0x6, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 0, 0, 0, 0 } },
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