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Support x86 Intel MSR_IMM
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
This commit is contained in:
Hu, Lin1
Haochen Jiang
parent
77bcfb741c
commit
d7d71afa6a
2
gas/NEWS
2
gas/NEWS
@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for the x86 Intel MSR_IMM instructions.
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* Add support for the x86 Zhaoxin GMI instructions.
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* On x86 emulation support (for secondary targets) was dropped.
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@ -1221,6 +1221,7 @@ static const arch_entry cpu_arch[] =
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SUBARCH (apx_f, APX_F, APX_F, false),
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VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
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SUBARCH (gmi, GMI, GMI, false),
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SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
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};
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#undef SUBARCH
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@ -2233,7 +2234,8 @@ cpu_flags_match (const insn_template *t)
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&& (any.bitfield.cpubmi || any.bitfield.cpubmi2
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|| any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw
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|| any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
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|| any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr))
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|| any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr
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|| any.bitfield.cpumsr_imm))
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{
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/* These checks (verifying that APX_F() was properly used in the
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opcode table entry) make sure there's no need for an "else" to
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@ -4037,7 +4039,8 @@ install_template (const insn_template *t)
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if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
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|| maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
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|| maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
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|| maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR))
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|| maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
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|| maybe_cpu (t, CpuMSR_IMM))
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&& maybe_cpu (t, CpuAPX_F))
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{
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if (need_evex_encoding (t))
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@ -6990,18 +6993,20 @@ i386_assemble (char *line)
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because of the swapping above) in the incoming set of operands. */
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if ((i.imm_operands == 2
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&& (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq))
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|| (t->mnem_off == MN_uwrmsr && i.imm_operands
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&& i.operands > i.imm_operands))
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|| ((t->mnem_off == MN_uwrmsr || t->mnem_off == MN_wrmsrns)
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&& i.imm_operands && i.operands > i.imm_operands))
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swap_2_operands (0, 1);
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if (i.imm_operands)
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{
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/* For USER_MSR instructions, imm32 stands for the name of an model specific
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register (MSR). That's an unsigned quantity, whereas all other insns with
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32-bit immediate and 64-bit operand size use sign-extended
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immediates (imm32s). Therefore these insns are special-cased, bypassing
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the normal handling of immediates here. */
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if (is_cpu(current_templates.start, CpuUSER_MSR))
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/* For USER_MSR and MSR_IMM instructions, imm32 stands for the name of a
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model specific register (MSR). That's an unsigned quantity, whereas all
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other insns with 32-bit immediate and 64-bit operand size use
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sign-extended immediates (imm32s). Therefore these insns are
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special-cased, bypassing the normal handling of immediates here. */
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if (is_cpu(current_templates.start, CpuUSER_MSR)
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|| t->mnem_off == MN_rdmsr
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|| t->mnem_off == MN_wrmsrns)
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{
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for (j = 0; j < i.operands; j++)
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{
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@ -218,6 +218,7 @@ accept various extension mnemonics. For example,
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@code{avx10.1/256},
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@code{avx10.1/128},
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@code{user_msr},
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@code{msr_imm},
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@code{apx_f},
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@code{avx10.2},
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@code{avx10.2/512},
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@ -1694,7 +1695,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
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@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
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@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
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@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.avx10.2}
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@item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2}
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@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
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@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
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@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
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@ -520,6 +520,7 @@ if [gas_32_check] then {
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run_dump_test "sm4-intel"
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run_list_test "pbndkb-inval"
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run_list_test "user_msr-inval"
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run_list_test "msr_imm-inval"
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run_list_test "apx-push2pop2-inval"
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run_dump_test "avx10_2-rounding"
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run_dump_test "avx10_2-rounding-intel"
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3
gas/testsuite/gas/i386/msr_imm-inval.l
Normal file
3
gas/testsuite/gas/i386/msr_imm-inval.l
Normal file
@ -0,0 +1,3 @@
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.* Assembler messages:
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.*:5: Error: unsupported instruction `rdmsr'
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.*:6: Error: unsupported instruction `wrmsrns'
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6
gas/testsuite/gas/i386/msr_imm-inval.s
Normal file
6
gas/testsuite/gas/i386/msr_imm-inval.s
Normal file
@ -0,0 +1,6 @@
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# Check Illegal 32bit MSR_IMM instructions
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.text
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_start:
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rdmsr $51515151, %eax
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wrmsrns %eax, $51515151
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35
gas/testsuite/gas/i386/x86-64-msr_imm-intel.d
Normal file
35
gas/testsuite/gas/i386/x86-64-msr_imm-intel.d
Normal file
@ -0,0 +1,35 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 MSR_IMM insns (Intel disassembly)
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#source: x86-64-msr_imm.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 0f 0f 12 03\s+rdmsr r12,0x3120f0f
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\s*[a-f0-9]+:\s*c4 e7 7b f6 c0 0f 0f 12 03\s+rdmsr rax,0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 7f 00 00 00\s+rdmsr r12,0x7f
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 ff 7f 00 00\s+rdmsr r12,0x7fff
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 00 00 00 80\s+rdmsr r12,0x80000000
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\s*[a-f0-9]+:\s*62 df 7f 08 f6 c0 0f 0f 12 03\s+rdmsr r24,0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 0f 0f 12 03\s+wrmsrns 0x3120f0f,r12
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\s*[a-f0-9]+:\s*c4 e7 7a f6 c0 0f 0f 12 03\s+wrmsrns 0x3120f0f,rax
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 7f 00 00 00\s+wrmsrns 0x7f,r12
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 ff 7f 00 00\s+wrmsrns 0x7fff,r12
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 00 00 00 80\s+wrmsrns 0x80000000,r12
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\s*[a-f0-9]+:\s*62 df 7e 08 f6 c0 0f 0f 12 03\s+wrmsrns 0x3120f0f,r24
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 0f 0f 12 03\s+rdmsr r12,0x3120f0f
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\s*[a-f0-9]+:\s*c4 e7 7b f6 c0 0f 0f 12 03\s+rdmsr rax,0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 7f 00 00 00\s+rdmsr r12,0x7f
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 ff 7f 00 00\s+rdmsr r12,0x7fff
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 00 00 00 80\s+rdmsr r12,0x80000000
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\s*[a-f0-9]+:\s*62 df 7f 08 f6 c0 0f 0f 12 03\s+rdmsr r24,0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 0f 0f 12 03\s+wrmsrns 0x3120f0f,r12
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\s*[a-f0-9]+:\s*c4 e7 7a f6 c0 0f 0f 12 03\s+wrmsrns 0x3120f0f,rax
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 7f 00 00 00\s+wrmsrns 0x7f,r12
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 ff 7f 00 00\s+wrmsrns 0x7fff,r12
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 00 00 00 80\s+wrmsrns 0x80000000,r12
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\s*[a-f0-9]+:\s*62 df 7e 08 f6 c0 0f 0f 12 03\s+wrmsrns 0x3120f0f,r24
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#pass
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5
gas/testsuite/gas/i386/x86-64-msr_imm-inval.l
Normal file
5
gas/testsuite/gas/i386/x86-64-msr_imm-inval.l
Normal file
@ -0,0 +1,5 @@
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.* Assembler messages:
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.*:5: Error: operand type mismatch for `rdmsr'
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.*:6: Error: operand type mismatch for `rdmsr'
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.*:7: Error: operand type mismatch for `wrmsrns'
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.*:8: Error: operand type mismatch for `wrmsrns'
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8
gas/testsuite/gas/i386/x86-64-msr_imm-inval.s
Normal file
8
gas/testsuite/gas/i386/x86-64-msr_imm-inval.s
Normal file
@ -0,0 +1,8 @@
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# Check Illegal 64bit MSR_IMM instructions
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.text
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_start:
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rdmsr $5151515151515151, %r12
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rdmsr $-515151, %r12
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wrmsrns %r12, $5151515151515151
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wrmsrns %r12, $-515151
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35
gas/testsuite/gas/i386/x86-64-msr_imm.d
Normal file
35
gas/testsuite/gas/i386/x86-64-msr_imm.d
Normal file
@ -0,0 +1,35 @@
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#as:
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#objdump: -dw
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#name: x86_64 MSR_IMM insns
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#source: x86-64-msr_imm.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%r12
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\s*[a-f0-9]+:\s*c4 e7 7b f6 c0 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%rax
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 7f 00 00 00\s+rdmsr\s+\$0x7f,%r12
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 ff 7f 00 00\s+rdmsr\s+\$0x7fff,%r12
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 00 00 00 80\s+rdmsr\s+\$0x80000000,%r12
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\s*[a-f0-9]+:\s*62 df 7f 08 f6 c0 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%r24
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 0f 0f 12 03\s+wrmsrns\s+%r12,\$0x3120f0f
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\s*[a-f0-9]+:\s*c4 e7 7a f6 c0 0f 0f 12 03\s+wrmsrns\s+%rax,\$0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 7f 00 00 00\s+wrmsrns\s+%r12,\$0x7f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 ff 7f 00 00\s+wrmsrns\s+%r12,\$0x7fff
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 00 00 00 80\s+wrmsrns\s+%r12,\$0x80000000
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\s*[a-f0-9]+:\s*62 df 7e 08 f6 c0 0f 0f 12 03\s+wrmsrns\s+%r24,\$0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%r12
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\s*[a-f0-9]+:\s*c4 e7 7b f6 c0 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%rax
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 7f 00 00 00\s+rdmsr\s+\$0x7f,%r12
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 ff 7f 00 00\s+rdmsr\s+\$0x7fff,%r12
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\s*[a-f0-9]+:\s*c4 c7 7b f6 c4 00 00 00 80\s+rdmsr\s+\$0x80000000,%r12
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\s*[a-f0-9]+:\s*62 df 7f 08 f6 c0 0f 0f 12 03\s+rdmsr\s+\$0x3120f0f,%r24
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 0f 0f 12 03\s+wrmsrns\s+%r12,\$0x3120f0f
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\s*[a-f0-9]+:\s*c4 e7 7a f6 c0 0f 0f 12 03\s+wrmsrns\s+%rax,\$0x3120f0f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 7f 00 00 00\s+wrmsrns\s+%r12,\$0x7f
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 ff 7f 00 00\s+wrmsrns\s+%r12,\$0x7fff
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\s*[a-f0-9]+:\s*c4 c7 7a f6 c4 00 00 00 80\s+wrmsrns\s+%r12,\$0x80000000
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\s*[a-f0-9]+:\s*62 df 7e 08 f6 c0 0f 0f 12 03\s+wrmsrns\s+%r24,\$0x3120f0f
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#pass
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30
gas/testsuite/gas/i386/x86-64-msr_imm.s
Normal file
30
gas/testsuite/gas/i386/x86-64-msr_imm.s
Normal file
@ -0,0 +1,30 @@
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# Check 64bit MSR_IMM instructions
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.text
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_start:
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rdmsr $51515151, %r12
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rdmsr $51515151, %rax
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rdmsr $0x7f, %r12
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rdmsr $0x7fff, %r12
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rdmsr $0x80000000, %r12
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rdmsr $51515151, %r24
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wrmsrns %r12, $51515151
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wrmsrns %rax, $51515151
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wrmsrns %r12, $0x7f
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wrmsrns %r12, $0x7fff
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wrmsrns %r12, $0x80000000
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wrmsrns %r24, $51515151
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.intel_syntax noprefix
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rdmsr r12, 51515151
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rdmsr rax, 51515151
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rdmsr r12, 0x7f
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rdmsr r12, 0x7fff
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rdmsr r12, 0x80000000
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rdmsr r24, 51515151
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wrmsrns 51515151, r12
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wrmsrns 51515151, rax
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wrmsrns 0x7f, r12
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wrmsrns 0x7fff, r12
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wrmsrns 0x80000000, r12
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wrmsrns 51515151, r24
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@ -498,6 +498,9 @@ run_dump_test "x86-64-pbndkb-intel"
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run_dump_test "x86-64-user_msr"
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run_dump_test "x86-64-user_msr-intel"
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run_list_test "x86-64-user_msr-inval"
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run_dump_test "x86-64-msr_imm"
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run_dump_test "x86-64-msr_imm-intel"
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run_list_test "x86-64-msr_imm-inval"
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run_dump_test "x86-64-avx10_2-rounding"
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run_dump_test "x86-64-avx10_2-rounding-intel"
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run_dump_test "x86-64-avx10_2-evex-promote"
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@ -902,6 +902,7 @@ enum
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REG_VEX_0FAE,
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REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
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REG_VEX_0F38F3_L_0_P_0,
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REG_VEX_MAP7_F6_L_0_W_0,
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REG_VEX_MAP7_F8_L_0_W_0,
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REG_XOP_09_01_L_0,
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@ -1151,6 +1152,7 @@ enum
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PREFIX_VEX_0F38F6_L_0,
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PREFIX_VEX_0F38F7_L_0,
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PREFIX_VEX_0F3AF0_L_0,
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PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
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PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
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||||
PREFIX_EVEX_0F5B,
|
||||
@ -1318,6 +1320,7 @@ enum
|
||||
X86_64_VEX_0F386C,
|
||||
X86_64_VEX_0F38Ex,
|
||||
|
||||
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
|
||||
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
|
||||
};
|
||||
|
||||
@ -1432,6 +1435,7 @@ enum
|
||||
VEX_LEN_0F3ADE_W_0,
|
||||
VEX_LEN_0F3ADF,
|
||||
VEX_LEN_0F3AF0,
|
||||
VEX_LEN_MAP7_F6,
|
||||
VEX_LEN_MAP7_F8,
|
||||
VEX_LEN_XOP_08_85,
|
||||
VEX_LEN_XOP_08_86,
|
||||
@ -1593,6 +1597,7 @@ enum
|
||||
VEX_W_0F3ACE,
|
||||
VEX_W_0F3ACF,
|
||||
VEX_W_0F3ADE,
|
||||
VEX_W_MAP7_F6_L_0,
|
||||
VEX_W_MAP7_F8_L_0,
|
||||
|
||||
VEX_W_XOP_08_85_L_0,
|
||||
@ -2958,6 +2963,10 @@ static const struct dis386 reg_table[][8] = {
|
||||
{ "%NFblsmskS", { VexGdq, Edq }, 0 },
|
||||
{ "%NFblsiS", { VexGdq, Edq }, 0 },
|
||||
},
|
||||
/* REG_VEX_MAP7_F6_L_0_W_0 */
|
||||
{
|
||||
{ X86_64_TABLE (X86_64_VEX_MAP7_F6_L_0_W_0_R_0) },
|
||||
},
|
||||
/* REG_VEX_MAP7_F8_L_0_W_0 */
|
||||
{
|
||||
{ X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
|
||||
@ -4166,12 +4175,20 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ "%XErorxS", { Gdq, Edq, Ib }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "wrmsrns", { Skip_MODRM, Id, Rq }, 0 },
|
||||
{ Bad_Opcode },
|
||||
{ "rdmsr", { Rq, Id }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
|
||||
{ "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
|
||||
{ Bad_Opcode },
|
||||
{ "urdmsr", { Rq, Id }, 0 },
|
||||
{ "urdmsr", { Rq, Id }, 0 },
|
||||
},
|
||||
|
||||
#include "i386-dis-evex-prefix.h"
|
||||
@ -4530,6 +4547,12 @@ static const struct dis386 x86_64_table[][2] = {
|
||||
{ "%XEcmp%CCxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
|
||||
},
|
||||
|
||||
/* X86_64_VEX_MAP7_F6_L_0_W_0_R_0 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64) },
|
||||
},
|
||||
|
||||
/* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@ -7287,6 +7310,11 @@ static const struct dis386 vex_len_table[][2] = {
|
||||
{ PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
|
||||
},
|
||||
|
||||
/* VEX_LEN_MAP7_F6 */
|
||||
{
|
||||
{ VEX_W_TABLE (VEX_W_MAP7_F6_L_0) },
|
||||
},
|
||||
|
||||
/* VEX_LEN_MAP7_F8 */
|
||||
{
|
||||
{ VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
|
||||
@ -7898,6 +7926,10 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
/* VEX_W_0F3ADE */
|
||||
{ VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
|
||||
},
|
||||
{
|
||||
/* VEX_W_MAP7_F6_L_0 */
|
||||
{ REG_TABLE (REG_VEX_MAP7_F6_L_0_W_0) },
|
||||
},
|
||||
{
|
||||
/* VEX_W_MAP7_F8_L_0 */
|
||||
{ REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
|
||||
@ -8643,6 +8675,7 @@ static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
|
||||
/* Fetch error indicator. */
|
||||
static const struct dis386 err_opcode = { NULL, { XX }, 0 };
|
||||
|
||||
static const struct dis386 map7_f6_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F6) };
|
||||
static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
|
||||
|
||||
/* Get a pointer to struct dis386 with a valid name. */
|
||||
@ -8956,6 +8989,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
|
||||
ins->condition_code = vindex & 0xf;
|
||||
if (vex_table_index != VEX_MAP7)
|
||||
dp = &vex_table[vex_table_index][vindex];
|
||||
else if (vindex == 0xf6)
|
||||
dp = &map7_f6_opcode;
|
||||
else if (vindex == 0xf8)
|
||||
dp = &map7_f8_opcode;
|
||||
else
|
||||
@ -9117,6 +9152,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
|
||||
dp = &evex_table[vex_table_index][vindex];
|
||||
else if (vindex == 0xf8)
|
||||
dp = &map7_f8_opcode;
|
||||
else if (vindex == 0xf6)
|
||||
dp = &map7_f6_opcode;
|
||||
else
|
||||
dp = &bad_opcode;
|
||||
ins->end_codep = ins->codep;
|
||||
|
||||
@ -281,6 +281,8 @@ static const dependency isa_dependencies[] =
|
||||
"64" },
|
||||
{ "USER_MSR",
|
||||
"64" },
|
||||
{ "MSR_IMM",
|
||||
"64" },
|
||||
{ "APX_F",
|
||||
"XSAVE|64" },
|
||||
};
|
||||
@ -406,6 +408,7 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (FRED),
|
||||
BITFIELD (LKGS),
|
||||
BITFIELD (USER_MSR),
|
||||
BITFIELD (MSR_IMM),
|
||||
BITFIELD (APX_F),
|
||||
BITFIELD (AVX10_2),
|
||||
BITFIELD (MWAITX),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -227,6 +227,8 @@ enum i386_cpu
|
||||
CpuLKGS,
|
||||
/* Intel USER_MSR Instruction support required. */
|
||||
CpuUSER_MSR,
|
||||
/* Intel MSR_IMM Instructions support required. */
|
||||
CpuMSR_IMM,
|
||||
/* Intel AVX10.2 Instructions support required. */
|
||||
CpuAVX10_2,
|
||||
/* mwaitx instruction required */
|
||||
@ -482,6 +484,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpufred:1;
|
||||
unsigned int cpulkgs:1;
|
||||
unsigned int cpuuser_msr:1;
|
||||
unsigned int cpumsr_imm:1;
|
||||
unsigned int cpuavx10_2:1;
|
||||
unsigned int cpumwaitx:1;
|
||||
unsigned int cpuclzero:1;
|
||||
|
||||
@ -3421,6 +3421,14 @@ uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm3
|
||||
|
||||
// USER_MSR instructions end.
|
||||
|
||||
// MSR_IMM instructions.
|
||||
|
||||
rdmsr, 0xf2f6/0, APX_F(MSR_IMM), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
|
||||
// See uwrmsr for the unusual Imm32.
|
||||
wrmsrns, 0xf3f6/0, APX_F(MSR_IMM), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 }
|
||||
|
||||
// MSR_IMM instructions end.
|
||||
|
||||
// APX Push2/Pop2 instructions.
|
||||
//PUSH2/POP2 pushes/pops 2 GPRs at a time to/from the stack. So 2 GPRs are both
|
||||
//Dst/Src, here the V register is used to encode the Operand 1 (Intel format).
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user