mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-29 13:04:46 +08:00
Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
This commit is contained in:
Martin Hunt
parent
e7dd77751d
commit
d70b4d426b
@ -1,3 +1,22 @@
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Wed Aug 28 17:33:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* Makefile.in, d10v_sim.h, interp.c: Fix byte-order problems.
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Mon Aug 26 18:30:28 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* d10v_sim.h (SEXT32): Added.
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* interp.c: Commented out printfs.
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* simops.c: Fixed error in sb and st2w.
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Thu Aug 15 13:30:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* Makefile.in, d10v_sim.h, interp.c, simops.c: Added remaining
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DSP instructions. Added modulo addressing.
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Sun Aug 11 12:57:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* Makefile.in, d10v_sim.h, interp.c, simops.c: Snapshot.
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Fri Aug 2 17:44:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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* d10v_sim.h, simops.c: Snapshot.
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@ -56,7 +56,7 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
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AR = @AR@
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AR_FLAGS = rc
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CC = @CC@
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CFLAGS = @CFLAGS@
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CFLAGS = @CFLAGS@ @DEFS@
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MAKEINFO = makeinfo
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RANLIB = @RANLIB@
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CC_FOR_BUILD = @CC_FOR_BUILD@
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@ -77,7 +77,7 @@ CSEARCH = -I. -I$(srcdir) -I../../include \
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-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh
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DEP = mkdep
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all: run
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all: run libsim.a
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run: interp.o $(X) run.o table.o callback.o simops.o
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$(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm
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@ -86,7 +86,7 @@ interp.o:interp.c table.c
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run.o:run.c
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libsim.a:interp.o table.o simops.o
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$(AR) $(ARFLAGS) libsim.a interp.o table.o
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$(AR) $(ARFLAGS) libsim.a interp.o table.o simops.o
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$(RANLIB) libsim.a
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simops.h: gencode
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@ -95,7 +95,7 @@ simops.h: gencode
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table.c: gencode simops.h
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./gencode >$@
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gencode: gencode.c
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gencode: gencode.c ../../opcodes/libopcodes.a
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$(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc
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.c.o:
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@ -114,7 +114,7 @@ TAGS: force
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clean:
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rm -f *.[oa] *~ core *.E *.p *.ip aout-params.h gen-aout
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rm -f run libsim.a
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rm -f run table.c simops.h gencode libsim.a
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distclean mostlyclean maintainer-clean realclean: clean
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rm -f TAGS
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@ -81,6 +81,12 @@ extern struct simops Simops[];
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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@ -93,17 +99,28 @@ extern struct simops Simops[];
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#ifdef WORDS_BIGENDIAN
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#define RW(x) (*((uint16 *)((x)+State.imem)))
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#define RLW(x) (*((uint32 *)((x)+State.imem)))
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#define SW(addr,data) RW(addr)=data
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#define RW(x) (*((uint16 *)((x)+State.imem)))
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#define RLW(x) (*((uint32 *)((x)+State.imem)))
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#define SW(addr,data) RW(addr)=data
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#define READ_16(x) (*((int16 *)(x)))
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#define WRITE_16(addr,data) (*(int16 *)(addr)=data)
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#define READ_64(x) (*((int64 *)(x)))
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#define WRITE_64(addr,data) (*(int64 *)(addr)=data)
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#else
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uint32 get_longword_swap PARAMS ((uint16 x));
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uint16 get_word_swap PARAMS ((uint16 x));
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void write_word_swap PARAMS ((uint16 addr, uint16 data));
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#define SW(addr,data) write_word_swap(addr,data)
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#define RW(x) get_word_swap(x)
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#define RLW(x) get_longword_swap(x)
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uint32 get_longword PARAMS ((uint8 *));
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uint16 get_word PARAMS ((uint8 *));
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int64 get_longlong PARAMS ((uint8 *));
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void write_word PARAMS ((uint8 *addr, uint16 data));
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void write_longlong PARAMS ((uint8 *addr, int64 data));
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#define SW(addr,data) write_word((long)(addr)+State.imem,data)
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#define RW(x) get_word((long)(x)+State.imem)
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#define RLW(x) get_longword((long)(x)+State.imem)
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#define READ_16(x) get_word(x)
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#define WRITE_16(addr,data) write_word(addr,data)
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#define READ_64(x) get_longlong(x)
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#define WRITE_64(addr,data) write_longlong(addr,data)
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#endif /* not WORDS_BIGENDIAN */
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@ -1,3 +1,4 @@
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#include <signal.h>
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#include "sysdep.h"
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#include "bfd.h"
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#include "remote-sim.h"
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@ -59,30 +60,56 @@ lookup_hash (ins, size)
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}
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uint32
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get_longword_swap (x)
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uint16 x;
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get_longword (x)
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uint8 *x;
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{
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uint8 *a = (uint8 *)(x + State.imem);
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uint8 *a = x;
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return (a[0]<<24) + (a[1]<<16) + (a[2]<<8) + (a[3]);
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}
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uint16
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get_word_swap (x)
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uint16 x;
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int64
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get_longlong (x)
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uint8 *x;
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{
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uint8 *a = (uint8 *)(x + State.imem);
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return (a[0]<<8) + a[1];
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uint8 *a = x;
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return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) +
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((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7];
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}
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uint16
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get_word (x)
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uint8 *x;
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{
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uint8 *a = x;
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return ((uint16)a[0]<<8) + a[1];
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}
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void
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write_word_swap (addr, data)
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uint16 addr, data;
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write_word (addr, data)
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uint8 *addr;
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uint16 data;
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{
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uint8 *a = (uint8 *)(addr + State.imem);
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uint8 *a = addr;
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a[0] = data >> 8;
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a[1] = data & 0xff;
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}
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void
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write_longlong (addr, data)
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uint8 *addr;
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int64 data;
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{
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uint8 *a = addr;
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a[0] = data >> 56;
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a[1] = (data >> 48) & 0xff;
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a[2] = (data >> 40) & 0xff;
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a[3] = (data >> 32) & 0xff;
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a[4] = (data >> 24) & 0xff;
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a[5] = (data >> 16) & 0xff;
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a[6] = (data >> 8) & 0xff;
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a[7] = data & 0xff;
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}
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static void
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get_operands (struct simops *s, uint32 ins)
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@ -127,26 +154,35 @@ do_parallel (ins1, ins2)
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uint16 ins1, ins2;
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{
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struct hash_entry *h1, *h2;
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/* printf ("do_parallel %x || %x\n",ins1,ins2); */
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/* printf ("do_parallel %x || %x\n",ins1,ins2); */
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h1 = lookup_hash (ins1, 0);
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get_operands (h1->ops, ins1);
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h2 = lookup_hash (ins2, 0);
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get_operands (h2->ops, ins2);
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if (h1->ops->exec_type == PARONLY)
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{
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get_operands (h1->ops, ins1);
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(h1->ops->func)();
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if (State.exe)
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(h2->ops->func)();
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{
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get_operands (h2->ops, ins2);
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(h2->ops->func)();
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}
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}
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else if (h2->ops->exec_type == PARONLY)
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{
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get_operands (h2->ops, ins2);
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(h2->ops->func)();
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if (State.exe)
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(h1->ops->func)();
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{
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get_operands (h1->ops, ins1);
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(h1->ops->func)();
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}
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}
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else
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{
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get_operands (h1->ops, ins1);
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(h1->ops->func)();
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get_operands (h2->ops, ins2);
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(h2->ops->func)();
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}
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}
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@ -190,7 +226,7 @@ sim_write (addr, buffer, size)
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int i;
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init_system ();
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printf ("sim_write %d bytes to 0x%x\n",size,addr);
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/* printf ("sim_write %d bytes to 0x%x\n",size,addr); */
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for (i = 0; i < size; i++)
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{
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State.imem[i+addr] = buffer[i];
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@ -257,44 +293,50 @@ sim_resume (step, siggnal)
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int i;
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reg_t oldpc;
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printf ("sim_resume %d %d\n",step,siggnal);
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/* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
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while (1)
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{
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inst = RLW (PC << 2);
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oldpc = PC;
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switch (inst & 0xC0000000)
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{
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case 0xC0000000:
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/* long instruction */
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do_long (inst & 0x3FFFFFFF);
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break;
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case 0x80000000:
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/* R -> L */
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do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
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break;
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case 0x40000000:
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/* L -> R */
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do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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break;
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case 0:
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do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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break;
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}
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if (State.RP && PC == RPT_E)
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{
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RPT_C -= 1;
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if (RPT_C == 0)
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State.RP = 0;
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else
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PC = RPT_S;
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}
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/* FIXME */
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if (PC == oldpc)
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PC++;
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}
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if (step)
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State.exception = SIGTRAP;
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else
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State.exception = 0;
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do
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{
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inst = RLW (PC << 2);
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oldpc = PC;
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switch (inst & 0xC0000000)
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{
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case 0xC0000000:
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/* long instruction */
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do_long (inst & 0x3FFFFFFF);
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break;
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case 0x80000000:
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/* R -> L */
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do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15);
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break;
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case 0x40000000:
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/* L -> R */
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do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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break;
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case 0:
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do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
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break;
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}
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if (State.RP && PC == RPT_E)
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{
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RPT_C -= 1;
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if (RPT_C == 0)
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State.RP = 0;
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else
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PC = RPT_S;
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}
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/* FIXME */
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if (PC == oldpc)
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PC++;
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}
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while (!State.exception);
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}
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int
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@ -308,7 +350,7 @@ void
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sim_info (verbose)
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int verbose;
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{
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printf ("sim_verbose\n");
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printf ("sim_info\n");
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}
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void
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@ -341,5 +383,79 @@ sim_stop_reason (reason, sigrc)
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enum sim_stop *reason;
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int *sigrc;
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{
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printf ("sim_stop_reason\n");
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/* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */
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if (State.exception == SIGQUIT)
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{
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*reason = sim_exited;
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*sigrc = State.exception;
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}
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else
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{
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*reason = sim_stopped;
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*sigrc = State.exception;
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}
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}
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void
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sim_fetch_register (rn, memory)
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int rn;
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unsigned char *memory;
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{
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if (rn > 31)
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{
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WRITE_64 (memory, State.a[rn-32]);
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/* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
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}
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else
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{
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WRITE_16 (memory, State.regs[rn]);
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/* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
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}
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}
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void
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sim_store_register (rn, memory)
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int rn;
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unsigned char *memory;
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{
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if (rn > 31)
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{
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State.a[rn-32] = READ_64 (memory) & MASK40;
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/* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
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}
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else
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{
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State.regs[rn]= READ_16 (memory);
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/* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */
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}
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}
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sim_read (addr, buffer, size)
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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int i;
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for (i = 0; i < size; i++)
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{
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buffer[i] = State.imem[addr + i];
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}
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return size;
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}
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void
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sim_do_command (cmd)
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char *cmd;
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{
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printf("sim_do_command: %s\n",cmd);
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}
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int
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sim_load (prog, from_tty)
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char *prog;
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int from_tty;
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{
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/* Return nonzero so GDB will handle it. */
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return 1;
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}
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