mirrors/binutils-gdb
1
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-23 10:03:47 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

DesCGENization of the BPF binutils port

Browse Source 
CGEN is cool, but the BPF architecture is simply too bizarre for it.

The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port.  The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update.  Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.

This is getting un-maintenable.

So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN.  Overall, this involved:

* To remove the cpu/bpf.{cpu,opc} descriptions.

* To remove the CGEN generated files.

* To replace the CGEN generated opcodes table with a new hand-written
  opcodes table for BPF.

* To replace the CGEN generated disassembler wih a new disassembler
  that uses the new opcodes.

* To replace the CGEN generated assembler with a new assembler that uses the
  new opcodes.

* To replace the CGEN generated simulator with a new simulator that uses the
  new opcodes. [This is pushed in GDB in another patch.]

* To adapt the build systems to the new situation.

Additionally, this patch introduces some extensions and improvements:

* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
  relocation R_BPF_GNU_64_16 are added to the BPF BFD port.  These
  relocations are used for section-relative 16-bit offsets used in
  load/store instructions.

* The disassembler now has support for the "pseudo-c" assembly syntax of
  BPF.  What dialect to use when disassembling is controlled by a command
  line option.

* The disassembler now has support for dumping instruction immediates in
  either octal, hexadecimal or decimal.  The used output base is controlled
  by a new command-line option.

* The GAS BPF test suite has been re-structured and expanded in order to
  test the disassembler pseudoc syntax support.  Minor bugs have been also
  fixed there.  The assembler generic tests that were disabled for bpf-*-*
  targets due to the previous implementation of pseudoc syntax are now
  re-enabled.  Additional tests have been added to test the new features of
  the assembler.  .dump files are no longer used.

* The linker BPF test suite has been adapted to the command line options
  used by the new disassembler.

The result is very satisfactory.  This patchs adds 3448 lines of code
and removes 10542 lines of code.

Tested in:

* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
  little-endian host.

* Target x86-64-linux-gnu with --enable-targets=all

Note that I have not tested in a big-endian host yet.  I will do so
once this lands upstream so I can use the GCC compiler farm.

I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port.  I beg the indulgence of the global maintainers.
This commit is contained in:
Jose E. Marchesi 2023-07-15 00:50:14 +02:00
parent 1c850ca80d
commit d218e7fedc
101 changed files with 3516 additions and 10610 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
bfd/bfd-in2.h
View File

@ -7148,6 +7148,7 @@ assembler and not (currently) written to any object files. */
/* Linux eBPF relocations. */
BFD_RELOC_BPF_64,
BFD_RELOC_BPF_DISP32,
BFD_RELOC_BPF_DISP16,
/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
BFD_RELOC_EPIPHANY_SIMM8,

15
bfd/bpf-reloc.def
View File

@ -72,3 +72,18 @@
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
true) /* pcrel_offset */
/* 16-bit PC-relative address in load instructions. */
BPF_HOWTO (R_BPF_GNU_64_16, /* type */
0, /* rightshift */
2, /* size */
16, /* bitsize */
true, /* pc_relative */
16, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bpf_elf_generic_reloc, /* special_function */
"R_BPF_GNU_64_16", /* name */
true, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
true) /* pcrel_offset */

2
bfd/elf64-bpf.c
View File

@ -89,6 +89,8 @@ bpf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
return &bpf_elf_howto_table[ (int) R_BPF_64_64_IDX];
case BFD_RELOC_BPF_DISP32:
return &bpf_elf_howto_table[ (int) R_BPF_64_32_IDX];
case BFD_RELOC_BPF_DISP16:
return &bpf_elf_howto_table[ (int) R_BPF_GNU_64_16_IDX];
default:
/* Pacify gcc -Wall. */

1
bfd/libbfd.h
View File

@ -3346,6 +3346,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD",
"BFD_RELOC_BPF_64",
"BFD_RELOC_BPF_DISP32",
"BFD_RELOC_BPF_DISP16",
"BFD_RELOC_EPIPHANY_SIMM8",
"BFD_RELOC_EPIPHANY_SIMM24",
"BFD_RELOC_EPIPHANY_HIGH",

2
bfd/reloc.c
View File

@ -7753,6 +7753,8 @@ ENUM
BFD_RELOC_BPF_64
ENUMX
BFD_RELOC_BPF_DISP32
ENUMX
BFD_RELOC_BPF_DISP16
ENUMDOC
Linux eBPF relocations.

855
cpu/bpf.cpu
View File

@ -1,855 +0,0 @@
;; Linux BPF CPU description -*- Scheme -*-
;; Copyright (C) 2019 Free Software Foundation, Inc.
;;
;; Contributed by Oracle Inc.
;;
;; This file is part of the GNU Binutils and of GDB.
;;
;; This program is free software; you can redistribute it and/or
;; modify it under the terms of the GNU General Public License as
;; published by the Free Software Foundation; either version 3 of the
;; License, or (at your option) any later version.
;;
;; This program is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with this program; if not, write to the Free Software
;; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
;; 02110-1301, USA.
;; This file contains a CGEN CPU description for the Linux kernel eBPF
;; instruction set. eBPF is documented in the linux kernel source
;; tree. See linux/Documentation/networking/filter.txt, and also the
;; sources in the networking subsystem, notably
;; linux/net/core/filter.c.
(include "simplify.inc")
(define-arch
(name bpf)
(comment "Linux kernel BPF")
(insn-lsb0? #t)
;; XXX explain the default-alignment setting is for the simulator.
;; It is confusing that the simulator follows the emulated memory
;; access conventions for fetching instructions by pieces...
(default-alignment unaligned)
(machs bpf xbpf)
(isas ebpfle ebpfbe xbpfle xbpfbe))
;;;; The ISAs
;; Logically, eBPF comforms a single instruction set featuring two
;; kind of instructions: 64-bit instructions and 128-bit instructions.
;;
;; The 64-bit instructions have the form:
;;
;; code:8 regs:8 offset:16 imm:32
;;
;; Whereas the 128-bit instructions (at the moment there is only one
;; of such instructions, lddw) have the form:
;;
;; code:8 regs:8 offset:16 imm:32 unused:32 imm:32
;;
;; In both formats `regs' is itself composed by two fields:
;;
;; dst:4 src:4
;;
;; The ISA is supposed to be orthogonal to endianness: the endianness
;; of the instruction fields follow the endianness of the host running
;; the eBPF program, and that's all. However, this is not entirely
;; true. The definition of an eBPF code in the Linux kernel is:
;;
;; struct bpf_insn {
;; __u8 code; /* opcode */
;; __u8 dst_reg:4; /* dest register */
;; __u8 src_reg:4; /* source register */
;; __s16 off; /* signed offset */
;; __s32 imm; /* signed immediate constant */
;; };
;;
;; Since the ordering of fields in C bitmaps is defined by the
;; implementation, the impact of endianness in the encoding of eBPF
;; instructions is effectively defined by GCC. In particular, GCC
;; places dst_reg before src_reg in little-endian code, and the other
;; way around in big-endian code.
;;
;; So, in reality, eBPF comprises two instruction sets: one for
;; little-endian with instructions like:
;;
;; code:8 src:4 dst:4 offset:16 imm:32 [unused:32 imm:32]
;;
;; and another for big-endian with instructions like:
;;
;; code:8 dst:4 src:4 offset:16 imm:32 [unused:32 imm:32]
;;
;; where `offset' and the immediate fields are encoded in
;; little-endian and big-endian byte-order, respectively.
(define-pmacro (define-bpf-isa x-endian)
(define-isa
(name (.sym ebpf x-endian))
(comment "The eBPF instruction set")
;; Default length to record in ifields. This is used in
;; calculations involving bit numbers.
(default-insn-word-bitsize 64)
;; Length of an unknown instruction. Used by disassembly and by the
;; simulator's invalid insn handler.
(default-insn-bitsize 64)
;; Number of bits of insn that can be initially fetched. This is
;; the size of the smallest insn.
(base-insn-bitsize 64)))
(define-bpf-isa le)
(define-bpf-isa be)
(define-pmacro (define-xbpf-isa x-endian)
(define-isa
(name (.sym xbpf x-endian))
(comment "The xBPF instruction set")
(default-insn-word-bitsize 64)
(default-insn-bitsize 64)
(base-insn-bitsize 64)))
(define-xbpf-isa le)
(define-xbpf-isa be)
(define-pmacro all-isas () (ISA ebpfle,ebpfbe,xbpfle,xbpfbe))
(define-pmacro xbpf-isas () (ISA xbpfle,xbpfbe))
(define-pmacro (endian-isas x-endian)
((ISA (.sym ebpf x-endian) (.sym xbpf x-endian))))
;;;; Hardware Hierarchy
;;
;; bpf architecture
;; |
;; bpfbf cpu-family
;; / \
;; bpf xbpf machine
;; | |
;; bpf-def xbpf-def model
(define-cpu
(name bpfbf)
(comment "Linux kernel eBPF virtual CPU")
(insn-endian big)
(word-bitsize 64))
(define-mach
(name bpf)
(comment "Linux eBPF")
(cpu bpfbf)
(isas ebpfle ebpfbe))
(define-model
(name bpf-def)
(comment "Linux eBPF default model")
(mach bpf)
(unit u-exec "execution unit" ()
1 ; issue
1 ; done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
))
(define-mach
(name xbpf)
(comment "Experimental BPF")
(cpu bpfbf)
(isas ebpfle ebpfbe xbpfle xbpfbe))
(define-model
(name xbpf-def)
(comment "xBPF default model")
(mach xbpf)
(unit u-exec "execution unit" ()
1 ; issue
1 ; done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
))
;;;; Hardware Elements
;; eBPF programs can access 10 general-purpose registers which are
;; 64-bit.
(define-hardware
(name h-gpr)
(comment "General Purpose Registers")
(attrs all-isas (MACH bpf xbpf))
(type register DI (16))
(indices keyword "%"
;; XXX the frame pointer fp is read-only, so it should
;; go in a different hardware.
(;; ABI names. Take priority when disassembling.
(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
(r7 7) (r8 8) (r9 9) (fp 10)
;; Additional names recognized when assembling.
(r0 0) (r6 6) (r10 10))))
;; The program counter. CGEN requires it, even if it is not visible
;; to eBPF programs.
(define-hardware
(name h-pc)
(comment "program counter")
(attrs PC PROFILE all-isas)
(type pc UDI)
(get () (raw-reg h-pc))
(set (newval) (set (raw-reg h-pc) newval)))
;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
;; shouldn't be needed, as h-sint is supposed to be able to hold
;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
;; in 32-bit hosts. To be fixed in CGEN.
(dnh h-sint64 "signed 64-bit integer" (all-isas) (immediate DI)
() () ())
;;;; The Instruction Sets
;;; Fields and Opcodes
;; Convenience macro to shorten the definition of the fields below.
(define-pmacro (dwf x-name x-comment x-attrs
x-word-offset x-word-length x-start x-length
x-mode)
"Define a field including its containing word."
(define-ifield
(name x-name)
(comment x-comment)
(.splice attrs (.unsplice x-attrs))
(word-offset x-word-offset)
(word-length x-word-length)
(start x-start)
(length x-length)
(mode x-mode)))
;; For arithmetic and jump instructions the 8-bit code field is
;; subdivided in:
;;
;; op-code:4 op-src:1 op-class:3
(dwf f-op-code "eBPF opcode code" (all-isas) 0 8 7 4 UINT)
(dwf f-op-src "eBPF opcode source" (all-isas) 0 8 3 1 UINT)
(dwf f-op-class "eBPF opcode instruction class" (all-isas) 0 8 2 3 UINT)
(define-normal-insn-enum insn-op-code-alu "eBPF instruction codes"
(all-isas) OP_CODE_ f-op-code
(;; Codes for OP_CLASS_ALU and OP_CLASS_ALU64
(ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5)
(LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb)
(ARSH #xc) (END #xd)
;; xBPF-only: signed div, signed mod
(SDIV #xe) (SMOD #xf)
;; Codes for OP_CLASS_JMP
(JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4)
(JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9)
(JLT #xa) (JLE #xb) (JSLT #xc) (JSLE #xd)))
(define-normal-insn-enum insn-op-src "eBPF instruction source"
(all-isas) OP_SRC_ f-op-src
;; X => use `src' as source operand.
;; K => use `imm32' as source operand.
((K #b0) (X #b1)))
(define-normal-insn-enum insn-op-class "eBPF instruction class"
(all-isas) OP_CLASS_ f-op-class
((LD #b000) (LDX #b001) (ST #b010) (STX #b011)
(ALU #b100) (JMP #b101) (JMP32 #b110) (ALU64 #b111)))
;; For load/store instructions, the 8-bit code field is subdivided in:
;;
;; op-mode:3 op-size:2 op-class:3
(dwf f-op-mode "eBPF opcode mode" (all-isas) 0 8 7 3 UINT)
(dwf f-op-size "eBPF opcode size" (all-isas) 0 8 4 2 UINT)
(define-normal-insn-enum insn-op-mode "eBPF load/store instruction modes"
(all-isas) OP_MODE_ f-op-mode
((IMM #b000) (ABS #b001) (IND #b010) (MEM #b011)
;; #b100 and #b101 are used in classic BPF only, reserved in eBPF.
(XADD #b110)))
(define-normal-insn-enum insn-op-size "eBPF load/store instruction sizes"
(all-isas) OP_SIZE_ f-op-size
((W #b00) ;; Word: 4 byte
(H #b01) ;; Half-word: 2 byte
(B #b10) ;; Byte: 1 byte
(DW #b11))) ;; Double-word: 8 byte
;; The fields for the source and destination registers are a bit
;; tricky. Due to the bizarre nibble swap between little-endian and
;; big-endian ISAs we need to keep different variants of the fields.
;;
;; Note that f-regs is used in the format spec of instructions that do
;; NOT use registers, where endianness is irrelevant i.e. f-regs is a
;; constant 0 opcode.
(dwf f-dstle "eBPF dst register field" ((ISA ebpfle xbpfle)) 8 8 3 4 UINT)
(dwf f-srcle "eBPF source register field" ((ISA ebpfle xbpfle)) 8 8 7 4 UINT)
(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe xbpfbe)) 8 8 7 4 UINT)
(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe xbpfbe)) 8 8 3 4 UINT)
(dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT)
;; Finally, the fields for the immediates.
;;
;; The 16-bit offsets and 32-bit immediates do not present any special
;; difficulty: we put them in their own instruction word so the
;; byte-endianness will be properly applied.
(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 HI)
(dwf f-imm32 "eBPF 32-bit immediate field" (all-isas) 32 32 31 32 INT)
;; For the disjoint 64-bit signed immediate, however, we need to use a
;; multi-ifield.
(dwf f-imm64-a "eBPF 64-bit immediate a" (all-isas) 32 32 31 32 UINT)
(dwf f-imm64-b "eBPF 64-bit immediate b" (all-isas) 64 32 31 32 UINT)
(dwf f-imm64-c "eBPF 64-bit immediate c" (all-isas) 96 32 31 32 UINT)
(define-multi-ifield
(name f-imm64)
(comment "eBPF 64-bit immediate field")
(attrs all-isas)
(mode DI)
(subfields f-imm64-a f-imm64-b f-imm64-c)
(insert (sequence ()
(set (ifield f-imm64-b) (const 0))
(set (ifield f-imm64-c) (srl (ifield f-imm64) (const 32)))
(set (ifield f-imm64-a) (and (ifield f-imm64) (const #xffffffff)))))
(extract (sequence ()
(set (ifield f-imm64)
(or (sll UDI (zext UDI (ifield f-imm64-c)) (const 32))
(zext UDI (ifield f-imm64-a)))))))
;;; Operands
;; A couple of source and destination register operands are defined
;; for each ISA: ebpfle and ebpfbe.
(dno dstle "destination register" ((ISA ebpfle xbpfle)) h-gpr f-dstle)
(dno srcle "source register" ((ISA ebpfle xbpfle)) h-gpr f-srcle)
(dno dstbe "destination register" ((ISA ebpfbe xbpfbe)) h-gpr f-dstbe)
(dno srcbe "source register" ((ISA ebpfbe xbpfbe)) h-gpr f-srcbe)
;; Jump instructions have a 16-bit PC-relative address.
;; CALL instructions have a 32-bit PC-relative address.
(dno disp16 "16-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
f-offset16)
(dno disp32 "32-bit PC-relative address" (all-isas PCREL-ADDR) h-sint
f-imm32)
;; Immediate operands in eBPF are signed, and we want the disassembler
;; to print negative values in a sane way. Therefore we use the macro
;; below to register a printer, which is itself defined as a C
;; function in bpf.opc.
;; define-normal-signed-immediate-operand
(define-pmacro (dnsio x-name x-comment x-attrs x-type x-index)
(define-operand
(name x-name)
(comment x-comment)
(.splice attrs (.unsplice x-attrs))
(type x-type)
(index x-index)
(handlers (print "immediate"))))
(dnsio imm32 "32-bit immediate" (all-isas) h-sint f-imm32)
(dnsio offset16 "16-bit offset" (all-isas) h-sint f-offset16)
;; The 64-bit immediate cannot use the default
;; cgen_parse_signed_integer, because it assumes operands are at much
;; 32-bit wide. Use our own.
(define-operand
(name imm64)
(comment "64-bit immediate")
(attrs all-isas)
(type h-sint64)
(index f-imm64)
(handlers (parse "imm64") (print "immediate")))
;; The endle/endbe instructions take an operand to specify the word
;; width in endianness conversions. We use both a parser and printer,
;; which are defined as C functions in bpf.opc.
(define-operand
(name endsize)
(comment "endianness size immediate: 16, 32 or 64")
(attrs all-isas)
(type h-uint)
(index f-imm32)
(handlers (parse "endsize") (print "endsize")))
;;; ALU instructions
;; For each opcode in insn-op-code-alu representing and integer
;; arithmetic instruction (ADD, SUB, etc) we define a bunch of
;; instruction variants:
;;
;; ADD[32]{i,r}le for the little-endian ISA
;; ADD[32]{i,r}be for the big-endian ISA
;;
;; The `i' variants perform `dst OP imm32 -> dst' operations.
;; The `r' variants perform `dst OP src -> dst' operations.
;;
;; The variants with 32 in their name are of ALU class. Otherwise
;; they are ALU64 class.
(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
x-endian x-mode x-semop)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
(endian-isas x-endian)
(.str x-basename x-suffix " $dst" x-endian)
(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_K x-op-code)
(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
()))
(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
x-endian x-mode x-semop x-isas)
(begin
;; dst = dst OP immediate
(dni (.sym x-basename x-suffix "i" x-endian)
(.str x-basename x-suffix " immediate")
(.splice (.unsplice x-isas))
(.str x-basename x-suffix " $dst" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_K x-op-code)
(set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
())
;; dst = dst OP src
(dni (.sym x-basename x-suffix "r" x-endian)
(.str x-basename x-suffix " register")
(.splice (.unsplice x-isas))
(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
x-op-class OP_SRC_X x-op-code)
(set x-mode (.sym dst x-endian)
(x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
())))
(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
x-endian x-mode)
(begin
(dni (.sym mov x-suffix "i" x-endian)
(.str mov x-suffix " immediate")
(endian-isas x-endian)
(.str x-basename x-suffix " $dst" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_K x-op-code)
(set x-mode (.sym dst x-endian) imm32)
())
(dni (.sym mov x-suffix "r" x-endian)
(.str mov x-suffix " register")
(endian-isas x-endian)
(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
x-op-class OP_SRC_X x-op-code)
(set x-mode (.sym dst x-endian) (.sym src x-endian))
())))
;; Unary ALU instructions (neg)
(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
(begin
(define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
(define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
;; Binary ALU instructions (all the others)
;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
(define-pmacro (daib x-basename x-op-code x-endian x-semop x-isas)
(begin
(define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop x-isas)
(define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop x-isas)))
;; Move ALU instructions (mov)
(define-pmacro (daim x-basename x-op-code x-endian)
(begin
(define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
(define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
(define-pmacro (define-alu-instructions x-endian)
(begin
(daib add OP_CODE_ADD x-endian add (endian-isas x-endian))
(daib sub OP_CODE_SUB x-endian sub (endian-isas x-endian))
(daib mul OP_CODE_MUL x-endian mul (endian-isas x-endian))
(daib div OP_CODE_DIV x-endian udiv (endian-isas x-endian))
(daib or OP_CODE_OR x-endian or (endian-isas x-endian))
(daib and OP_CODE_AND x-endian and (endian-isas x-endian))
(daib lsh OP_CODE_LSH x-endian sll (endian-isas x-endian))
(daib rsh OP_CODE_RSH x-endian srl (endian-isas x-endian))
(daib mod OP_CODE_MOD x-endian umod (endian-isas x-endian))
(daib xor OP_CODE_XOR x-endian xor (endian-isas x-endian))
(daib arsh OP_CODE_ARSH x-endian sra (endian-isas x-endian))
(daib sdiv OP_CODE_SDIV x-endian div ((ISA (.sym xbpf x-endian))))
(daib smod OP_CODE_SMOD x-endian mod ((ISA (.sym xbpf x-endian))))
(daiu neg OP_CODE_NEG x-endian neg)
(daim mov OP_CODE_MOV x-endian)))
(define-alu-instructions le)
(define-alu-instructions be)
;;; Endianness conversion instructions
;; The endianness conversion instructions come in several variants:
;;
;; END{le,be}le for the little-endian ISA
;; END{le,be}be for the big-endian ISA
;;
;; Please do not be confused by the repeated `be' and `le' here. Each
;; ISA has both endle and endbe instructions. It is the disposition
;; of the source and destination register fields that change between
;; ISAs, not the semantics of the instructions themselves (see section
;; "The ISAs" above in this very file.)
(define-pmacro (define-endian-insn x-suffix x-op-src x-endian)
(dni (.sym "end" x-suffix x-endian)
(.str "end" x-suffix " register")
(endian-isas x-endian)
(.str "end" x-suffix " $dst" x-endian ",$endsize")
(+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
OP_CLASS_ALU x-op-src OP_CODE_END)
(set (.sym dst x-endian)
(c-call DI (.str "bpfbf_end" x-suffix) (.sym dst x-endian) endsize))
()))
(define-endian-insn "le" OP_SRC_K le)
(define-endian-insn "be" OP_SRC_X le)
(define-endian-insn "le" OP_SRC_K be)
(define-endian-insn "be" OP_SRC_X be)
;;; Load/Store instructions
;; The lddw instruction takes a 64-bit immediate as an operand. Since
;; this instruction also takes a `dst' operand, we need to define a
;; variant for each ISA:
;;
;; LDDWle for the little-endian ISA
;; LDDWbe for the big-endian ISA
(define-pmacro (define-lddw x-endian)
(dni (.sym lddw x-endian)
(.str "lddw" x-endian)
(endian-isas x-endian)
(.str "lddw $dst" x-endian ",$imm64")
(+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
(.sym dst x-endian)
OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
(set DI (.sym dst x-endian) imm64)
()))
(define-lddw le)
(define-lddw be)
;; The absolute load instructions are non-generic loads designed to be
;; used in socket filters. They come in several variants:
;;
;; LDABS{w,h,b,dw}
(define-pmacro (dlabs x-suffix x-size x-smode)
(dni (.sym "ldabs" x-suffix)
(.str "ldabs" x-suffix)
(all-isas)
(.str "ldabs" x-suffix " $imm32")
(+ imm32 (f-offset16 0) (f-regs 0)
OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
(set x-smode
(reg x-smode h-gpr 0)
(mem x-smode
(add DI
(mem DI
(add DI
(reg DI h-gpr 6) ;; Pointer to struct sk_buff
(c-call "bpfbf_skb_data_offset")))
imm32)))
;; XXX this clobbers R1-R5
()))
(dlabs "w" W SI)
(dlabs "h" H HI)
(dlabs "b" B QI)
(dlabs "dw" DW DI)
;; The indirect load instructions are non-generic loads designed to be
;; used in socket filters. They come in several variants:
;;
;; LDIND{w,h,b,dw}le for the little-endian ISA
;; LDIND[w,h,b,dw}be for the big-endian ISA
(define-pmacro (dlind x-suffix x-size x-endian x-smode)
(dni (.sym "ldind" x-suffix x-endian)
(.str "ldind" x-suffix)
(endian-isas x-endian)
(.str "ldind" x-suffix " $src" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
(set x-smode
(reg x-smode h-gpr 0)
(mem x-smode
(add DI
(mem DI
(add DI
(reg DI h-gpr 6) ;; Pointer to struct sk_buff
(c-call "bpfbf_skb_data_offset")))
(add DI
(.sym src x-endian)
imm32))))
;; XXX this clobbers R1-R5
()))
(define-pmacro (define-ldind x-endian)
(begin
(dlind "w" W x-endian SI)
(dlind "h" H x-endian HI)
(dlind "b" B x-endian QI)
(dlind "dw" DW x-endian DI)))
(define-ldind le)
(define-ldind be)
;; Generic load and store instructions are provided for several word
;; sizes. They come in several variants:
;;
;; LDX{b,h,w,dw}le, STX{b,h,w,dw}le for the little-endian ISA
;;
;; LDX{b,h,w,dw}be, STX{b,h,w,dw}be for the big-endian ISA
;;
;; Loads operate on [$SRC+-OFFSET] -> $DST
;; Stores operate on $SRC -> [$DST+-OFFSET]
(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
(endian-isas x-endian)
(.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
(set x-mode
(.sym dst x-endian)
(mem x-mode (add DI (.sym src x-endian) offset16)))
()))
(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
(endian-isas x-endian)
(.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
(set x-mode
(mem x-mode (add DI (.sym dst x-endian) offset16))
(.sym src x-endian)) ;; XXX address is section-relative
()))
(define-pmacro (define-ldstx-insns x-endian)
(begin
(dxli "ldx" "w" W x-endian SI)
(dxli "ldx" "h" H x-endian HI)
(dxli "ldx" "b" B x-endian QI)
(dxli "ldx" "dw" DW x-endian DI)
(dxsi "stx" "w" W x-endian SI)
(dxsi "stx" "h" H x-endian HI)
(dxsi "stx" "b" B x-endian QI)
(dxsi "stx" "dw" DW x-endian DI)))
(define-ldstx-insns le)
(define-ldstx-insns be)
;; Generic store instructions of the form IMM32 -> [$DST+OFFSET] are
;; provided in several variants:
;;
;; ST{b,h,w,dw}le for the little-endian ISA
;; ST{b,h,w,dw}be for the big-endian ISA
(define-pmacro (dsti x-suffix x-size x-endian x-mode)
(dni (.sym "st" x-suffix x-endian)
(.str "st" x-suffix)
(endian-isas x-endian)
(.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
(+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
(set x-mode
(mem x-mode (add DI (.sym dst x-endian) offset16))
imm32) ;; XXX address is section-relative
()))
(define-pmacro (define-st-insns x-endian)
(begin
(dsti "b" B x-endian QI)
(dsti "h" H x-endian HI)
(dsti "w" W x-endian SI)
(dsti "dw" DW x-endian DI)))
(define-st-insns le)
(define-st-insns be)
;;; Jump instructions
;; Compare-and-jump instructions, on the other hand, make use of
;; registers. Therefore, we need to define several variants in both
;; ISAs:
;;
;; J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
;; little-endian ISA.
;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
;; big-endian ISA.
(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
(begin
(dni (.sym j x-cond x-suffix i x-endian)
(.str j x-cond x-suffix " i")
(endian-isas x-endian)
(.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
(if VOID (x-semop x-mode (.sym dst x-endian) imm32)
(set DI
(reg DI h-pc) (add DI (reg DI h-pc)
(mul DI (add HI disp16 1) 8))))
())
(dni (.sym j x-cond x-suffix r x-endian)
(.str j x-cond x-suffix " r")
(endian-isas x-endian)
(.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
(if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
(set DI
(reg DI h-pc) (add DI (reg DI h-pc)
(mul DI (add HI disp16 1) 8))))
())))
(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
(begin
(define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
(define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
(define-pmacro (define-condjump-insns x-endian)
(begin
(dcji "eq" JEQ x-endian eq)
(dcji "gt" JGT x-endian gtu)
(dcji "ge" JGE x-endian geu)
(dcji "lt" JLT x-endian ltu)
(dcji "le" JLE x-endian leu)
(dcji "set" JSET x-endian and)
(dcji "ne" JNE x-endian ne)
(dcji "sgt" JSGT x-endian gt)
(dcji "sge" JSGE x-endian ge)
(dcji "slt" JSLT x-endian lt)
(dcji "sle" JSLE x-endian le)))
(define-condjump-insns le)
(define-condjump-insns be)
;; The `call' instruction doesn't make use of registers, but the
;; semantic routine should have access to the src register in order to
;; properly interpret the meaning of disp32. Therefore we need one
;; version per ISA.
(define-pmacro (define-call-insn x-endian)
(dni (.sym call x-endian)
"call"
(endian-isas x-endian)
"call $disp32"
(+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0)
OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
(c-call VOID
"bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
()))
(define-call-insn le)
(define-call-insn be)
(define-pmacro (define-callr-insn x-endian)
(dni (.sym callr x-endian)
"callr"
((ISA (.sym xbpf x-endian)))
(.str "call $dst" x-endian)
(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
OP_CLASS_JMP OP_SRC_X OP_CODE_CALL)
(c-call VOID
"bpfbf_callr" (ifield (.sym f-dst x-endian)))
()))
(define-callr-insn le)
(define-callr-insn be)
;; The jump-always and `exit' instructions dont make use of either
;; source nor destination registers, so only one variant per
;; instruction is defined.
(dni ja "ja" (all-isas) "ja $disp16"
(+ (f-imm32 0) disp16 (f-regs 0)
OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
(set DI (reg DI h-pc) (add DI (reg DI h-pc)
(mul DI (add HI disp16 1) 8)))
())
(dni "exit" "exit" (all-isas) "exit"
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
(c-call VOID "bpfbf_exit")
())
;;; Atomic instructions
;; The atomic exchange-and-add instructions come in two flavors: one
;; for swapping 64-bit quantities and another for 32-bit quantities.
(define-pmacro (sem-exchange-and-add x-endian x-mode)
(sequence VOID ((x-mode tmp))
;; XXX acquire lock in simulator... as a hardware element?
(set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
(set x-mode
(mem x-mode (add DI (.sym dst x-endian) offset16))
(add x-mode tmp (.sym src x-endian)))))
(define-pmacro (define-atomic-insns x-endian)
(begin
(dni (.str "xadddw" x-endian)
"xadddw"
(endian-isas x-endian)
(.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
(sem-exchange-and-add x-endian DI)
())
(dni (.str "xaddw" x-endian)
"xaddw"
(endian-isas x-endian)
(.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
(sem-exchange-and-add x-endian SI)
())))
(define-atomic-insns le)
(define-atomic-insns be)
;;; Breakpoint instruction
;; The brkpt instruction is used by the BPF simulator and it doesn't
;; really belong to the eBPF instruction set.
(dni "brkpt" "brkpt" (all-isas) "brkpt"
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
(c-call VOID "bpfbf_breakpoint")
())

191
cpu/bpf.opc
View File

@ -1,191 +0,0 @@
/* EBPF opcode support. -*- c -*-
Copyright (C) 2019 Free Software Foundation, Inc.
Contributed by Oracle, Inc.
This file is part of the GNU Binutils and of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/*
Each section is delimited with start and end markers.
<arch>-opc.h additions use: "-- opc.h"
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h". */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 1
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) 0
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- opc.c */
/* -- asm.c */
/* Parse a signed 64-bit immediate. */
static const char *
parse_imm64 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
int64_t *valuep)
{
bfd_vma value;
enum cgen_parse_operand_result result;
const char *errmsg;
errmsg = (* cd->parse_operand_fn)
(cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
&result, &value);
if (!errmsg)
*valuep = value;
return errmsg;
}
/* Endianness size operands are integer immediates whose values can be
16, 32 or 64. */
static const char *
parse_endsize (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
if (errmsg)
return errmsg;
switch (*valuep)
{
case 16:
case 32:
case 64:
break;
default:
return _("expected 16, 32 or 64 in");
}
return NULL;
}
/* Special check to ensure that the right instruction variant is used
for the given endianness induced by the ISA selected in the CPU.
See bpf.cpu for a discussion on how eBPF is really two instruction
sets. */
int
bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
return cgen_bitset_intersect_p (&isas, cd->isas);
}
/* -- dis.c */
/* We need to customize the disassembler a bit:
- Use 8 bytes per line by default.
*/
#define CGEN_PRINT_INSN bpf_print_insn
static int
bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
bfd_byte buf[CGEN_MAX_INSN_SIZE];
int buflen;
int status;
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
/* Try again with the minimum part, if min < base. */
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
{
buflen = cd->min_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
}
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
return print_insn (cd, pc, info, buf, buflen);
}
/* Signed immediates should be printed in hexadecimal. */
static void
print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
int64_t value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
if (value <= 9)
(*info->fprintf_func) (info->stream, "%" PRId64, value);
else
(*info->fprintf_func) (info->stream, "%#" PRIx64, value);
/* This is to avoid -Wunused-function for print_normal. */
if (0)
print_normal (cd, dis_info, value, attrs, pc, length);
}
/* Endianness bit sizes should be printed in decimal. */
static void
print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
unsigned long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "%lu", value);
}
/* -- */

2585
gas/config/tc-bpf.c
View File

File diff suppressed because it is too large Load Diff

4
gas/config/tc-bpf.h
View File

@ -37,7 +37,6 @@
/* .-foo gets turned into PC relative relocs. */
#define DIFF_EXPR_OK 1
#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
/* Call md_pcrel_from_section(), not md_pcrel_from(). */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
@ -52,4 +51,5 @@
a jump to offset 0 means jump to the next instruction. */
#define md_single_noop_insn "ja 0"
#define TC_EQUAL_IN_INSN(c, s) 1
#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s))
extern bool bpf_tc_equal_in_insn (int, char *);

1
gas/configure vendored
View File

@ -12301,7 +12301,6 @@ cat >>confdefs.h <<_ACEOF
_ACEOF
fi
using_cgen=yes
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes

1
gas/configure.ac
View File

@ -454,7 +454,6 @@ changequote([,])dnl
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
using_cgen=yes
;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes

816
gas/doc/c-bpf.texi
View File

File diff suppressed because it is too large Load Diff

1
gas/testsuite/gas/all/assign-bad-recursive.d
View File

@ -1,5 +1,4 @@
#name: bad recursive assignments
#source: assign-bad-recursive.s
#xfail: bfin-*-*
#notarget: *bpf-*-*
#error_output: assign-bad-recursive.l

2
gas/testsuite/gas/all/eqv-dot.d
View File

@ -2,7 +2,7 @@
#name: eqv involving dot
# bfin doesn't support 'symbol = expression'
# tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte
#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-*
#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-*
# linkrelax targets don't handle equivalence expressions well (nor any
# other forward expression). mep uses complex relocs
#xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-*

5
gas/testsuite/gas/all/gas.exp
View File

@ -105,7 +105,7 @@ if { [istarget "pdp11-*-*"] } then {
run_dump_test eqv-dot
}
if { ![istarget "bfin-*-*"] && ![istarget "bpf-*-*"] } then {
if { ![istarget "bfin-*-*"] } then {
gas_test "assign-ok.s" "" "" "== assignment support"
}
gas_test_error "assign-bad.s" "" "== assignment for symbol already set"
@ -403,8 +403,7 @@ if { ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \
gas_test "fastcall.s" "" "" "fastcall labels"
}
if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] \
&& ![istarget "bpf-*-*"] } then {
if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then {
run_dump_test assign
}
run_dump_test sleb128

66
gas/testsuite/gas/bpf/alu-be-pseudoc.d
View File

@ -1,5 +1,65 @@
#as: --EB
#as: -EB -mdialect=pseudoc
#source: alu-pseudoc.s
#objdump: -dr
#dump: alu-be.dump
#objdump: -dr -M hex,pseudoc
#name: eBPF ALU64 instructions, big endian, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 20 00 00 00 00 02 9a r2\+=0x29a
8: 07 30 00 00 ff ff fd 66 r3\+=0xfffffd66
10: 07 40 00 00 7e ad be ef r4\+=0x7eadbeef
18: 0f 56 00 00 00 00 00 00 r5\+=r6
20: 17 20 00 00 00 00 02 9a r2-=0x29a
28: 17 30 00 00 ff ff fd 66 r3-=0xfffffd66
30: 17 40 00 00 7e ad be ef r4-=0x7eadbeef
38: 1f 56 00 00 00 00 00 00 r5-=r6
40: 27 20 00 00 00 00 02 9a r2\*=0x29a
48: 27 30 00 00 ff ff fd 66 r3\*=0xfffffd66
50: 27 40 00 00 7e ad be ef r4\*=0x7eadbeef
58: 2f 56 00 00 00 00 00 00 r5\*=r6
60: 37 20 00 00 00 00 02 9a r2/=0x29a
68: 37 30 00 00 ff ff fd 66 r3/=0xfffffd66
70: 37 40 00 00 7e ad be ef r4/=0x7eadbeef
78: 3f 56 00 00 00 00 00 00 r5/=r6
80: 47 20 00 00 00 00 02 9a r2|=0x29a
88: 47 30 00 00 ff ff fd 66 r3|=0xfffffd66
90: 47 40 00 00 7e ad be ef r4|=0x7eadbeef
98: 4f 56 00 00 00 00 00 00 r5|=r6
a0: 57 20 00 00 00 00 02 9a r2&=0x29a
a8: 57 30 00 00 ff ff fd 66 r3&=0xfffffd66
b0: 57 40 00 00 7e ad be ef r4&=0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 r5&=r6
c0: 67 20 00 00 00 00 02 9a r2<<=0x29a
c8: 67 30 00 00 ff ff fd 66 r3<<=0xfffffd66
d0: 67 40 00 00 7e ad be ef r4<<=0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 r5<<=r6
e0: 77 20 00 00 00 00 02 9a r2>>=0x29a
e8: 77 30 00 00 ff ff fd 66 r3>>=0xfffffd66
f0: 77 40 00 00 7e ad be ef r4>>=0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 r5>>=r6
100: 97 20 00 00 00 00 02 9a r2%=0x29a
108: 97 30 00 00 ff ff fd 66 r3%=0xfffffd66
110: 97 40 00 00 7e ad be ef r4%=0x7eadbeef
118: 9f 56 00 00 00 00 00 00 r5%=r6
120: a7 20 00 00 00 00 02 9a r2\^=0x29a
128: a7 30 00 00 ff ff fd 66 r3\^=0xfffffd66
130: a7 40 00 00 7e ad be ef r4\^=0x7eadbeef
138: af 56 00 00 00 00 00 00 r5\^=r6
140: b7 20 00 00 00 00 02 9a r2=0x29a
148: b7 30 00 00 ff ff fd 66 r3=0xfffffd66
150: b7 40 00 00 7e ad be ef r4=0x7eadbeef
158: bf 56 00 00 00 00 00 00 r5=r6
160: c7 20 00 00 00 00 02 9a r2 s>>=0x29a
168: c7 30 00 00 ff ff fd 66 r3 s>>=0xfffffd66
170: c7 40 00 00 7e ad be ef r4 s>>=0x7eadbeef
178: cf 56 00 00 00 00 00 00 r5 s>>=r6
180: 8f 23 00 00 00 00 00 00 r2=-r3
188: d4 90 00 00 00 00 00 10 r9=le16 r9
190: d4 80 00 00 00 00 00 20 r8=le32 r8
198: d4 70 00 00 00 00 00 40 r7=le64 r7
1a0: dc 60 00 00 00 00 00 10 r6=be16 r6
1a8: dc 50 00 00 00 00 00 20 r5=be32 r5
1b0: dc 40 00 00 00 00 00 40 r4=be64 r4

68
gas/testsuite/gas/bpf/alu-be.d
View File

@ -1,5 +1,65 @@
#as: --EB
#as: -EB -mdialect=normal
#source: alu.s
#objdump: -dr
#dump: alu-be.dump
#name: eBPF ALU64 instructions, big endian, normal syntax
#objdump: -dr -M hex
#name: eBPF ALU instructions, big endian, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 20 00 00 00 00 02 9a add %r2,0x29a
8: 07 30 00 00 ff ff fd 66 add %r3,0xfffffd66
10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
18: 0f 56 00 00 00 00 00 00 add %r5,%r6
20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
28: 17 30 00 00 ff ff fd 66 sub %r3,0xfffffd66
30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
48: 27 30 00 00 ff ff fd 66 mul %r3,0xfffffd66
50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
60: 37 20 00 00 00 00 02 9a div %r2,0x29a
68: 37 30 00 00 ff ff fd 66 div %r3,0xfffffd66
70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
78: 3f 56 00 00 00 00 00 00 div %r5,%r6
80: 47 20 00 00 00 00 02 9a or %r2,0x29a
88: 47 30 00 00 ff ff fd 66 or %r3,0xfffffd66
90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
98: 4f 56 00 00 00 00 00 00 or %r5,%r6
a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
a8: 57 30 00 00 ff ff fd 66 and %r3,0xfffffd66
b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
c8: 67 30 00 00 ff ff fd 66 lsh %r3,0xfffffd66
d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
e8: 77 30 00 00 ff ff fd 66 rsh %r3,0xfffffd66
f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
108: 97 30 00 00 ff ff fd 66 mod %r3,0xfffffd66
110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
128: a7 30 00 00 ff ff fd 66 xor %r3,0xfffffd66
130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
138: af 56 00 00 00 00 00 00 xor %r5,%r6
140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
148: b7 30 00 00 ff ff fd 66 mov %r3,0xfffffd66
150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
158: bf 56 00 00 00 00 00 00 mov %r5,%r6
160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
168: c7 30 00 00 ff ff fd 66 arsh %r3,0xfffffd66
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 23 00 00 00 00 00 00 neg %r2,%r3
188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64
1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
1b0: dc 40 00 00 00 00 00 40 endbe %r4,64

54
gas/testsuite/gas/bpf/alu-be.dump
View File

@ -1,54 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 20 00 00 00 00 02 9a add %r2,0x29a
8: 07 30 00 00 ff ff fd 66 add %r3,-666
10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
18: 0f 56 00 00 00 00 00 00 add %r5,%r6
20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
28: 17 30 00 00 ff ff fd 66 sub %r3,-666
30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
38: 1f 56 00 00 00 00 00 00 sub %r5,%r6
40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
48: 27 30 00 00 ff ff fd 66 mul %r3,-666
50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
58: 2f 56 00 00 00 00 00 00 mul %r5,%r6
60: 37 20 00 00 00 00 02 9a div %r2,0x29a
68: 37 30 00 00 ff ff fd 66 div %r3,-666
70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
78: 3f 56 00 00 00 00 00 00 div %r5,%r6
80: 47 20 00 00 00 00 02 9a or %r2,0x29a
88: 47 30 00 00 ff ff fd 66 or %r3,-666
90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
98: 4f 56 00 00 00 00 00 00 or %r5,%r6
a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
a8: 57 30 00 00 ff ff fd 66 and %r3,-666
b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
b8: 5f 56 00 00 00 00 00 00 and %r5,%r6
c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6
100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
108: 97 30 00 00 ff ff fd 66 mod %r3,-666
110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
118: 9f 56 00 00 00 00 00 00 mod %r5,%r6
120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
128: a7 30 00 00 ff ff fd 66 xor %r3,-666
130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
138: af 56 00 00 00 00 00 00 xor %r5,%r6
140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
148: b7 30 00 00 ff ff fd 66 mov %r3,-666
150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
158: bf 56 00 00 00 00 00 00 mov %r5,%r6
160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 87 20 00 00 00 00 00 00 neg %r2

68
gas/testsuite/gas/bpf/alu-pseudoc.d
View File

@ -1,5 +1,65 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: alu-pseudoc.s
#dump: alu.dump
#name: eBPF ALU64 instructions, pseudo-c syntax
#name: eBPF ALU instructions, pseudo-c syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 02 00 00 9a 02 00 00 r2\+=0x29a
8: 07 03 00 00 66 fd ff ff r3\+=0xfffffd66
10: 07 04 00 00 ef be ad 7e r4\+=0x7eadbeef
18: 0f 65 00 00 00 00 00 00 r5\+=r6
20: 17 02 00 00 9a 02 00 00 r2-=0x29a
28: 17 03 00 00 66 fd ff ff r3-=0xfffffd66
30: 17 04 00 00 ef be ad 7e r4-=0x7eadbeef
38: 1f 65 00 00 00 00 00 00 r5-=r6
40: 27 02 00 00 9a 02 00 00 r2\*=0x29a
48: 27 03 00 00 66 fd ff ff r3\*=0xfffffd66
50: 27 04 00 00 ef be ad 7e r4\*=0x7eadbeef
58: 2f 65 00 00 00 00 00 00 r5\*=r6
60: 37 02 00 00 9a 02 00 00 r2/=0x29a
68: 37 03 00 00 66 fd ff ff r3/=0xfffffd66
70: 37 04 00 00 ef be ad 7e r4/=0x7eadbeef
78: 3f 65 00 00 00 00 00 00 r5/=r6
80: 47 02 00 00 9a 02 00 00 r2|=0x29a
88: 47 03 00 00 66 fd ff ff r3|=0xfffffd66
90: 47 04 00 00 ef be ad 7e r4|=0x7eadbeef
98: 4f 65 00 00 00 00 00 00 r5|=r6
a0: 57 02 00 00 9a 02 00 00 r2&=0x29a
a8: 57 03 00 00 66 fd ff ff r3&=0xfffffd66
b0: 57 04 00 00 ef be ad 7e r4&=0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 r5&=r6
c0: 67 02 00 00 9a 02 00 00 r2<<=0x29a
c8: 67 03 00 00 66 fd ff ff r3<<=0xfffffd66
d0: 67 04 00 00 ef be ad 7e r4<<=0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 r5<<=r6
e0: 77 02 00 00 9a 02 00 00 r2>>=0x29a
e8: 77 03 00 00 66 fd ff ff r3>>=0xfffffd66
f0: 77 04 00 00 ef be ad 7e r4>>=0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 r5>>=r6
100: 97 02 00 00 9a 02 00 00 r2%=0x29a
108: 97 03 00 00 66 fd ff ff r3%=0xfffffd66
110: 97 04 00 00 ef be ad 7e r4%=0x7eadbeef
118: 9f 65 00 00 00 00 00 00 r5%=r6
120: a7 02 00 00 9a 02 00 00 r2\^=0x29a
128: a7 03 00 00 66 fd ff ff r3\^=0xfffffd66
130: a7 04 00 00 ef be ad 7e r4\^=0x7eadbeef
138: af 65 00 00 00 00 00 00 r5\^=r6
140: b7 02 00 00 9a 02 00 00 r2=0x29a
148: b7 03 00 00 66 fd ff ff r3=0xfffffd66
150: b7 04 00 00 ef be ad 7e r4=0x7eadbeef
158: bf 65 00 00 00 00 00 00 r5=r6
160: c7 02 00 00 9a 02 00 00 r2 s>>=0x29a
168: c7 03 00 00 66 fd ff ff r3 s>>=0xfffffd66
170: c7 04 00 00 ef be ad 7e r4 s>>=0x7eadbeef
178: cf 65 00 00 00 00 00 00 r5 s>>=r6
180: 8f 32 00 00 00 00 00 00 r2=-r3
188: d4 09 00 00 10 00 00 00 r9=le16 r9
190: d4 08 00 00 20 00 00 00 r8=le32 r8
198: d4 07 00 00 40 00 00 00 r7=le64 r7
1a0: dc 06 00 00 10 00 00 00 r6=be16 r6
1a8: dc 05 00 00 20 00 00 00 r5=be32 r5
1b0: dc 04 00 00 40 00 00 00 r4=be64 r4

8
gas/testsuite/gas/bpf/alu-pseudoc.s
View File

@ -48,4 +48,10 @@
r3 s>>= -666
r4 s>>= 2125315823
r5 s>>= r6
r2 = -r2
r2 = - r3
r9 = le16 r9
r8 = le32 r8
r7 = le64 r7
r6 = be16 r6
r5 = be32 r5
r4 = be64 r4

17
gas/testsuite/gas/bpf/alu-xbpf.d
View File

@ -1,17 +0,0 @@
#as: --EL -mxbpf
#objdump: -dr -mxbpf
#name: xBPF ALU64 insns
.*: +file format .*bpf.*
Disassembly of section \.text:
0+ <\.text>:
0: e7 02 00 00 02 00 00 00 sdiv %r2,2
8: e7 03 00 00 fd ff ff ff sdiv %r3,-3
10: e7 04 00 00 ef be ad 7e sdiv %r4,0x7eadbeef
18: ef 25 00 00 00 00 00 00 sdiv %r5,%r2
20: f7 02 00 00 03 00 00 00 smod %r2,3
28: f7 03 00 00 fc ff ff ff smod %r3,-4
30: f7 04 00 00 ef be ad 7e smod %r4,0x7eadbeef
38: ff 25 00 00 00 00 00 00 smod %r5,%r2

11
gas/testsuite/gas/bpf/alu-xbpf.s
View File

@ -1,11 +0,0 @@
# Tests for xBPF-specific alu instructions
.text
sdiv %r2, 2
sdiv %r3, -3
sdiv %r4, 0x7eadbeef
sdiv %r5, %r2
smod %r2, 3
smod %r3, -4
smod %r4, 0x7eadbeef
smod %r5, %r2

68
gas/testsuite/gas/bpf/alu.d
View File

@ -1,5 +1,65 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#source: alu.s
#dump: alu.dump
#name: eBPF ALU64 instructions, normal syntax
#name: eBPF ALU instructions, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
8: 07 03 00 00 66 fd ff ff add %r3,0xfffffd66
10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
18: 0f 65 00 00 00 00 00 00 add %r5,%r6
20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
28: 17 03 00 00 66 fd ff ff sub %r3,0xfffffd66
30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
48: 27 03 00 00 66 fd ff ff mul %r3,0xfffffd66
50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
68: 37 03 00 00 66 fd ff ff div %r3,0xfffffd66
70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
78: 3f 65 00 00 00 00 00 00 div %r5,%r6
80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
88: 47 03 00 00 66 fd ff ff or %r3,0xfffffd66
90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
98: 4f 65 00 00 00 00 00 00 or %r5,%r6
a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
a8: 57 03 00 00 66 fd ff ff and %r3,0xfffffd66
b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
c8: 67 03 00 00 66 fd ff ff lsh %r3,0xfffffd66
d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
e8: 77 03 00 00 66 fd ff ff rsh %r3,0xfffffd66
f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
108: 97 03 00 00 66 fd ff ff mod %r3,0xfffffd66
110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
128: a7 03 00 00 66 fd ff ff xor %r3,0xfffffd66
130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
138: af 65 00 00 00 00 00 00 xor %r5,%r6
140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
148: b7 03 00 00 66 fd ff ff mov %r3,0xfffffd66
150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
158: bf 65 00 00 00 00 00 00 mov %r5,%r6
160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
168: c7 03 00 00 66 fd ff ff arsh %r3,0xfffffd66
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 32 00 00 00 00 00 00 neg %r2,%r3
188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64
1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
1b0: dc 04 00 00 40 00 00 00 endbe %r4,64

54
gas/testsuite/gas/bpf/alu.dump
View File

@ -1,54 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
8: 07 03 00 00 66 fd ff ff add %r3,-666
10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
18: 0f 65 00 00 00 00 00 00 add %r5,%r6
20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
28: 17 03 00 00 66 fd ff ff sub %r3,-666
30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
38: 1f 65 00 00 00 00 00 00 sub %r5,%r6
40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
48: 27 03 00 00 66 fd ff ff mul %r3,-666
50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
58: 2f 65 00 00 00 00 00 00 mul %r5,%r6
60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
68: 37 03 00 00 66 fd ff ff div %r3,-666
70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
78: 3f 65 00 00 00 00 00 00 div %r5,%r6
80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
88: 47 03 00 00 66 fd ff ff or %r3,-666
90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
98: 4f 65 00 00 00 00 00 00 or %r5,%r6
a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
a8: 57 03 00 00 66 fd ff ff and %r3,-666
b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
b8: 5f 65 00 00 00 00 00 00 and %r5,%r6
c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6
e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6
100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
108: 97 03 00 00 66 fd ff ff mod %r3,-666
110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
118: 9f 65 00 00 00 00 00 00 mod %r5,%r6
120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
128: a7 03 00 00 66 fd ff ff xor %r3,-666
130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
138: af 65 00 00 00 00 00 00 xor %r5,%r6
140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
148: b7 03 00 00 66 fd ff ff mov %r3,-666
150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
158: bf 65 00 00 00 00 00 00 mov %r5,%r6
160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
168: c7 03 00 00 66 fd ff ff arsh %r3,-666
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 87 02 00 00 00 00 00 00 neg %r2

8
gas/testsuite/gas/bpf/alu.s
View File

@ -48,4 +48,10 @@
arsh %r3, -666
arsh %r4, 0x7eadbeef
arsh %r5, %r6
neg %r2
neg %r2, %r3
endle %r9,16
endle %r8,32
endle %r7,64
endbe %r6,16
endbe %r5,32
endbe %r4,64

62
gas/testsuite/gas/bpf/alu32-be-pseudoc.d
View File

@ -1,5 +1,59 @@
#as: --EB
#objdump: -dr
#as: -EB -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: alu32-pseudoc.s
#dump: alu32-be.dump
#name: eBPF ALU instructions, big-endian, pseudo-c syntax
#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 20 00 00 00 00 02 9a w2\+=0x29a
8: 04 30 00 00 ff ff fd 66 w3\+=0xfffffd66
10: 04 40 00 00 7e ad be ef w4\+=0x7eadbeef
18: 0c 56 00 00 00 00 00 00 w5\+=w6
20: 14 20 00 00 00 00 02 9a w2-=0x29a
28: 14 30 00 00 ff ff fd 66 w3-=0xfffffd66
30: 14 40 00 00 7e ad be ef w4-=0x7eadbeef
38: 1c 56 00 00 00 00 00 00 w5-=w6
40: 24 20 00 00 00 00 02 9a w2\*=0x29a
48: 24 30 00 00 ff ff fd 66 w3\*=0xfffffd66
50: 24 40 00 00 7e ad be ef w4\*=0x7eadbeef
58: 2c 56 00 00 00 00 00 00 w5\*=w6
60: 34 20 00 00 00 00 02 9a w2/=0x29a
68: 34 30 00 00 ff ff fd 66 w3/=0xfffffd66
70: 34 40 00 00 7e ad be ef w4/=0x7eadbeef
78: 3c 56 00 00 00 00 00 00 w5/=w6
80: 44 20 00 00 00 00 02 9a w2|=0x29a
88: 44 30 00 00 ff ff fd 66 w3|=0xfffffd66
90: 44 40 00 00 7e ad be ef w4|=0x7eadbeef
98: 4c 56 00 00 00 00 00 00 w5|=w6
a0: 54 20 00 00 00 00 02 9a w2&=0x29a
a8: 54 30 00 00 ff ff fd 66 w3&=0xfffffd66
b0: 54 40 00 00 7e ad be ef w4&=0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 w5&=w6
c0: 64 20 00 00 00 00 02 9a w2<<=0x29a
c8: 64 30 00 00 ff ff fd 66 w3<<=0xfffffd66
d0: 64 40 00 00 7e ad be ef w4<<=0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 w5<<=w6
e0: 74 20 00 00 00 00 02 9a w2>>=0x29a
e8: 74 30 00 00 ff ff fd 66 w3>>=0xfffffd66
f0: 74 40 00 00 7e ad be ef w4>>=0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 w5>>=w6
100: 94 20 00 00 00 00 02 9a w2%=0x29a
108: 94 30 00 00 ff ff fd 66 w3%=0xfffffd66
110: 94 40 00 00 7e ad be ef w4%=0x7eadbeef
118: 9c 56 00 00 00 00 00 00 w5%=w6
120: a4 20 00 00 00 00 02 9a w2\^=0x29a
128: a4 30 00 00 ff ff fd 66 w3\^=0xfffffd66
130: a4 40 00 00 7e ad be ef w4\^=0x7eadbeef
138: ac 56 00 00 00 00 00 00 w5\^=w6
140: b4 20 00 00 00 00 02 9a w2=0x29a
148: b4 30 00 00 ff ff fd 66 w3=0xfffffd66
150: b4 40 00 00 7e ad be ef w4=0x7eadbeef
158: bc 56 00 00 00 00 00 00 w5=w6
160: c4 20 00 00 00 00 02 9a w2 s>>=0x29a
168: c4 30 00 00 ff ff fd 66 w3 s>>=0xfffffd66
170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef
178: cc 56 00 00 00 00 00 00 w5 s>>=w6
180: 8c 23 00 00 00 00 00 00 w2=-w3

64
gas/testsuite/gas/bpf/alu32-be.d
View File

@ -1,5 +1,59 @@
#as: --EB
#objdump: -dr
#source: alu32-pseudoc.s
#dump: alu32-be.dump
#name: eBPF ALU instructions, big-endian, normal syntax
#as: -EB -mdialect=normal
#objdump: -dr -M hex
#source: alu32.s
#name: eBPF ALU32 instructions, big-endian, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
8: 04 30 00 00 ff ff fd 66 add32 %r3,0xfffffd66
10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
28: 14 30 00 00 ff ff fd 66 sub32 %r3,0xfffffd66
30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
48: 24 30 00 00 ff ff fd 66 mul32 %r3,0xfffffd66
50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
68: 34 30 00 00 ff ff fd 66 div32 %r3,0xfffffd66
70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
88: 44 30 00 00 ff ff fd 66 or32 %r3,0xfffffd66
90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
a8: 54 30 00 00 ff ff fd 66 and32 %r3,0xfffffd66
b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,0xfffffd66
d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,0xfffffd66
f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
108: 94 30 00 00 ff ff fd 66 mod32 %r3,0xfffffd66
110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
128: a4 30 00 00 ff ff fd 66 xor32 %r3,0xfffffd66
130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
148: b4 30 00 00 ff ff fd 66 mov32 %r3,0xfffffd66
150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,0xfffffd66
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3

60
gas/testsuite/gas/bpf/alu32-be.dump
View File

@ -1,60 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6
20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6
80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 20 00 00 00 00 00 00 neg32 %r2
188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64
1a0: dc 60 00 00 00 00 00 10 endbe %r6,16
1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
1b0: dc 40 00 00 00 00 00 40 endbe %r4,64

62
gas/testsuite/gas/bpf/alu32-pseudoc.d
View File

@ -1,5 +1,59 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: alu32-pseudoc.s
#dump: alu32.dump
#name: eBPF ALU instructions, pseudo-c syntax
#name: eBPF ALU32 instructions, pseudo-c syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 02 00 00 9a 02 00 00 w2\+=0x29a
8: 04 03 00 00 66 fd ff ff w3\+=0xfffffd66
10: 04 04 00 00 ef be ad 7e w4\+=0x7eadbeef
18: 0c 65 00 00 00 00 00 00 w5\+=w6
20: 14 02 00 00 9a 02 00 00 w2-=0x29a
28: 14 03 00 00 66 fd ff ff w3-=0xfffffd66
30: 14 04 00 00 ef be ad 7e w4-=0x7eadbeef
38: 1c 65 00 00 00 00 00 00 w5-=w6
40: 24 02 00 00 9a 02 00 00 w2\*=0x29a
48: 24 03 00 00 66 fd ff ff w3\*=0xfffffd66
50: 24 04 00 00 ef be ad 7e w4\*=0x7eadbeef
58: 2c 65 00 00 00 00 00 00 w5\*=w6
60: 34 02 00 00 9a 02 00 00 w2/=0x29a
68: 34 03 00 00 66 fd ff ff w3/=0xfffffd66
70: 34 04 00 00 ef be ad 7e w4/=0x7eadbeef
78: 3c 65 00 00 00 00 00 00 w5/=w6
80: 44 02 00 00 9a 02 00 00 w2|=0x29a
88: 44 03 00 00 66 fd ff ff w3|=0xfffffd66
90: 44 04 00 00 ef be ad 7e w4|=0x7eadbeef
98: 4c 65 00 00 00 00 00 00 w5|=w6
a0: 54 02 00 00 9a 02 00 00 w2&=0x29a
a8: 54 03 00 00 66 fd ff ff w3&=0xfffffd66
b0: 54 04 00 00 ef be ad 7e w4&=0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 w5&=w6
c0: 64 02 00 00 9a 02 00 00 w2<<=0x29a
c8: 64 03 00 00 66 fd ff ff w3<<=0xfffffd66
d0: 64 04 00 00 ef be ad 7e w4<<=0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 w5<<=w6
e0: 74 02 00 00 9a 02 00 00 w2>>=0x29a
e8: 74 03 00 00 66 fd ff ff w3>>=0xfffffd66
f0: 74 04 00 00 ef be ad 7e w4>>=0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 w5>>=w6
100: 94 02 00 00 9a 02 00 00 w2%=0x29a
108: 94 03 00 00 66 fd ff ff w3%=0xfffffd66
110: 94 04 00 00 ef be ad 7e w4%=0x7eadbeef
118: 9c 65 00 00 00 00 00 00 w5%=w6
120: a4 02 00 00 9a 02 00 00 w2\^=0x29a
128: a4 03 00 00 66 fd ff ff w3\^=0xfffffd66
130: a4 04 00 00 ef be ad 7e w4\^=0x7eadbeef
138: ac 65 00 00 00 00 00 00 w5\^=w6
140: b4 02 00 00 9a 02 00 00 w2=0x29a
148: b4 03 00 00 66 fd ff ff w3=0xfffffd66
150: b4 04 00 00 ef be ad 7e w4=0x7eadbeef
158: bc 65 00 00 00 00 00 00 w5=w6
160: c4 02 00 00 9a 02 00 00 w2 s>>=0x29a
168: c4 03 00 00 66 fd ff ff w3 s>>=0xfffffd66
170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef
178: cc 65 00 00 00 00 00 00 w5 s>>=w6
180: 8c 32 00 00 00 00 00 00 w2=-w3

30
gas/testsuite/gas/bpf/alu32-pseudoc.s
View File

@ -1,16 +1,16 @@
# Tests for the ALU eBPF pseudo-C instructions
.text
W2 += 666
W3 += -666
W4 += 2125315823
W5 += w6
W2 -= 666
W3 -= -666
W4 -= 2125315823
W5 -= w6
W2 *= 666
W3 *= -666
W4 *= 2125315823
w2 += 666
w3 += -666
w4 += 2125315823
w5 += w6
w2 -= 666
w3 -= -666
w4 -= 2125315823
w5 -= w6
w2 *= 666
w3 *= -666
w4 *= 2125315823
w5 *= w6
w2 /= 666
w3 /= -666
@ -48,10 +48,4 @@
w3 s>>= -666
w4 s>>= 2125315823
w5 s>>= w6
w2 = -w2
r9 = le16 r9
r8 = le32 r8
r7 = le64 r7
r6 = be16 r6
r5 = be32 r5
r4 = be64 r4
w2 = - w3

17
gas/testsuite/gas/bpf/alu32-xbpf.d
View File

@ -1,17 +0,0 @@
#as: --EL -mxbpf
#objdump: -dr -mxbpf
#name: xBPF ALU32 insns
.*: +file format .*bpf.*
Disassembly of section \.text:
0+ <\.text>:
0: e4 02 00 00 02 00 00 00 sdiv32 %r2,2
8: e4 03 00 00 fd ff ff ff sdiv32 %r3,-3
10: e4 04 00 00 ef be ad 7e sdiv32 %r4,0x7eadbeef
18: ec 25 00 00 00 00 00 00 sdiv32 %r5,%r2
20: f4 02 00 00 03 00 00 00 smod32 %r2,3
28: f4 03 00 00 fc ff ff ff smod32 %r3,-4
30: f4 04 00 00 ef be ad 7e smod32 %r4,0x7eadbeef
38: fc 25 00 00 00 00 00 00 smod32 %r5,%r2

11
gas/testsuite/gas/bpf/alu32-xbpf.s
View File

@ -1,11 +0,0 @@
# Tests for xBPF-specific alu instructions
.text
sdiv32 %r2, 2
sdiv32 %r3, -3
sdiv32 %r4, 0x7eadbeef
sdiv32 %r5, %r2
smod32 %r2, 3
smod32 %r3, -4
smod32 %r4, 0x7eadbeef
smod32 %r5, %r2

62
gas/testsuite/gas/bpf/alu32.d
View File

@ -1,5 +1,59 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#source: alu32.s
#dump: alu32.dump
#name: eBPF ALU instructions, normal syntax
#name: eBPF ALU32 instructions, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
8: 04 03 00 00 66 fd ff ff add32 %r3,0xfffffd66
10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
28: 14 03 00 00 66 fd ff ff sub32 %r3,0xfffffd66
30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
48: 24 03 00 00 66 fd ff ff mul32 %r3,0xfffffd66
50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
68: 34 03 00 00 66 fd ff ff div32 %r3,0xfffffd66
70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
88: 44 03 00 00 66 fd ff ff or32 %r3,0xfffffd66
90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
a8: 54 03 00 00 66 fd ff ff and32 %r3,0xfffffd66
b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
c8: 64 03 00 00 66 fd ff ff lsh32 %r3,0xfffffd66
d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
e8: 74 03 00 00 66 fd ff ff rsh32 %r3,0xfffffd66
f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
108: 94 03 00 00 66 fd ff ff mod32 %r3,0xfffffd66
110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
128: a4 03 00 00 66 fd ff ff xor32 %r3,0xfffffd66
130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
148: b4 03 00 00 66 fd ff ff mov32 %r3,0xfffffd66
150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
168: c4 03 00 00 66 fd ff ff arsh32 %r3,0xfffffd66
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3

60
gas/testsuite/gas/bpf/alu32.dump
View File

@ -1,60 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
8: 04 03 00 00 66 fd ff ff add32 %r3,-666
10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6
20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6
40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6
60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
68: 34 03 00 00 66 fd ff ff div32 %r3,-666
70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6
80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
88: 44 03 00 00 66 fd ff ff or32 %r3,-666
90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6
a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6
c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6
e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6
100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6
120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6
140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6
160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 84 02 00 00 00 00 00 00 neg32 %r2
188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64
1a0: dc 06 00 00 10 00 00 00 endbe %r6,16
1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
1b0: dc 04 00 00 40 00 00 00 endbe %r4,64

8
gas/testsuite/gas/bpf/alu32.s
View File

@ -48,10 +48,4 @@
arsh32 %r3, -666
arsh32 %r4, 0x7eadbeef
arsh32 %r5, %r6
neg32 %r2
endle %r9,16
endle %r8,32
endle %r7,64
endbe %r6,16
endbe %r5,32
endbe %r4,64
neg32 %r2, %r3

12
gas/testsuite/gas/bpf/atomic-be-pseudoc.d Normal file
View File

@ -0,0 +1,12 @@
#as: -EB -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: atomic-pseudoc.s
#name: eBPF atomic instructions, pseudoc syntax, big endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 12 1e ef 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
8: c3 12 1e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2

5
gas/testsuite/gas/bpf/atomic-be.d
View File

@ -1,7 +1,6 @@
#as: --EB
#as: -EB -mdialect=normal
#source: atomic.s
#source: atomic-pseudoc.s
#objdump: -dr
#objdump: -dr -M hex,v1
#name: eBPF atomic instructions, big endian
.*: +file format .*bpf.*

15
gas/testsuite/gas/bpf/atomic-pseudoc.d
View File

@ -1,5 +1,12 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: atomic-pseudoc.s
#dump: atomic.dump
#name: eBPF atomic instructions, normal syntax
#name: eBPF atomic instructions, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 21 ef 1e 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2
8: c3 21 ef 1e 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2

4
gas/testsuite/gas/bpf/atomic-pseudoc.s
View File

@ -1,4 +1,4 @@
# Test for eBPF ADDW and ADDDW pseudo-C instructions
.text
lock *(u64 *)(r1 + 7919) += r2
lock *(u32 *)(r1 + 7919) += r2
*(u64 *)(r1 + 7919) += r2
*(u32 *)(r1 + 7919) += r2

13
gas/testsuite/gas/bpf/atomic.d
View File

@ -1,5 +1,12 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#source: atomic.s
#dump: atomic.dump
#name: eBPF atomic instructions, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 21 ef 1e 00 00 00 00 aadd \[%r1\+0x1eef\],%r2
8: c3 21 ef 1e 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2

7
gas/testsuite/gas/bpf/atomic.dump
View File

@ -1,7 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2

4
gas/testsuite/gas/bpf/atomic.s
View File

@ -1,5 +1,5 @@
# Test for eBPF ADDW and ADDDW instructions
.text
xadddw [%r1+0x1eef], %r2
xaddw [%r1+0x1eef], %r2
aadd [%r1+0x1eef], %r2
aadd32 [%r1+0x1eef], %r2

30
gas/testsuite/gas/bpf/bpf.exp
View File

@ -18,6 +18,10 @@
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
if {[istarget bpf*-*-*]} {
# Little-endian BPF tests
run_dump_test call
run_dump_test exit
run_dump_test data
run_dump_test lddw
run_dump_test lddw-pseudoc
run_dump_test alu
@ -30,13 +34,15 @@ if {[istarget bpf*-*-*]} {
run_dump_test jump-pseudoc
run_dump_test jump32
run_dump_test jump32-pseudoc
run_dump_test call
run_dump_test exit
run_dump_test atomic
run_dump_test atomic-pseudoc
run_dump_test data
run_dump_test pseudoc-normal
run_dump_test indcall-1
run_dump_test indcall-1-pseudoc
# Big-endian BPF tests
run_dump_test call-be
run_dump_test exit-be
run_dump_test data-be
run_dump_test lddw-be
run_dump_test lddw-be-pseudoc
run_dump_test alu-be
@ -44,17 +50,11 @@ if {[istarget bpf*-*-*]} {
run_dump_test alu32-be
run_dump_test alu32-be-pseudoc
run_dump_test mem-be
run_dump_test mem-be-pseudoc
run_dump_test jump-be
run_dump_test call-be
run_dump_test exit-be
run_dump_test jump-be-pseudoc
run_dump_test jump32-be
run_dump_test jump32-be-pseudoc
run_dump_test atomic-be
run_dump_test data-be
run_dump_test pseudoc-normal-be
run_dump_test indcall-1
run_dump_test indcall-1-pseudoc
run_list_test indcall-bad-1
run_dump_test alu-xbpf
run_dump_test alu32-xbpf
run_dump_test atomic-be-pseudoc
}

4
gas/testsuite/gas/bpf/call-be.d
View File

@ -1,6 +1,6 @@
#as: --EB
#as: -EB -mdialect=normal
#source: call.s
#objdump: -dr
#objdump: -dr -M dec
#name: eBPF CALL instruction, big endian
.*: +file format .*bpf.*

4
gas/testsuite/gas/bpf/call.d
View File

@ -1,5 +1,5 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M dec
#name: eBPF CALL instruction
.*: +file format .*bpf.*

2
gas/testsuite/gas/bpf/data-be.d
View File

@ -1,4 +1,4 @@
#as: --EB
#as: -EB -mdialect=normal
#source: data.s
#objdump: -s -j .data
#name: eBPF data directives, big endian

2
gas/testsuite/gas/bpf/data.d
View File

@ -1,4 +1,4 @@
#as: --EL
#as: -EL -mdialect=normal
#objdump: -s -j .data
#name: eBPF data directives

4
gas/testsuite/gas/bpf/exit-be.d
View File

@ -1,6 +1,6 @@
#as: --EB
#as: -EB -mdialect=normal
#source: exit.s
#objdump: -dr
#objdump: -dr -M hex
#name: eBPF EXIT instruction, big endian
.*: +file format .*bpf.*

4
gas/testsuite/gas/bpf/exit.d
View File

@ -1,5 +1,5 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#name: eBPF EXIT instruction
.*: +file format .*bpf.*

24
gas/testsuite/gas/bpf/indcall-1-pseudoc.d
View File

@ -1,5 +1,23 @@
#as: -mxbpf --EL
#objdump: -mxbpf -dr
#as: -EL -mdialect=pseudoc -misa-spec=xbpf
#objdump: -M xbpf,pseudoc,dec -dr
#source: indcall-1-pseudoc.s
#dump: indcall-1.dump
#name: BPF indirect call 1, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section \.text:
0000000000000000 <main>:
0: b7 00 00 00 01 00 00 00 r0=1
8: b7 01 00 00 01 00 00 00 r1=1
10: b7 02 00 00 02 00 00 00 r2=2
18: 18 06 00 00 38 00 00 00 r6=56 ll
20: 00 00 00 00 00 00 00 00[ ]*
18: R_BPF_64_64 .text
28: 8d 06 00 00 00 00 00 00 callx r6
30: 95 00 00 00 00 00 00 00 exit
0000000000000038 <bar>:
38: b7 00 00 00 00 00 00 00 r0=0
40: 95 00 00 00 00 00 00 00 exit
#pass

24
gas/testsuite/gas/bpf/indcall-1.d
View File

@ -1,5 +1,23 @@
#as: -mxbpf --EL
#objdump: -mxbpf -dr
#as: -EL -misa-spec=xbpf
#objdump: -dr -M xbpf,dec
#source: indcall-1.s
#dump: indcall-1.dump
#name: BPF indirect call 1, normal syntax
.*: +file format .*bpf.*
Disassembly of section \.text:
0000000000000000 <main>:
0: b7 00 00 00 01 00 00 00 mov %r0,1
8: b7 01 00 00 01 00 00 00 mov %r1,1
10: b7 02 00 00 02 00 00 00 mov %r2,2
18: 18 06 00 00 38 00 00 00 lddw %r6,56
20: 00 00 00 00 00 00 00 00[ ]*
18: R_BPF_64_64 .text
28: 8d 06 00 00 00 00 00 00 call %r6
30: 95 00 00 00 00 00 00 00 exit
0000000000000038 <bar>:
38: b7 00 00 00 00 00 00 00 mov %r0,0
40: 95 00 00 00 00 00 00 00 exit
#pass

18
gas/testsuite/gas/bpf/indcall-1.dump
View File

@ -1,18 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section \.text:
0000000000000000 <main>:
0: b7 00 00 00 01 00 00 00 mov %r0,1
8: b7 01 00 00 01 00 00 00 mov %r1,1
10: b7 02 00 00 02 00 00 00 mov %r2,2
18: 18 06 00 00 38 00 00 00 lddw %r6,0x38
20: 00 00 00 00 00 00 00 00[ ]*
18: R_BPF_64_64 .text
28: 8d 06 00 00 00 00 00 00 call %r6
30: 95 00 00 00 00 00 00 00 exit
0000000000000038 <bar>:
38: b7 00 00 00 00 00 00 00 mov %r0,0
40: 95 00 00 00 00 00 00 00 exit
#pass

5
gas/testsuite/gas/bpf/indcall-bad-1.l
View File

@ -1,5 +0,0 @@
.*: Assembler messages:
.* Error: bad expression
.* Error: illegal operand `call %r6'
.* Error: unexpected token: '%r6'
#pass

1
gas/testsuite/gas/bpf/indcall-bad-1.s
View File

@ -1 +0,0 @@
call %r6

32
gas/testsuite/gas/bpf/jump-be-pseudoc.d Normal file
View File

@ -0,0 +1,32 @@
#as: -EB -mdialect=pseudoc
#source: jump-pseudoc.s
#objdump: -dr -M dec,pseudoc
#name: eBPF JUMP instructions, big endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 00 03 00 00 00 00 goto 3
8: 0f 11 00 00 00 00 00 00 r1\+=r1
10: 15 30 00 01 00 00 00 03 if r3==3 goto 1
18: 1d 34 00 00 00 00 00 00 if r3==r4 goto 0
20: 35 30 ff fd 00 00 00 03 if r3>=3 goto -3
28: 3d 34 ff fc 00 00 00 00 if r3>=r4 goto -4
30: a5 30 00 01 00 00 00 03 if r3<3 goto 1
38: ad 34 00 00 00 00 00 00 if r3<r4 goto 0
40: b5 30 00 01 00 00 00 03 if r3<=3 goto 1
48: bd 34 00 00 00 00 00 00 if r3<=r4 goto 0
50: 45 30 00 01 00 00 00 03 if r3&3 goto 1
58: 4d 34 00 00 00 00 00 00 if r3&r4 goto 0
60: 55 30 00 01 00 00 00 03 if r3!=3 goto 1
68: 5d 34 00 00 00 00 00 00 if r3!=r4 goto 0
70: 65 30 00 01 00 00 00 03 if r3s>3 goto 1
78: 6d 34 00 00 00 00 00 00 if r3s>r4 goto 0
80: 75 30 00 01 00 00 00 03 if r3s>=3 goto 1
88: 7d 34 00 00 00 00 00 00 if r3s>=r4 goto 0
90: c5 30 00 01 00 00 00 03 if r3s<3 goto 1
98: cd 34 00 00 00 00 00 00 if r3s<r4 goto 0
a0: d5 30 00 01 00 00 00 03 if r3s<=3 goto 1
a8: dd 34 00 00 00 00 00 00 if r3s<=r4 goto 0

5
gas/testsuite/gas/bpf/jump-be.d
View File

@ -1,7 +1,6 @@
#as: --EB
#as: -EB -mdialect=normal
#source: jump.s
#source: jump-pseudoc.s
#objdump: -dr
#objdump: -dr -M dec
#name: eBPF JUMP instructions, big endian
.*: +file format .*bpf.*

33
gas/testsuite/gas/bpf/jump-pseudoc.d
View File

@ -1,5 +1,32 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M dec,pseudoc
#source: jump-pseudoc.s
#dump: jump.dump
#name: eBPF JUMP instructions, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 goto 3
8: 0f 11 00 00 00 00 00 00 r1\+=r1
10: 15 03 01 00 03 00 00 00 if r3==3 goto 1
18: 1d 43 00 00 00 00 00 00 if r3==r4 goto 0
20: 35 03 fd ff 03 00 00 00 if r3>=3 goto -3
28: 3d 43 fc ff 00 00 00 00 if r3>=r4 goto -4
30: a5 03 01 00 03 00 00 00 if r3<3 goto 1
38: ad 43 00 00 00 00 00 00 if r3<r4 goto 0
40: b5 03 01 00 03 00 00 00 if r3<=3 goto 1
48: bd 43 00 00 00 00 00 00 if r3<=r4 goto 0
50: 45 03 01 00 03 00 00 00 if r3&3 goto 1
58: 4d 43 00 00 00 00 00 00 if r3&r4 goto 0
60: 55 03 01 00 03 00 00 00 if r3!=3 goto 1
68: 5d 43 00 00 00 00 00 00 if r3!=r4 goto 0
70: 65 03 01 00 03 00 00 00 if r3s>3 goto 1
78: 6d 43 00 00 00 00 00 00 if r3s>r4 goto 0
80: 75 03 01 00 03 00 00 00 if r3s>=3 goto 1
88: 7d 43 00 00 00 00 00 00 if r3s>=r4 goto 0
90: c5 03 01 00 03 00 00 00 if r3s<3 goto 1
98: cd 43 00 00 00 00 00 00 if r3s<r4 goto 0
a0: d5 03 01 00 03 00 00 00 if r3s<=3 goto 1
a8: dd 43 00 00 00 00 00 00 if r3s<=r4 goto 0

33
gas/testsuite/gas/bpf/jump.d
View File

@ -1,5 +1,32 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M dec
#source: jump.s
#dump: jump.dump
#name: eBPF JUMP instructions, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
40: b5 03 01 00 03 00 00 00 jle %r3,3,1
48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
50: 45 03 01 00 03 00 00 00 jset %r3,3,1
58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
60: 55 03 01 00 03 00 00 00 jne %r3,3,1
68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0

27
gas/testsuite/gas/bpf/jump.dump
View File

@ -1,27 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
40: b5 03 01 00 03 00 00 00 jle %r3,3,1
48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
50: 45 03 01 00 03 00 00 00 jset %r3,3,1
58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
60: 55 03 01 00 03 00 00 00 jne %r3,3,1
68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0

32
gas/testsuite/gas/bpf/jump32-be-pseudoc.d Normal file
View File

@ -0,0 +1,32 @@
#as: -EB -mdialect=pseudoc
#objdump: -dr -M dec,pseudoc
#source: jump32-pseudoc.s
#name: eBPF JUMP32 instructions, pseudoc syntax, big-endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 00 03 00 00 00 00 goto 3
8: 0f 11 00 00 00 00 00 00 r1\+=r1
10: 16 30 00 01 00 00 00 03 if w3==3 goto 1
18: 1e 34 00 00 00 00 00 00 if w3==w4 goto 0
20: 36 30 ff fd 00 00 00 03 if w3>=3 goto -3
28: 3e 34 ff fc 00 00 00 00 if w3>=w4 goto -4
30: a6 30 00 01 00 00 00 03 if w3<3 goto 1
38: ae 34 00 00 00 00 00 00 if w3<w4 goto 0
40: b6 30 00 01 00 00 00 03 if w3<=3 goto 1
48: be 34 00 00 00 00 00 00 if w3<=w4 goto 0
50: 46 30 00 01 00 00 00 03 if w3&3 goto 1
58: 4e 34 00 00 00 00 00 00 if w3&w4 goto 0
60: 56 30 00 01 00 00 00 03 if w3!=3 goto 1
68: 5e 34 00 00 00 00 00 00 if w3!=w4 goto 0
70: 66 30 00 01 00 00 00 03 if w3s>3 goto 1
78: 6e 34 00 00 00 00 00 00 if w3s>w4 goto 0
80: 76 30 00 01 00 00 00 03 if w3s>=3 goto 1
88: 7e 34 00 00 00 00 00 00 if w3s>=w4 goto 0
90: c6 30 00 01 00 00 00 03 if w3s<3 goto 1
98: ce 34 00 00 00 00 00 00 if w3s<w4 goto 0
a0: d6 30 00 01 00 00 00 03 if w3s<=3 goto 1
a8: de 34 00 00 00 00 00 00 if w3s<=w4 goto 0

32
gas/testsuite/gas/bpf/jump32-be.d Normal file
View File

@ -0,0 +1,32 @@
#as: -EB -mdialect=normal
#objdump: -dr -M dec
#source: jump32.s
#name: eBPF JUMP32 instructions, normal syntax, big-endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 00 03 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 16 30 00 01 00 00 00 03 jeq32 %r3,3,1
18: 1e 34 00 00 00 00 00 00 jeq32 %r3,%r4,0
20: 36 30 ff fd 00 00 00 03 jge32 %r3,3,-3
28: 3e 34 ff fc 00 00 00 00 jge32 %r3,%r4,-4
30: a6 30 00 01 00 00 00 03 jlt32 %r3,3,1
38: ae 34 00 00 00 00 00 00 jlt32 %r3,%r4,0
40: b6 30 00 01 00 00 00 03 jle32 %r3,3,1
48: be 34 00 00 00 00 00 00 jle32 %r3,%r4,0
50: 46 30 00 01 00 00 00 03 jset32 %r3,3,1
58: 4e 34 00 00 00 00 00 00 jset32 %r3,%r4,0
60: 56 30 00 01 00 00 00 03 jne32 %r3,3,1
68: 5e 34 00 00 00 00 00 00 jne32 %r3,%r4,0
70: 66 30 00 01 00 00 00 03 jsgt32 %r3,3,1
78: 6e 34 00 00 00 00 00 00 jsgt32 %r3,%r4,0
80: 76 30 00 01 00 00 00 03 jsge32 %r3,3,1
88: 7e 34 00 00 00 00 00 00 jsge32 %r3,%r4,0
90: c6 30 00 01 00 00 00 03 jslt32 %r3,3,1
98: ce 34 00 00 00 00 00 00 jslt32 %r3,%r4,0
a0: d6 30 00 01 00 00 00 03 jsle32 %r3,3,1
a8: de 34 00 00 00 00 00 00 jsle32 %r3,%r4,0

33
gas/testsuite/gas/bpf/jump32-pseudoc.d
View File

@ -1,5 +1,32 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M dec,pseudoc
#source: jump32-pseudoc.s
#dump: jump32.dump
#name: eBPF JUMP32 instructions, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 goto 3
8: 0f 11 00 00 00 00 00 00 r1\+=r1
10: 16 03 01 00 03 00 00 00 if w3==3 goto 1
18: 1e 43 00 00 00 00 00 00 if w3==w4 goto 0
20: 36 03 fd ff 03 00 00 00 if w3>=3 goto -3
28: 3e 43 fc ff 00 00 00 00 if w3>=w4 goto -4
30: a6 03 01 00 03 00 00 00 if w3<3 goto 1
38: ae 43 00 00 00 00 00 00 if w3<w4 goto 0
40: b6 03 01 00 03 00 00 00 if w3<=3 goto 1
48: be 43 00 00 00 00 00 00 if w3<=w4 goto 0
50: 46 03 01 00 03 00 00 00 if w3&3 goto 1
58: 4e 43 00 00 00 00 00 00 if w3&w4 goto 0
60: 56 03 01 00 03 00 00 00 if w3!=3 goto 1
68: 5e 43 00 00 00 00 00 00 if w3!=w4 goto 0
70: 66 03 01 00 03 00 00 00 if w3s>3 goto 1
78: 6e 43 00 00 00 00 00 00 if w3s>w4 goto 0
80: 76 03 01 00 03 00 00 00 if w3s>=3 goto 1
88: 7e 43 00 00 00 00 00 00 if w3s>=w4 goto 0
90: c6 03 01 00 03 00 00 00 if w3s<3 goto 1
98: ce 43 00 00 00 00 00 00 if w3s<w4 goto 0
a0: d6 03 01 00 03 00 00 00 if w3s<=3 goto 1
a8: de 43 00 00 00 00 00 00 if w3s<=w4 goto 0

33
gas/testsuite/gas/bpf/jump32.d
View File

@ -1,5 +1,32 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M dec
#source: jump32.s
#dump: jump32.dump
#name: eBPF JUMP32 instructions, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0

27
gas/testsuite/gas/bpf/jump32.dump
View File

@ -1,27 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 05 00 03 00 00 00 00 00 ja 3
8: 0f 11 00 00 00 00 00 00 add %r1,%r1
10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1
18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0
20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3
28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4
30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1
38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0
40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1
48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0
50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1
58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0
60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1
68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0
70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1
78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0
80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1
88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0
90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1
98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0
a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1
a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0

19
gas/testsuite/gas/bpf/lddw-be-pseudoc.d
View File

@ -1,5 +1,18 @@
#as: --EB
#as: -EB -mdialect=pseudoc
#source: lddw-pseudoc.s
#objdump: -dr
#dump: lddw-be.dump
#objdump: -dr -M hex,pseudoc
#name: eBPF LDDW, big-endian, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 30 00 00 00 00 00 01 r3=0x1 ll
8: 00 00 00 00 00 00 00 00
10: 18 40 00 00 de ad be ef r4=0xdeadbeef ll
18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 r5=0x1122334455667788 ll
28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe r6=0xfffffffffffffffe ll
38: 00 00 00 00 ff ff ff ff

19
gas/testsuite/gas/bpf/lddw-be.d
View File

@ -1,5 +1,18 @@
#as: --EB
#as: -EB -mdialect=normal
#source: lddw.s
#objdump: -dr
#dump: lddw-be.dump
#objdump: -dr -M hex
#name: eBPF LDDW, big-endian, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 30 00 00 00 00 00 01 lddw %r3,0x1
8: 00 00 00 00 00 00 00 00
10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe lddw %r6,0xfffffffffffffffe
38: 00 00 00 00 ff ff ff ff

13
gas/testsuite/gas/bpf/lddw-be.dump
View File

@ -1,13 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 30 00 00 00 00 00 01 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
28: 00 00 00 00 11 22 33 44
30: 18 60 00 00 ff ff ff fe lddw %r6,-2
38: 00 00 00 00 ff ff ff ff

19
gas/testsuite/gas/bpf/lddw-pseudoc.d
View File

@ -1,5 +1,18 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: lddw-pseudoc.s
#dump: lddw.dump
#name: eBPF LDDW, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 03 00 00 01 00 00 00 r3=0x1 ll
8: 00 00 00 00 00 00 00 00
10: 18 04 00 00 ef be ad de r4=0xdeadbeef ll
18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 r5=0x1122334455667788 ll
28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff r6=0xfffffffffffffffe ll
38: 00 00 00 00 ff ff ff ff

19
gas/testsuite/gas/bpf/lddw.d
View File

@ -1,5 +1,18 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#source: lddw.s
#dump: lddw.dump
#name: eBPF LDDW, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 03 00 00 01 00 00 00 lddw %r3,0x1
8: 00 00 00 00 00 00 00 00
10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff lddw %r6,0xfffffffffffffffe
38: 00 00 00 00 ff ff ff ff

13
gas/testsuite/gas/bpf/lddw.dump
View File

@ -1,13 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 18 03 00 00 01 00 00 00 lddw %r3,1
8: 00 00 00 00 00 00 00 00
10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
18: 00 00 00 00 00 00 00 00
20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
28: 00 00 00 00 44 33 22 11
30: 18 06 00 00 fe ff ff ff lddw %r6,-2
38: 00 00 00 00 ff ff ff ff

30
gas/testsuite/gas/bpf/mem-be-pseudoc.d Normal file
View File

@ -0,0 +1,30 @@
#as: -EB -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: mem-pseudoc.s
#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax, big-endian
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 00 00 be ef r0=\*\(u32\*\)skb\[0xbeef\]
8: 28 00 00 00 00 00 be ef r0=\*\(u16\*\)skb\[0xbeef\]
10: 30 00 00 00 00 00 be ef r0=\*\(u8\*\)skb\[0xbeef\]
18: 38 00 00 00 00 00 be ef r0=\*\(u64\*\)skb\[0xbeef\]
20: 40 03 00 00 00 00 be ef r0=\*\(u32\*\)skb\[r3\+0xbeef\]
28: 48 05 00 00 00 00 be ef r0=\*\(u16\*\)skb\[r5\+0xbeef\]
30: 50 07 00 00 00 00 be ef r0=\*\(u8\*\)skb\[r7\+0xbeef\]
38: 58 09 00 00 00 00 be ef r0=\*\(u64\*\)skb\[r9\+0xbeef\]
40: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
48: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
50: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
58: 79 21 ff fe 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\)
60: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
68: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
70: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
78: 7b 12 ff fe 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2
80: 72 10 7e ef 11 22 33 44 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344
88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344

11
gas/testsuite/gas/bpf/mem-be.d
View File

@ -1,7 +1,6 @@
#as: --EB
#as: -EB -mdialect=normal
#source: mem.s
#source: mem-pseudoc.s
#objdump: -dr
#objdump: -dr -M hex
#name: eBPF MEM instructions, modulus lddw, big endian
.*: +file format .*bpf.*
@ -20,12 +19,12 @@ Disassembly of section .text:
40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\]
60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2
78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2
80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344
88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344
90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344
98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344
98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344

31
gas/testsuite/gas/bpf/mem-pseudoc.d
View File

@ -1,5 +1,30 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=pseudoc
#objdump: -dr -M hex,pseudoc
#source: mem-pseudoc.s
#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[0xbeef\]
8: 28 00 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[0xbeef\]
10: 30 00 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[0xbeef\]
18: 38 00 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[0xbeef\]
20: 40 30 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[r3\+0xbeef\]
28: 48 50 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[r5\+0xbeef\]
30: 50 70 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[r7\+0xbeef\]
38: 58 90 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[r9\+0xbeef\]
40: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\)
48: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\)
50: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\)
58: 79 12 fe ff 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\)
60: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2
68: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2
70: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2
78: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2
80: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344
88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344
90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344
98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344

8
gas/testsuite/gas/bpf/mem-pseudoc.s
View File

@ -17,7 +17,7 @@
*(u16 *)(r1 + 32495) = r2
*(u8 *)(r1 + 32495) = r2
*(u64 *)(r1 - 2) = r2
stb [%r1+0x7eef], 0x11223344
sth [%r1+0x7eef], 0x11223344
stw [%r1+0x7eef], 0x11223344
stdw [%r1+-2], 0x11223344
*(u8 *)(r1 + 0x7eef) = 0x11223344
*(u16 *)(r1 + 0x7eef) = 0x11223344
*(u32 *)(r1 + 0x7eef) = 0x11223344
*(u64 *)(r1 + -2) = 0x11223344

31
gas/testsuite/gas/bpf/mem.d
View File

@ -1,5 +1,30 @@
#as: --EL
#objdump: -dr
#as: -EL -mdialect=normal
#objdump: -dr -M hex
#source: mem.s
#dump: mem.dump
#name: eBPF MEM instructions, modulus lddw, normal syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\]
60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2
80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344

25
gas/testsuite/gas/bpf/mem.dump
View File

@ -1,25 +0,0 @@
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef
40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344

2
gas/testsuite/gas/bpf/mem.s
View File

@ -21,4 +21,4 @@
stb [%r1+0x7eef], 0x11223344
sth [%r1+0x7eef], 0x11223344
stw [%r1+0x7eef], 0x11223344
stdw [%r1+-2], 0x11223344
stdw [%r1-2], 0x11223344

214
gas/testsuite/gas/bpf/pseudoc-normal-be.d
View File

@ -1,214 +0,0 @@
#as: --EB
#objdump: -dr
#source: pseudoc-normal.s
#name: eBPF clang (pseudo-C)/gas (normal) instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <beg>:
0: 07 10 00 00 00 00 00 aa add %r1,0xaa
8: 07 10 00 00 00 00 00 aa add %r1,0xaa
10: 0f 12 00 00 00 00 00 00 add %r1,%r2
18: 0f 12 00 00 00 00 00 00 add %r1,%r2
20: 17 10 00 00 00 00 00 aa sub %r1,0xaa
28: 17 10 00 00 00 00 00 aa sub %r1,0xaa
30: 1f 12 00 00 00 00 00 00 sub %r1,%r2
38: 1f 12 00 00 00 00 00 00 sub %r1,%r2
40: 27 10 00 00 00 00 00 aa mul %r1,0xaa
48: 27 10 00 00 00 00 00 aa mul %r1,0xaa
50: 2f 12 00 00 00 00 00 00 mul %r1,%r2
58: 2f 12 00 00 00 00 00 00 mul %r1,%r2
60: 37 10 00 00 00 00 00 aa div %r1,0xaa
68: 37 10 00 00 00 00 00 aa div %r1,0xaa
70: 3f 12 00 00 00 00 00 00 div %r1,%r2
78: 3f 12 00 00 00 00 00 00 div %r1,%r2
80: 47 10 00 00 00 00 00 aa or %r1,0xaa
88: 47 10 00 00 00 00 00 aa or %r1,0xaa
90: 4f 12 00 00 00 00 00 00 or %r1,%r2
98: 4f 12 00 00 00 00 00 00 or %r1,%r2
a0: 57 10 00 00 00 00 00 aa and %r1,0xaa
a8: 57 10 00 00 00 00 00 aa and %r1,0xaa
b0: 5f 12 00 00 00 00 00 00 and %r1,%r2
b8: 5f 12 00 00 00 00 00 00 and %r1,%r2
c0: 67 10 00 00 00 00 00 aa lsh %r1,0xaa
c8: 67 10 00 00 00 00 00 aa lsh %r1,0xaa
d0: 6f 12 00 00 00 00 00 00 lsh %r1,%r2
d8: 6f 12 00 00 00 00 00 00 lsh %r1,%r2
e0: 77 10 00 00 00 00 00 aa rsh %r1,0xaa
e8: 77 10 00 00 00 00 00 aa rsh %r1,0xaa
f0: 7f 12 00 00 00 00 00 00 rsh %r1,%r2
f8: 7f 12 00 00 00 00 00 00 rsh %r1,%r2
100: a7 10 00 00 00 00 00 aa xor %r1,0xaa
108: a7 10 00 00 00 00 00 aa xor %r1,0xaa
110: af 12 00 00 00 00 00 00 xor %r1,%r2
118: af 12 00 00 00 00 00 00 xor %r1,%r2
120: b7 10 00 00 00 00 00 aa mov %r1,0xaa
128: b7 10 00 00 00 00 00 aa mov %r1,0xaa
130: bf 12 00 00 00 00 00 00 mov %r1,%r2
138: bf 12 00 00 00 00 00 00 mov %r1,%r2
140: c7 10 00 00 00 00 00 aa arsh %r1,0xaa
148: c7 10 00 00 00 00 00 aa arsh %r1,0xaa
150: cf 12 00 00 00 00 00 00 arsh %r1,%r2
158: cf 12 00 00 00 00 00 00 arsh %r1,%r2
160: 87 10 00 00 00 00 00 00 neg %r1
168: 87 10 00 00 00 00 00 00 neg %r1
170: 04 10 00 00 00 00 00 aa add32 %r1,0xaa
178: 04 10 00 00 00 00 00 aa add32 %r1,0xaa
180: 0c 12 00 00 00 00 00 00 add32 %r1,%r2
188: 0c 12 00 00 00 00 00 00 add32 %r1,%r2
190: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa
198: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa
1a0: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2
1a8: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2
1b0: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa
1b8: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa
1c0: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2
1c8: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2
1d0: 34 10 00 00 00 00 00 aa div32 %r1,0xaa
1d8: 34 10 00 00 00 00 00 aa div32 %r1,0xaa
1e0: 3c 12 00 00 00 00 00 00 div32 %r1,%r2
1e8: 3c 12 00 00 00 00 00 00 div32 %r1,%r2
1f0: 44 10 00 00 00 00 00 aa or32 %r1,0xaa
1f8: 44 10 00 00 00 00 00 aa or32 %r1,0xaa
200: 4c 12 00 00 00 00 00 00 or32 %r1,%r2
208: 4c 12 00 00 00 00 00 00 or32 %r1,%r2
210: 54 10 00 00 00 00 00 aa and32 %r1,0xaa
218: 54 10 00 00 00 00 00 aa and32 %r1,0xaa
220: 5c 12 00 00 00 00 00 00 and32 %r1,%r2
228: 5c 12 00 00 00 00 00 00 and32 %r1,%r2
230: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa
238: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa
240: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2
248: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2
250: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa
258: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa
260: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2
268: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2
270: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa
278: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa
280: ac 12 00 00 00 00 00 00 xor32 %r1,%r2
288: ac 12 00 00 00 00 00 00 xor32 %r1,%r2
290: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa
298: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa
2a0: bc 12 00 00 00 00 00 00 mov32 %r1,%r2
2a8: bc 12 00 00 00 00 00 00 mov32 %r1,%r2
2b0: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa
2b8: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa
2c0: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2
2c8: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2
2d0: 84 10 00 00 00 00 00 00 neg32 %r1
2d8: 84 10 00 00 00 00 00 00 neg32 %r1
2e0: d4 10 00 00 00 00 00 10 endle %r1,16
2e8: d4 10 00 00 00 00 00 10 endle %r1,16
2f0: d4 10 00 00 00 00 00 20 endle %r1,32
2f8: d4 10 00 00 00 00 00 20 endle %r1,32
300: d4 10 00 00 00 00 00 40 endle %r1,64
308: d4 10 00 00 00 00 00 40 endle %r1,64
310: dc 10 00 00 00 00 00 10 endbe %r1,16
318: dc 10 00 00 00 00 00 10 endbe %r1,16
320: dc 10 00 00 00 00 00 20 endbe %r1,32
328: dc 10 00 00 00 00 00 20 endbe %r1,32
330: dc 10 00 00 00 00 00 40 endbe %r1,64
338: dc 10 00 00 00 00 00 40 endbe %r1,64
340: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
348: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
350: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
358: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
360: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
368: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
370: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
378: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
380: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2
388: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2
390: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2
398: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2
3a0: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2
3a8: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2
3b0: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
3b8: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
3c0: 05 00 00 bb 00 00 00 00 ja 187
3c8: 05 00 00 bb 00 00 00 00 ja 187
3d0: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187
3d8: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187
3e0: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187
3e8: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187
3f0: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187
3f8: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187
400: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187
408: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187
410: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187
418: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187
420: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187
428: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187
430: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187
438: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187
440: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187
448: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187
450: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187
458: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187
460: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187
468: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187
470: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187
478: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187
480: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187
488: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187
490: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187
498: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187
4a0: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187
4a8: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187
4b0: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187
4b8: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187
4c0: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187
4c8: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187
4d0: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187
4d8: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187
4e0: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187
4e8: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187
4f0: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187
4f8: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187
500: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187
508: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187
510: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187
518: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187
520: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187
528: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187
530: 85 00 00 00 00 00 00 aa call 170
538: 85 00 00 00 00 00 00 aa call 170
540: 95 00 00 00 00 00 00 00 exit
548: 95 00 00 00 00 00 00 00 exit
550: b7 60 00 00 00 00 06 20 mov %r6,0x620
558: 95 00 00 00 00 00 00 00 exit
560: 20 00 00 00 00 00 00 aa ldabsw 0xaa
568: 20 00 00 00 00 00 00 aa ldabsw 0xaa
570: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
578: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
580: 20 00 00 00 00 00 00 aa ldabsw 0xaa
588: 20 00 00 00 00 00 00 aa ldabsw 0xaa
590: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
598: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa
5a0: 18 30 00 00 00 00 00 01 lddw %r3,1
5a8: 00 00 00 00 00 00 00 00
5b0: 18 30 00 00 00 00 00 01 lddw %r3,1
5b8: 00 00 00 00 00 00 00 00
5c0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416
5c8: 00 00 00 00 aa bb cc dd
5d0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416
5d8: 00 00 00 00 aa bb cc dd
5e0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
5e8: 00 00 00 00 11 22 33 44
5f0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
5f8: 00 00 00 00 11 22 33 44
600: 18 60 00 00 00 00 06 20 lddw %r6,0x620
608: 00 00 00 00 00 00 00 00
600: R_BPF_64_64 .text
610: 18 60 00 00 00 00 06 20 lddw %r6,0x620
618: 00 00 00 00 00 00 00 00
610: R_BPF_64_64 .text
0000000000000620 <main>:
620: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
628: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
630: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
638: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2

214
gas/testsuite/gas/bpf/pseudoc-normal.d
View File

@ -1,214 +0,0 @@
#as: --EL
#objdump: -dr
#source: pseudoc-normal.s
#name: eBPF clang (pseudo-C)/gas (normal) instructions
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <beg>:
0: 07 01 00 00 aa 00 00 00 add %r1,0xaa
8: 07 01 00 00 aa 00 00 00 add %r1,0xaa
10: 0f 21 00 00 00 00 00 00 add %r1,%r2
18: 0f 21 00 00 00 00 00 00 add %r1,%r2
20: 17 01 00 00 aa 00 00 00 sub %r1,0xaa
28: 17 01 00 00 aa 00 00 00 sub %r1,0xaa
30: 1f 21 00 00 00 00 00 00 sub %r1,%r2
38: 1f 21 00 00 00 00 00 00 sub %r1,%r2
40: 27 01 00 00 aa 00 00 00 mul %r1,0xaa
48: 27 01 00 00 aa 00 00 00 mul %r1,0xaa
50: 2f 21 00 00 00 00 00 00 mul %r1,%r2
58: 2f 21 00 00 00 00 00 00 mul %r1,%r2
60: 37 01 00 00 aa 00 00 00 div %r1,0xaa
68: 37 01 00 00 aa 00 00 00 div %r1,0xaa
70: 3f 21 00 00 00 00 00 00 div %r1,%r2
78: 3f 21 00 00 00 00 00 00 div %r1,%r2
80: 47 01 00 00 aa 00 00 00 or %r1,0xaa
88: 47 01 00 00 aa 00 00 00 or %r1,0xaa
90: 4f 21 00 00 00 00 00 00 or %r1,%r2
98: 4f 21 00 00 00 00 00 00 or %r1,%r2
a0: 57 01 00 00 aa 00 00 00 and %r1,0xaa
a8: 57 01 00 00 aa 00 00 00 and %r1,0xaa
b0: 5f 21 00 00 00 00 00 00 and %r1,%r2
b8: 5f 21 00 00 00 00 00 00 and %r1,%r2
c0: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa
c8: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa
d0: 6f 21 00 00 00 00 00 00 lsh %r1,%r2
d8: 6f 21 00 00 00 00 00 00 lsh %r1,%r2
e0: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa
e8: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa
f0: 7f 21 00 00 00 00 00 00 rsh %r1,%r2
f8: 7f 21 00 00 00 00 00 00 rsh %r1,%r2
100: a7 01 00 00 aa 00 00 00 xor %r1,0xaa
108: a7 01 00 00 aa 00 00 00 xor %r1,0xaa
110: af 21 00 00 00 00 00 00 xor %r1,%r2
118: af 21 00 00 00 00 00 00 xor %r1,%r2
120: b7 01 00 00 aa 00 00 00 mov %r1,0xaa
128: b7 01 00 00 aa 00 00 00 mov %r1,0xaa
130: bf 21 00 00 00 00 00 00 mov %r1,%r2
138: bf 21 00 00 00 00 00 00 mov %r1,%r2
140: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa
148: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa
150: cf 21 00 00 00 00 00 00 arsh %r1,%r2
158: cf 21 00 00 00 00 00 00 arsh %r1,%r2
160: 87 01 00 00 00 00 00 00 neg %r1
168: 87 01 00 00 00 00 00 00 neg %r1
170: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa
178: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa
180: 0c 21 00 00 00 00 00 00 add32 %r1,%r2
188: 0c 21 00 00 00 00 00 00 add32 %r1,%r2
190: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa
198: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa
1a0: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2
1a8: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2
1b0: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa
1b8: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa
1c0: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2
1c8: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2
1d0: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa
1d8: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa
1e0: 3c 21 00 00 00 00 00 00 div32 %r1,%r2
1e8: 3c 21 00 00 00 00 00 00 div32 %r1,%r2
1f0: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa
1f8: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa
200: 4c 21 00 00 00 00 00 00 or32 %r1,%r2
208: 4c 21 00 00 00 00 00 00 or32 %r1,%r2
210: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa
218: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa
220: 5c 21 00 00 00 00 00 00 and32 %r1,%r2
228: 5c 21 00 00 00 00 00 00 and32 %r1,%r2
230: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa
238: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa
240: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2
248: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2
250: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa
258: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa
260: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2
268: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2
270: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa
278: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa
280: ac 21 00 00 00 00 00 00 xor32 %r1,%r2
288: ac 21 00 00 00 00 00 00 xor32 %r1,%r2
290: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa
298: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa
2a0: bc 21 00 00 00 00 00 00 mov32 %r1,%r2
2a8: bc 21 00 00 00 00 00 00 mov32 %r1,%r2
2b0: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa
2b8: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa
2c0: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2
2c8: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2
2d0: 84 01 00 00 00 00 00 00 neg32 %r1
2d8: 84 01 00 00 00 00 00 00 neg32 %r1
2e0: d4 01 00 00 10 00 00 00 endle %r1,16
2e8: d4 01 00 00 10 00 00 00 endle %r1,16
2f0: d4 01 00 00 20 00 00 00 endle %r1,32
2f8: d4 01 00 00 20 00 00 00 endle %r1,32
300: d4 01 00 00 40 00 00 00 endle %r1,64
308: d4 01 00 00 40 00 00 00 endle %r1,64
310: dc 01 00 00 10 00 00 00 endbe %r1,16
318: dc 01 00 00 10 00 00 00 endbe %r1,16
320: dc 01 00 00 20 00 00 00 endbe %r1,32
328: dc 01 00 00 20 00 00 00 endbe %r1,32
330: dc 01 00 00 40 00 00 00 endbe %r1,64
338: dc 01 00 00 40 00 00 00 endbe %r1,64
340: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
348: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\]
350: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
358: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\]
360: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
368: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\]
370: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
378: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\]
380: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2
388: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2
390: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2
398: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2
3a0: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2
3a8: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2
3b0: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
3b8: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2
3c0: 05 00 bb 00 00 00 00 00 ja 187
3c8: 05 00 bb 00 00 00 00 00 ja 187
3d0: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187
3d8: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187
3e0: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187
3e8: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187
3f0: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187
3f8: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187
400: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187
408: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187
410: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187
418: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187
420: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187
428: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187
430: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187
438: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187
440: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187
448: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187
450: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187
458: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187
460: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187
468: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187
470: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187
478: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187
480: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187
488: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187
490: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187
498: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187
4a0: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187
4a8: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187
4b0: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187
4b8: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187
4c0: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187
4c8: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187
4d0: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187
4d8: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187
4e0: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187
4e8: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187
4f0: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187
4f8: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187
500: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187
508: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187
510: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187
518: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187
520: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187
528: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187
530: 85 00 00 00 aa 00 00 00 call 170
538: 85 00 00 00 aa 00 00 00 call 170
540: 95 00 00 00 00 00 00 00 exit
548: 95 00 00 00 00 00 00 00 exit
550: b7 06 00 00 20 06 00 00 mov %r6,0x620
558: 95 00 00 00 00 00 00 00 exit
560: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
568: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
570: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
578: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
580: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
588: 20 00 00 00 aa 00 00 00 ldabsw 0xaa
590: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
598: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa
5a0: 18 03 00 00 01 00 00 00 lddw %r3,1
5a8: 00 00 00 00 00 00 00 00
5b0: 18 03 00 00 01 00 00 00 lddw %r3,1
5b8: 00 00 00 00 00 00 00 00
5c0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416
5c8: 00 00 00 00 dd cc bb aa
5d0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416
5d8: 00 00 00 00 dd cc bb aa
5e0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
5e8: 00 00 00 00 44 33 22 11
5f0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
5f8: 00 00 00 00 44 33 22 11
600: 18 06 00 00 20 06 00 00 lddw %r6,0x620
608: 00 00 00 00 00 00 00 00
600: R_BPF_64_64 .text
610: 18 06 00 00 20 06 00 00 lddw %r6,0x620
618: 00 00 00 00 00 00 00 00
610: R_BPF_64_64 .text
0000000000000620 <main>:
620: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
628: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2
630: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2
638: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2

196
gas/testsuite/gas/bpf/pseudoc-normal.s
View File

@ -1,196 +0,0 @@
# Tests for mixing pseudo-C and normal eBPF instructions
beg:
.text
add %r1,0xaa
r1 += 0xaa
add %r1,%r2
r1 += r2
sub %r1,0xaa
r1 -= 0xaa
sub %r1,%r2
r1 -= r2
mul %r1,0xaa
r1 *= 0xaa
mul %r1,%r2
r1 *= r2
div %r1,0xaa
r1 /= 0xaa
div %r1,%r2
r1 /= r2
or %r1,0xaa
r1 |= 0xaa
or %r1,%r2
r1 |= r2
and %r1,0xaa
r1 &= 0xaa
and %r1,%r2
r1 &= r2
lsh %r1,0xaa
r1 <<= 0xaa
lsh %r1,%r2
r1 <<= r2
rsh %r1,0xaa
r1 >>= 0xaa
rsh %r1,%r2
r1 >>= r2
xor %r1,0xaa
r1 ^= 0xaa
xor %r1,%r2
r1 ^= r2
mov %r1,0xaa
r1 = 0xaa
mov %r1,%r2
r1 = r2
arsh %r1,0xaa
r1 s>>= 0xaa
arsh %r1,%r2
r1 s>>= r2
neg %r1
r1 = -r1
add32 %r1,0xaa
w1 += 0xaa
add32 %r1,%r2
w1 += w2
sub32 %r1,0xaa
w1 -= 0xaa
sub32 %r1,%r2
w1 -= w2
mul32 %r1,0xaa
w1 *= 0xaa
mul32 %r1,%r2
w1 *= w2
div32 %r1,0xaa
w1 /= 0xaa
div32 %r1,%r2
w1 /= w2
or32 %r1,0xaa
w1 |= 0xaa
or32 %r1,%r2
w1 |= w2
and32 %r1,0xaa
w1 &= 0xaa
and32 %r1,%r2
w1 &= w2
lsh32 %r1,0xaa
w1 <<= 0xaa
lsh32 %r1,%r2
w1 <<= w2
rsh32 %r1,0xaa
w1 >>= 0xaa
rsh32 %r1,%r2
w1 >>= w2
xor32 %r1,0xaa
w1 ^= 0xaa
xor32 %r1,%r2
w1 ^= w2
mov32 %r1,0xaa
w1 = 0xaa
mov32 %r1,%r2
w1 = w2
arsh32 %r1,0xaa
w1 s>>= 0xaa
arsh32 %r1,%r2
w1 s>>= w2
neg32 %r1
w1 = -w1
endle %r1,16
r1 = le16 r1
endle %r1,32
r1 = le32 r1
endle %r1,64
r1 = le64 r1
endbe %r1,16
r1 = be16 r1
endbe %r1,32
r1 = be32 r1
endbe %r1,64
r1 = be64 r1
ldxb %r1,[%r2+0xaa]
r1 = *(u8 *)(r2 + 0xaa)
ldxh %r1,[%r2+0xaa]
r1 = *(u16 *)(r2 + 0xaa)
ldxw %r1,[%r2+0xaa]
r1 = *(u32 *)(r2 + 0xaa)
ldxdw %r1,[%r2+0xaa]
r1 = *(u64 *)(r2 + 0xaa)
stxb [%r1+0xaa],%r2
*(u8 *)(r1 + 0xaa) = r2
stxh [%r1+0xaa],%r2
*(u16 *)(r1 + 0xaa) = r2
stxw [%r1+0xaa],%r2
*(u32 *)(r1 + 0xaa) = r2
stxdw [%r1+0xaa],%r2
*(u64 *)(r1 + 0xaa) = r2
ja 187
goto 0xbb
jeq %r1,0xaa,187
if r1 == 0xaa goto 0xbb
jeq %r1,%r2,187
if r1 == r2 goto 0xbb
jgt %r1,0xaa,187
if r1 > 0xaa goto 0xbb
jgt %r1,%r2,187
if r1 > r2 goto 0xbb
jge %r1,0xaa,187
if r1 >= 0xaa goto 0xbb
jge %r1,%r2,187
if r1 >= r2 goto 0xbb
jlt %r1,0xaa,187
if r1 < 0xaa goto 0xbb
jlt %r1,%r2,187
if r1 < r2 goto 0xbb
jle %r1,0xaa,187
if r1 <= 0xaa goto 0xbb
jle %r1,%r2,187
if r1 <= r2 goto 0xbb
jset %r1,0xaa,187
if r1 & 0xaa goto 0xbb
jset %r1,%r2,187
if r1 & r2 goto 0xbb
jne %r1,0xaa,187
if r1 != 0xaa goto 0xbb
jne %r1,%r2,187
if r1 != r2 goto 0xbb
jsgt %r1,0xaa,187
if r1 s> 0xaa goto 0xbb
jsgt %r1,%r2,187
if r1 s> r2 goto 0xbb
jsge %r1,0xaa,187
if r1 s>= 0xaa goto 0xbb
jsge %r1,%r2,187
if r1 s>= r2 goto 0xbb
jslt %r1,0xaa,187
if r1 s< 0xaa goto 0xbb
jslt %r1,%r2,187
if r1 s< r2 goto 0xbb
jsle %r1,0xaa,187
if r1 s<= 0xaa goto 0xbb
jsle %r1,%r2,187
if r1 s<= r2 goto 0xbb
call 170
call 0xaa
exit
exit
mov %r6,main - beg
exit
ldabsw 0xaa
r0 = *(u32 *)skb[0xaa]
ldindb %r7,0xaa
r0 = *(u8 *)skb[r7 + 0xaa]
ldabsw 0xaa
r0 = *(u32 *)skb[0xaa]
ldindb %r7,0xaa
r0 = *(u8 *)skb[r7 + 0xaa]
lddw %r3,1
r3 = 1 ll
lddw %r4,0xaabbccddeeff7788
r4 = 0xaabbccddeeff7788 ll
r5 = 0x1122334455667788 ll
lddw %r5,0x1122334455667788
lddw %r6,main
r6 = main ll
main:
lock *(u32 *)(r1 + 0xaa) += r2
xaddw [%r1+0xaa],%r2
lock *(u64 *)(r1 + 0xaa) += r2
xadddw [%r1+0xaa],%r2

18
gas/testsuite/gas/bpf/spacing-pseudoc.d Normal file
View File

@ -0,0 +1,18 @@
#as: -EB -mdialect=pseudoc
#source: spacing-pseudoc.s
#objdump: -dr -M hex,pseudoc
#name: spacing, pseudoc syntax
.*: +file format .*bpf.*
Disassembly of section .text:
0+ <.text>:
0: b7 04 00 00 ef be ad de r4=0xdeadbeef
8: 18 04 00 00 ef be ad de r4=0xdeadbeef ll
10: 00 00 00 00 00 00 00 00
18: 05 00 01 00 00 00 00 00 goto 0x1
20: 05 00 01 00 00 00 00 00 goto 0x1
28: 05 00 01 00 00 00 00 00 goto 0x1
30: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1
38: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1

9
gas/testsuite/gas/bpf/spacing-pseudoc.s Normal file
View File

@ -0,0 +1,9 @@
;; This test checks that flexible spacing is supported in the
;; pseudoc syntax.
r4 = 0xdeadbeefll
r4 = 0xdeadbeef ll
goto +1
goto+1
goto1
if w3==3 goto+1
if w3==3 goto1

1
include/dis-asm.h
View File

@ -388,6 +388,7 @@ extern void print_arc_disassembler_options (FILE *);
extern void print_s390_disassembler_options (FILE *);
extern void print_wasm32_disassembler_options (FILE *);
extern void print_loongarch_disassembler_options (FILE *);
extern void print_bpf_disassembler_options (FILE *);
extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);
extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);

1
include/elf/bpf.h
View File

@ -34,6 +34,7 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type)
* It is kept in this file to remind that the value is already taken. */
RELOC_NUMBER (R_BPF_64_NODYLD32, 4)
RELOC_NUMBER (R_BPF_64_32, 10)
RELOC_NUMBER (R_BPF_GNU_64_16, 256)
END_RELOC_NUMBERS (R_BPF_max)
#endif /* _ELF_BPF_H */

306
include/opcode/bpf.h Normal file
View File

@ -0,0 +1,306 @@
/* bpf.h - BPF opcode list for binutils.
Copyright (C) 2023 Free Software Foundation, Inc.
Contributed by Oracle Inc.
This file is part of the GNU binutils.
This is free software; you can redistribute them and/or modify them
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef _BPF_H_
#define _BPF_H_
#include <stdint.h>
/* The BPF ISA has little-endian and big-endian variants. */
enum bpf_endian
{
BPF_ENDIAN_LITTLE,
BPF_ENDIAN_BIG
};
/* Most BPF instructions are conformed by a single 64-bit instruction
word. The lddw instruction is conformed by two consecutive 64-bit
instruction words. */
typedef uint64_t bpf_insn_word;
/* There are several versions of the BPF ISA. */
#define BPF_V1 0x1
#define BPF_V2 0x2
#define BPF_V3 0x3
#define BPF_V4 0x4
#define BPF_XBPF 0xff
/* Masks for the several instruction fields in a BPF instruction.
These assume big-endian BPF instructions. */
#define BPF_CODE 0xff00000000000000UL
#define BPF_REGS 0x00ff000000000000UL
#define BPF_DST 0x00f0000000000000UL
#define BPF_SRC 0x000f000000000000UL
#define BPF_OFFSET16 0x0000ffff00000000UL
#define BPF_IMM32 0x00000000ffffffffUL
/* The BPF opcode instruction field is eight bits long and its
interpretation depends on the instruction class.
For arithmetic and jump instructions the 8-bit opcode field is
subdivided in:
op-code:4 op-src:1 op-class:3
For load/store instructions, the 8-bit opcode field is subdivided
in:
op-mode:3 op-size:2 op-class:3
All the constants defined below are to be applied on the first
64-bit word of a BPF instruction. Please define them assuming
big-endian instructions; the matching and writing routines using
the instruction table know how to handle the endianness groups. */
#define BPF_SRC_X ((uint64_t)0x08 << 56)
#define BPF_SRC_K ((uint64_t)0x00 << 56)
#define BPF_CODE_ADD ((uint64_t)0x00 << 56)
#define BPF_CODE_SUB ((uint64_t)0x10 << 56)
#define BPF_CODE_MUL ((uint64_t)0x20 << 56)
#define BPF_CODE_DIV ((uint64_t)0x30 << 56)
#define BPF_CODE_OR ((uint64_t)0x40 << 56)
#define BPF_CODE_AND ((uint64_t)0x50 << 56)
#define BPF_CODE_LSH ((uint64_t)0x60 << 56)
#define BPF_CODE_RSH ((uint64_t)0x70 << 56)
#define BPF_CODE_NEG ((uint64_t)0x80 << 56)
#define BPF_CODE_MOD ((uint64_t)0x90 << 56)
#define BPF_CODE_XOR ((uint64_t)0xa0 << 56)
#define BPF_CODE_MOV ((uint64_t)0xb0 << 56)
#define BPF_CODE_ARSH ((uint64_t)0xc0 << 56)
#define BPF_CODE_END ((uint64_t)0xd0 << 56)
#define BPF_CODE_JA ((uint64_t)0x00 << 56)
#define BPF_CODE_JEQ ((uint64_t)0x10 << 56)
#define BPF_CODE_JGT ((uint64_t)0x20 << 56)
#define BPF_CODE_JGE ((uint64_t)0x30 << 56)
#define BPF_CODE_JSET ((uint64_t)0x40 << 56)
#define BPF_CODE_JNE ((uint64_t)0x50 << 56)
#define BPF_CODE_JSGT ((uint64_t)0x60 << 56)
#define BPF_CODE_JSGE ((uint64_t)0x70 << 56)
#define BPF_CODE_CALL ((uint64_t)0x80 << 56)
#define BPF_CODE_EXIT ((uint64_t)0x90 << 56)
#define BPF_CODE_JLT ((uint64_t)0xa0 << 56)
#define BPF_CODE_JLE ((uint64_t)0xb0 << 56)
#define BPF_CODE_JSLT ((uint64_t)0xc0 << 56)
#define BPF_CODE_JSLE ((uint64_t)0xd0 << 56)
#define BPF_MODE_IMM ((uint64_t)0x00 << 56)
#define BPF_MODE_ABS ((uint64_t)0x20 << 56)
#define BPF_MODE_IND ((uint64_t)0x40 << 56)
#define BPF_MODE_MEM ((uint64_t)0x60 << 56)
#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)
#define BPF_SIZE_W ((uint64_t)0x00 << 56)
#define BPF_SIZE_H ((uint64_t)0x08 << 56)
#define BPF_SIZE_B ((uint64_t)0x10 << 56)
#define BPF_SIZE_DW ((uint64_t)0x18 << 56)
#define BPF_CLASS_LD ((uint64_t)0x00 << 56)
#define BPF_CLASS_LDX ((uint64_t)0x01 << 56)
#define BPF_CLASS_ST ((uint64_t)0x02 << 56)
#define BPF_CLASS_STX ((uint64_t)0x03 << 56)
#define BPF_CLASS_ALU ((uint64_t)0x04 << 56)
#define BPF_CLASS_JMP ((uint64_t)0x05 << 56)
#define BPF_CLASS_JMP32 ((uint64_t)0x06 << 56)
#define BPF_CLASS_ALU64 ((uint64_t)0x07 << 56)
/* Certain instructions (ab)use other instruction fields as opcodes,
even if these are multi-byte or infra-byte. Bleh. */
#define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32)
#define BPF_IMM32_END16 ((uint64_t)0x00000010)
#define BPF_IMM32_END32 ((uint64_t)0x00000020)
#define BPF_IMM32_END64 ((uint64_t)0x00000040)
#define BPF_IMM32_AADD ((uint64_t)0x00000000)
#define BPF_IMM32_AOR ((uint64_t)0x00000040)
#define BPF_IMM32_AAND ((uint64_t)0x00000050)
#define BPF_IMM32_AXOR ((uint64_t)0x000000a0)
#define BPF_IMM32_AFADD ((uint64_t)0x00000001)
#define BPF_IMM32_AFOR ((uint64_t)0x00000041)
#define BPF_IMM32_AFAND ((uint64_t)0x00000051)
#define BPF_IMM32_AFXOR ((uint64_t)0x000000a1)
#define BPF_IMM32_AXCHG ((uint64_t)0x000000e1)
#define BPF_IMM32_ACMP ((uint64_t)b0x000000f1)
/* Unique identifiers for BPF instructions. */
enum bpf_insn_id
{
BPF_NOINSN = 0,
/* 64-bit load instruction. */
BPF_INSN_LDDW,
/* ALU instructions. */
BPF_INSN_ADDR, BPF_INSN_ADDI, BPF_INSN_SUBR, BPF_INSN_SUBI,
BPF_INSN_MULR, BPF_INSN_MULI, BPF_INSN_SDIVR, BPF_INSN_SDIVI,
BPF_INSN_SMODR, BPF_INSN_SMODI, BPF_INSN_DIVR, BPF_INSN_DIVI,
BPF_INSN_MODR, BPF_INSN_MODI, BPF_INSN_ORR, BPF_INSN_ORI,
BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,
BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,
BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,
BPF_INSN_MOVR, BPF_INSN_MOVI,
/* ALU32 instructions. */
BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I,
BPF_INSN_MUL32R, BPF_INSN_MUL32I, BPF_INSN_SDIV32R, BPF_INSN_SDIV32I,
BPF_INSN_SMOD32R, BPF_INSN_SMOD32I, BPF_INSN_DIV32R, BPF_INSN_DIV32I,
BPF_INSN_MOD32R, BPF_INSN_MOD32I, BPF_INSN_OR32R, BPF_INSN_OR32I,
BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,
BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
BPF_INSN_MOV32R, BPF_INSN_MOV32I,
/* Endianness conversion instructions. */
BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,
BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,
/* Absolute load instructions. */
BPF_INSN_LDABSB, BPF_INSN_LDABSH, BPF_INSN_LDABSW, BPF_INSN_LDABSDW,
/* Indirect load instructions. */
BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,
/* Generic load instructions (to register.) */
BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
/* Generic store instructions (from register.) */
BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,
BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,
/* Compare-and-jump instructions (reg OP reg.) */
BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR,
BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR,
BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER,
BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT,
/* Compare-and-jump instructions (reg OP imm.) */
BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI,
BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI,
BPF_INSN_JSLEI, BPF_INSN_JLEI, BPF_INSN_JSETI, BPF_INSN_JNEI,
BPF_INSN_CALLI,
/* 32-bit compare-and-jump instructions (reg OP reg.) */
BPF_INSN_JEQ32R, BPF_INSN_JGT32R, BPF_INSN_JSGT32R,
BPF_INSN_JGE32R, BPF_INSN_JSGE32R, BPF_INSN_JLT32R, BPF_INSN_JSLT32R,
BPF_INSN_JSLE32R, BPF_INSN_JLE32R, BPF_INSN_JSET32R, BPF_INSN_JNE32R,
/* 32-bit compare-and-jump instructions (reg OP imm.) */
BPF_INSN_JEQ32I, BPF_INSN_JGT32I, BPF_INSN_JSGT32I,
BPF_INSN_JGE32I, BPF_INSN_JSGE32I, BPF_INSN_JLT32I, BPF_INSN_JSLT32I,
BPF_INSN_JSLE32I, BPF_INSN_JLE32I, BPF_INSN_JSET32I, BPF_INSN_JNE32I,
/* Atomic instructions. */
BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR,
/* Atomic instructions with fetching. */
BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR,
/* Atomic instructions (32-bit.) */
BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32,
/* Atomic instructions with fetching (32-bit.) */
BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, BPF_INSN_AFXOR32,
/* GNU simulator specific instruction. */
BPF_INSN_BRKPT,
};
/* Entry for a BPF instruction in the opcodes table. */
struct bpf_opcode
{
/* Unique numerical code for the instruction. */
enum bpf_insn_id id;
/* The instruction template defines both the syntax of the
instruction and the set of the different operands that appear in
the instruction.
Tags:
%% - literal %.
%dr - destination 64-bit register.
%dw - destination 32-bit register.
%sr - source 64-bit register.
%sw - source 32-bit register.
%d32 - 32-bit signed displacement (in 64-bit words minus one.)
%d16 - 16-bit signed displacement (in 64-bit words minus one.)
%o16 - 16-bit signed offset (in bytes.)
%i32 - 32-bit signed immediate.
%I32 - Like %i32.
%i64 - 64-bit signed immediate.
%w - expect zero or more white spaces and print a single space.
%W - expect one or more white spaces and print a single space.
When parsing and printing %o16 and %I32 (but not %i32) an
explicit sign is always expected and included. Therefore, to
denote something like `[%r3 + 10]', please use a template like `[
%sr %o16]' instead of `[ %sr + %o16 ]'.
If %dr, %dw, %sr or %sw are found multiple times in a template,
they refer to the same register, i.e. `%rd = le64 %rd' denotes
`r2 = le64 r2', but not `r2 = le64 r1'.
If %i64 appears in a template then the instruction is 128-bits
long and composed by two consecutive 64-bit instruction words.
A white space character means to expect zero or more white
spaces, and to print no space.
There are two templates defined per instruction, corresponding to
two used different dialects: a "normal" assembly-like syntax and
a "pseudo-c" syntax. Some toolchains support just one of these
dialects. The GNU Toolchain supports both. */
const char *normal;
const char *pseudoc;
/* The version that introduced this instruction. Instructions are
generally not removed once they get introduced. */
uint8_t version;
/* Maks marking the opcode fields in the instruction, and the
opcodes characterizing it.
In multi-word instructions these apply to the first word in the
instruction. Note that these values assumes big-endian
instructions; code using these field must be aware of the
endianness groups to which BPF instructions must conform to and
DTRT. */
bpf_insn_word mask;
bpf_insn_word opcode;
};
/* Try to match a BPF instruction given its first instruction word.
If no matching instruction is found, return NULL. */
const struct bpf_opcode *bpf_match_insn (bpf_insn_word word,
enum bpf_endian endian,
int version);
/* Operand extractors.
These all get big-endian instruction words. Note how the extractor
for 64-bit signed immediates requires two instruction words. */
uint8_t bpf_extract_src (bpf_insn_word word, enum bpf_endian endian);
uint8_t bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian);
int16_t bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian);
int32_t bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian);
int64_t bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
enum bpf_endian endian);
/* Get the opcode occupying the INDEX position in the opcodes table.
The INDEX is zero based. If the provided index overflows the
opcodes table then NULL is returned. */
const struct bpf_opcode *bpf_get_opcode (unsigned int index);
#endif /* !_BPF_H_ */

4
ld/testsuite/ld-bpf/call-1.d
View File

@ -1,7 +1,7 @@
#as: --EL
#as: --EL -mdialect=normal
#source: foo.s
#source: bar.s
#objdump: -dr
#objdump: -dr -M dec
#ld: -EL
#name: CALL with 64_32 reloc

2
ld/testsuite/ld-bpf/call-2.d
View File

@ -1,7 +1,7 @@
#as: --EL
#source: call-2.s
#source: bar.s
#objdump: -dr
#objdump: -dr -M dec
#ld: -EL
#name: CALL with disp32 reloc and addend

4
ld/testsuite/ld-bpf/reloc-insn-external-be.d
View File

@ -1,7 +1,7 @@
#as: --EB
#as: -EB -mdialect=normal
#source: reloc-data.s
#source: reloc-insn-external.s
#objdump: -dr
#objdump: -dr -M hex
#ld: -Tdata=0x20 -EB
#name: reloc insn external BE

4
ld/testsuite/ld-bpf/reloc-insn-external-le.d
View File

@ -1,7 +1,7 @@
#as: --EL
#as: -EL -mdialect=normal
#source: reloc-data.s
#source: reloc-insn-external.s
#objdump: -dr
#objdump: -dr -M hex
#ld: -Tdata=0x20 -EL
#name: reloc insn external LE

16
opcodes/Makefile.am
View File

@ -59,7 +59,6 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
bpf-desc.h bpf-opc.h \
cris-desc.h cris-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
@ -94,10 +93,6 @@ TARGET64_LIBOPCODES_CFILES = \
aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
bpf-asm.c \
bpf-desc.c \
bpf-dis.c \
bpf-ibld.c \
bpf-opc.c \
ia64-dis.c \
ia64-opc.c \
@ -352,7 +347,6 @@ CGENDEPS = \
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
if CGEN_MAINT
BPF_DEPS = stamp-bpf
CRIS_DEPS = stamp-cris
EPIPHANY_DEPS = stamp-epiphany
FR30_DEPS = stamp-fr30
@ -367,7 +361,6 @@ MT_DEPS = stamp-mt
OR1K_DEPS = stamp-or1k
XSTORMY16_DEPS = stamp-xstormy16
else
BPF_DEPS =
CRIS_DEPS =
EPIPHANY_DEPS =
FR30_DEPS =
@ -400,15 +393,6 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
@true
stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
$(MAKE) run-cgen arch=bpf prefix=bpf \
archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
@true

20
opcodes/Makefile.in
View File

@ -450,7 +450,6 @@ BFD_H = ../bfd/bfd.h
# Header files.
HFILES = \
aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
bpf-desc.h bpf-opc.h \
cris-desc.h cris-opc.h \
epiphany-desc.h epiphany-opc.h \
fr30-desc.h fr30-opc.h \
@ -486,10 +485,6 @@ TARGET64_LIBOPCODES_CFILES = \
aarch64-opc-2.c \
alpha-dis.c \
alpha-opc.c \
bpf-asm.c \
bpf-desc.c \
bpf-dis.c \
bpf-ibld.c \
bpf-opc.c \
ia64-dis.c \
ia64-opc.c \
@ -708,8 +703,6 @@ CGENDEPS = \
cgen-asm.in cgen-dis.in cgen-ibld.in
CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
@CGEN_MAINT_FALSE@BPF_DEPS =
@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
@CGEN_MAINT_FALSE@CRIS_DEPS =
@CGEN_MAINT_TRUE@CRIS_DEPS = stamp-cris
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
@ -883,10 +876,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@
@ -1385,15 +1374,6 @@ run-cgen-all:
# For now, require developers to configure with --enable-cgen-maint.
$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
@true
stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
$(MAKE) run-cgen arch=bpf prefix=bpf \
archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
@true

590
opcodes/bpf-asm.c
View File

@ -1,590 +0,0 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "bpf-desc.h"
#include "bpf-opc.h"
#include "opintl.h"
#include "xregex.h"
#include "libiberty.h"
#include "safe-ctype.h"
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
static const char * parse_insn_normal
(CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
/* -- assembler routines inserted here. */
/* -- asm.c */
/* Parse a signed 64-bit immediate. */
static const char *
parse_imm64 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
int64_t *valuep)
{
bfd_vma value;
enum cgen_parse_operand_result result;
const char *errmsg;
errmsg = (* cd->parse_operand_fn)
(cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
&result, &value);
if (!errmsg)
*valuep = value;
return errmsg;
}
/* Endianness size operands are integer immediates whose values can be
16, 32 or 64. */
static const char *
parse_endsize (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
if (errmsg)
return errmsg;
switch (*valuep)
{
case 16:
case 32:
case 64:
break;
default:
return _("expected 16, 32 or 64 in");
}
return NULL;
}
/* Special check to ensure that the right instruction variant is used
for the given endianness induced by the ISA selected in the CPU.
See bpf.cpu for a discussion on how eBPF is really two instruction
sets. */
int
bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
return cgen_bitset_intersect_p (&isas, cd->isas);
}
/* -- dis.c */
const char * bpf_cgen_parse_operand
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
This function is basically just a big switch statement. Earlier versions
used tables to look up the function to use, but
- if the table contains both assembler and disassembler functions then
the disassembler contains much of the assembler and vice-versa,
- there's a lot of inlining possibilities as things grow,
- using a switch statement avoids the function call overhead.
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
the handlers. */
const char *
bpf_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
long junk ATTRIBUTE_UNUSED;
switch (opindex)
{
case BPF_OPERAND_DISP16 :
errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP16, (long *) (& fields->f_offset16));
break;
case BPF_OPERAND_DISP32 :
errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_DISP32, (long *) (& fields->f_imm32));
break;
case BPF_OPERAND_DSTBE :
errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstbe);
break;
case BPF_OPERAND_DSTLE :
errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_dstle);
break;
case BPF_OPERAND_ENDSIZE :
errmsg = parse_endsize (cd, strp, BPF_OPERAND_ENDSIZE, (unsigned long *) (& fields->f_imm32));
break;
case BPF_OPERAND_IMM32 :
errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_IMM32, (long *) (& fields->f_imm32));
break;
case BPF_OPERAND_IMM64 :
errmsg = parse_imm64 (cd, strp, BPF_OPERAND_IMM64, (int64_t *) (& fields->f_imm64));
break;
case BPF_OPERAND_OFFSET16 :
errmsg = cgen_parse_signed_integer (cd, strp, BPF_OPERAND_OFFSET16, (long *) (& fields->f_offset16));
break;
case BPF_OPERAND_SRCBE :
errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcbe);
break;
case BPF_OPERAND_SRCLE :
errmsg = cgen_parse_keyword (cd, strp, & bpf_cgen_opval_h_gpr, & fields->f_srcle);
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while parsing"),
opindex);
abort ();
}
return errmsg;
}
cgen_parse_fn * const bpf_cgen_parse_handlers[] =
{
parse_insn_normal,
};
void
bpf_cgen_init_asm (CGEN_CPU_DESC cd)
{
bpf_cgen_init_opcode_table (cd);
bpf_cgen_init_ibld_table (cd);
cd->parse_handlers = & bpf_cgen_parse_handlers[0];
cd->parse_operand = bpf_cgen_parse_operand;
#ifdef CGEN_ASM_INIT_HOOK
CGEN_ASM_INIT_HOOK
#endif
}
/* Regex construction routine.
This translates an opcode syntax string into a regex string,
by replacing any non-character syntax element (such as an
opcode) with the pattern '.*'
It then compiles the regex and stores it in the opcode, for
later use by bpf_cgen_assemble_insn
Returns NULL for success, an error message for failure. */
char *
bpf_cgen_build_insn_regex (CGEN_INSN *insn)
{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
char *rx = rxbuf;
const CGEN_SYNTAX_CHAR_TYPE *syn;
int reg_err;
syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
/* Mnemonics come first in the syntax string. */
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
return _("missing mnemonic in syntax string");
++syn;
/* Generate a case sensitive regular expression that emulates case
insensitive matching in the "C" locale. We cannot generate a case
insensitive regular expression because in Turkish locales, 'i' and 'I'
are not equal modulo case conversion. */
/* Copy the literal mnemonic out of the insn. */
for (; *mnem; mnem++)
{
char c = *mnem;
if (ISALPHA (c))
{
*rx++ = '[';
*rx++ = TOLOWER (c);
*rx++ = TOUPPER (c);
*rx++ = ']';
}
else
*rx++ = c;
}
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
switch (c)
{
/* Escape any regex metacharacters in the syntax. */
case '.': case '[': case '\\':
case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
*rx++ = '\\';
*rx++ = c;
break;
default:
if (ISALPHA (c))
{
*rx++ = '[';
*rx++ = TOLOWER (c);
*rx++ = TOUPPER (c);
*rx++ = ']';
}
else
*rx++ = c;
break;
}
}
else
{
/* Replace non-syntax fields with globs. */
*rx++ = '.';
*rx++ = '*';
}
}
/* Trailing whitespace ok. */
* rx++ = '[';
* rx++ = ' ';
* rx++ = '\t';
* rx++ = ']';
* rx++ = '*';
/* But anchor it after that. */
* rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
if (reg_err == 0)
return NULL;
else
{
static char msg[80];
regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
regfree ((regex_t *) CGEN_INSN_RX (insn));
free (CGEN_INSN_RX (insn));
(CGEN_INSN_RX (insn)) = NULL;
return msg;
}
}
/* Default insn parser.
The syntax string is scanned and operands are parsed and stored in FIELDS.
Relocs are queued as we go via other callbacks.
??? Note that this is currently an all-or-nothing parser. If we fail to
parse the instruction, we return 0 and the caller will start over from
the beginning. Backtracking will be necessary in parsing subexpressions,
but that can be handled there. Not handling backtracking here may get
expensive in the case of the m68k. Deal with later.
Returns NULL for success, an error message for failure. */
static const char *
parse_insn_normal (CGEN_CPU_DESC cd,
const CGEN_INSN *insn,
const char **strp,
CGEN_FIELDS *fields)
{
/* ??? Runtime added insns not handled yet. */
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
const char *str = *strp;
const char *errmsg;
const char *p;
const CGEN_SYNTAX_CHAR_TYPE * syn;
#ifdef CGEN_MNEMONIC_OPERANDS
/* FIXME: wip */
int past_opcode_p;
#endif
/* For now we assume the mnemonic is first (there are no leading operands).
We can parse it without needing to set up operand parsing.
GAS's input scrubber will ensure mnemonics are lowercase, but we may
not be called from GAS. */
p = CGEN_INSN_MNEMONIC (insn);
while (*p && TOLOWER (*p) == TOLOWER (*str))
++p, ++str;
if (* p)
return _("unrecognized instruction");
#ifndef CGEN_MNEMONIC_OPERANDS
if (* str && ! ISSPACE (* str))
return _("unrecognized instruction");
#endif
CGEN_INIT_PARSE (cd);
cgen_init_parse_operand (cd);
#ifdef CGEN_MNEMONIC_OPERANDS
past_opcode_p = 0;
#endif
/* We don't check for (*str != '\0') here because we want to parse
any trailing fake arguments in the syntax string. */
syn = CGEN_SYNTAX_STRING (syntax);
/* Mnemonics come first for now, ensure valid string. */
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
abort ();
++syn;
while (* syn != 0)
{
/* Non operand chars must match exactly. */
if (CGEN_SYNTAX_CHAR_P (* syn))
{
/* FIXME: While we allow for non-GAS callers above, we assume the
first char after the mnemonic part is a space. */
/* FIXME: We also take inappropriate advantage of the fact that
GAS's input scrubber will remove extraneous blanks. */
if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
{
#ifdef CGEN_MNEMONIC_OPERANDS
if (CGEN_SYNTAX_CHAR(* syn) == ' ')
past_opcode_p = 1;
#endif
++ syn;
++ str;
}
else if (*str)
{
/* Syntax char didn't match. Can't be this insn. */
static char msg [80];
/* xgettext:c-format */
sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
CGEN_SYNTAX_CHAR(*syn), *str);
return msg;
}
else
{
/* Ran out of input. */
static char msg [80];
/* xgettext:c-format */
sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
CGEN_SYNTAX_CHAR(*syn));
return msg;
}
continue;
}
#ifdef CGEN_MNEMONIC_OPERANDS
(void) past_opcode_p;
#endif
/* We have an operand of some sort. */
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
if (errmsg)
return errmsg;
/* Done with this operand, continue with next one. */
++ syn;
}
/* If we're at the end of the syntax string, we're done. */
if (* syn == 0)
{
/* FIXME: For the moment we assume a valid `str' can only contain
blanks now. IE: We needn't try again with a longer version of
the insn and it is assumed that longer versions of insns appear
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
while (ISSPACE (* str))
++ str;
if (* str != '\0')
return _("junk at end of line"); /* FIXME: would like to include `str' */
return NULL;
}
/* We couldn't parse it. */
return _("unrecognized instruction");
}
/* Main entry point.
This routine is called for each instruction to be assembled.
STR points to the insn to be assembled.
We assume all necessary tables have been initialized.
The assembled instruction, less any fixups, is stored in BUF.
Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
still needs to be converted to target byte order, otherwise BUF is an array
of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
or NULL if an error occured (an error message will have already been
printed).
Note that when processing (non-alias) macro-insns,
this function recurses.
??? It's possible to make this cpu-independent.
One would have to deal with a few minor things.
At this point in time doing so would be more of a curiosity than useful
[for example this file isn't _that_ big], but keeping the possibility in
mind helps keep the design clean. */
const CGEN_INSN *
bpf_cgen_assemble_insn (CGEN_CPU_DESC cd,
const char *str,
CGEN_FIELDS *fields,
CGEN_INSN_BYTES_PTR buf,
char **errmsg)
{
const char *start;
CGEN_INSN_LIST *ilist;
const char *parse_errmsg = NULL;
const char *insert_errmsg = NULL;
int recognized_mnemonic = 0;
/* Skip leading white space. */
while (ISSPACE (* str))
++ str;
/* The instructions are stored in hashed lists.
Get the first in the list. */
ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
/* Keep looking until we find a match. */
start = str;
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
{
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
if (! bpf_cgen_insn_supported (cd, insn))
continue;
#endif
/* If the RELAXED attribute is set, this is an insn that shouldn't be
chosen immediately. Instead, it is used during assembler/linker
relaxation if possible. */
if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
continue;
str = start;
/* Skip this insn if str doesn't look right lexically. */
if (CGEN_INSN_RX (insn) != NULL &&
regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
continue;
/* Allow parse/insert handlers to obtain length of insn. */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
if (parse_errmsg != NULL)
continue;
/* ??? 0 is passed for `pc'. */
insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
(bfd_vma) 0);
if (insert_errmsg != NULL)
continue;
/* It is up to the caller to actually output the insn and any
queued relocs. */
return insn;
}
{
static char errbuf[150];
const char *tmp_errmsg;
#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
#define be_verbose 1
#else
#define be_verbose 0
#endif
if (be_verbose)
{
/* If requesting verbose error messages, use insert_errmsg.
Failing that, use parse_errmsg. */
tmp_errmsg = (insert_errmsg ? insert_errmsg :
parse_errmsg ? parse_errmsg :
recognized_mnemonic ?
_("unrecognized form of instruction") :
_("unrecognized instruction"));
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
else
{
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
*errmsg = errbuf;
return NULL;
}
}

1939
opcodes/bpf-desc.c
View File

File diff suppressed because it is too large Load Diff

268
opcodes/bpf-desc.h
View File

@ -1,268 +0,0 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* CPU data header for bpf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef BPF_CPU_H
#define BPF_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
#define CGEN_ARCH bpf
/* Given symbol S, return bpf_cgen_<S>. */
#define CGEN_SYM(s) bpf##_cgen_##s
/* Selected cpu families. */
#define HAVE_CPU_BPFBF
#define CGEN_INSN_LSB0_P 1
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 8
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 16
#define CGEN_INT_INSN_P 0
/* Maximum number of syntax elements in an instruction. */
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
we can't hash on everything up to the space. */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of fields in an instruction. */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
/* Enums. */
/* Enum declaration for eBPF instruction codes. */
typedef enum insn_op_code_alu {
OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3
, OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7
, OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11
, OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_SDIV = 14, OP_CODE_SMOD = 15
, OP_CODE_JA = 0, OP_CODE_JEQ = 1, OP_CODE_JGT = 2, OP_CODE_JGE = 3
, OP_CODE_JSET = 4, OP_CODE_JNE = 5, OP_CODE_JSGT = 6, OP_CODE_JSGE = 7
, OP_CODE_CALL = 8, OP_CODE_EXIT = 9, OP_CODE_JLT = 10, OP_CODE_JLE = 11
, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13
} INSN_OP_CODE_ALU;
/* Enum declaration for eBPF instruction source. */
typedef enum insn_op_src {
OP_SRC_K, OP_SRC_X
} INSN_OP_SRC;
/* Enum declaration for eBPF instruction class. */
typedef enum insn_op_class {
OP_CLASS_LD, OP_CLASS_LDX, OP_CLASS_ST, OP_CLASS_STX
, OP_CLASS_ALU, OP_CLASS_JMP, OP_CLASS_JMP32, OP_CLASS_ALU64
} INSN_OP_CLASS;
/* Enum declaration for eBPF load/store instruction modes. */
typedef enum insn_op_mode {
OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3
, OP_MODE_XADD = 6
} INSN_OP_MODE;
/* Enum declaration for eBPF load/store instruction sizes. */
typedef enum insn_op_size {
OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW
} INSN_OP_SIZE;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_BPF, MACH_XBPF, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE
, ISA_MAX
} ISA_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS ((int) ISA_MAX)
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* cgen_ifld attribute accessor macros. */
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
/* Enum declaration for bpf ifield types. */
typedef enum ifield_type {
BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC
, BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE
, BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS
, BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B
, BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) BPF_F_MAX)
/* Hardware attribute indices. */
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* cgen_hw attribute accessor macros. */
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
/* Enum declaration for bpf hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64
, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
/* Operand attribute indices. */
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* cgen_operand attribute accessor macros. */
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
/* Enum declaration for bpf operand types. */
typedef enum cgen_operand_type {
BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE
, BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32
, BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 11
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
, CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
extern const struct cgen_ifld bpf_cgen_ifld_table[];
/* Attributes. */
extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[];
/* Hardware decls. */
extern CGEN_KEYWORD bpf_cgen_opval_h_gpr;
extern const CGEN_HW_ENTRY bpf_cgen_hw_table[];
#ifdef __cplusplus
}
#endif
#endif /* BPF_CPU_H */

801
opcodes/bpf-dis.c
View File

@ -1,631 +1,284 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
/* bpf-dis.c - BPF disassembler.
Copyright (C) 2023 Free Software Foundation, Inc.
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Contributed by Oracle Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU binutils.
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
This is free software; you can redistribute them and/or modify them
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "disassemble.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "bpf-desc.h"
#include "bpf-opc.h"
#include "opintl.h"
#include "opcode/bpf.h"
/* Default text to print if an instruction isn't recognized. */
#define UNKNOWN_INSN_MSG _("*unknown*")
#include <string.h>
#include <inttypes.h>
static void print_normal
(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
static void print_address
(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
static void print_keyword
(CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
static void print_insn_normal
(CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
static int print_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
static int default_print_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here. */
/* This disassembler supports two different syntaxes for BPF assembly.
One is called "normal" and has the typical form for assembly
languages, with mnemonics and the like. The othe is called
"pseudoc" and looks like C. */
/* -- dis.c */
/* We need to customize the disassembler a bit:
- Use 8 bytes per line by default.
*/
#define CGEN_PRINT_INSN bpf_print_insn
static int
bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
enum bpf_dialect
{
bfd_byte buf[CGEN_MAX_INSN_SIZE];
int buflen;
int status;
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
/* Try again with the minimum part, if min < base. */
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
{
buflen = cd->min_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
}
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
return print_insn (cd, pc, info, buf, buflen);
}
/* Signed immediates should be printed in hexadecimal. */
static void
print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
int64_t value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
if (value <= 9)
(*info->fprintf_func) (info->stream, "%" PRId64, value);
else
(*info->fprintf_func) (info->stream, "%#" PRIx64, value);
/* This is to avoid -Wunused-function for print_normal. */
if (0)
print_normal (cd, dis_info, value, attrs, pc, length);
}
/* Endianness bit sizes should be printed in decimal. */
static void
print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
unsigned long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "%lu", value);
}
/* -- */
void bpf_cgen_print_operand
(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
of dis-asm.h on cgen.h.
This function is basically just a big switch statement. Earlier versions
used tables to look up the function to use, but
- if the table contains both assembler and disassembler functions then
the disassembler contains much of the assembler and vice-versa,
- there's a lot of inlining possibilities as things grow,
- using a switch statement avoids the function call overhead.
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
the handlers. */
void
bpf_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
case BPF_OPERAND_DISP16 :
print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case BPF_OPERAND_DISP32 :
print_normal (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case BPF_OPERAND_DSTBE :
print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstbe, 0);
break;
case BPF_OPERAND_DSTLE :
print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);
break;
case BPF_OPERAND_ENDSIZE :
print_endsize (cd, info, fields->f_imm32, 0, pc, length);
break;
case BPF_OPERAND_IMM32 :
print_immediate (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case BPF_OPERAND_IMM64 :
print_immediate (cd, info, fields->f_imm64, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case BPF_OPERAND_OFFSET16 :
print_immediate (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case BPF_OPERAND_SRCBE :
print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcbe, 0);
break;
case BPF_OPERAND_SRCLE :
print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while printing insn"),
opindex);
abort ();
}
}
cgen_print_fn * const bpf_cgen_print_handlers[] =
{
print_insn_normal,
BPF_DIALECT_NORMAL,
BPF_DIALECT_PSEUDOC
};
/* Global configuration for the disassembler. */
static enum bpf_dialect asm_dialect = BPF_DIALECT_NORMAL;
static int asm_bpf_version = BPF_V4;
static int asm_obase = 10;
/* Print BPF specific command-line options. */
void
bpf_cgen_init_dis (CGEN_CPU_DESC cd)
print_bpf_disassembler_options (FILE *stream)
{
bpf_cgen_init_opcode_table (cd);
bpf_cgen_init_ibld_table (cd);
cd->print_handlers = & bpf_cgen_print_handlers[0];
cd->print_operand = bpf_cgen_print_operand;
fprintf (stream, _("\n\
The following BPF specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, "\n");
fprintf (stream, _("\
pseudoc Use pseudo-c syntax.\n\
v1,v2,v3,v4,xbpf Version of the BPF ISA to use.\n\
hex,oct,dec Output numerical base for immediates.\n"));
}
/* Default print handler. */
/* Parse BPF specific command-line options. */
static void
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
long value,
unsigned int attrs,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
parse_bpf_dis_option (const char *option)
{
disassemble_info *info = (disassemble_info *) dis_info;
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
(*info->fprintf_func) (info->stream, "%ld", value);
if (strcmp (option, "pseudoc") == 0)
asm_dialect = BPF_DIALECT_PSEUDOC;
else if (strcmp (option, "v1") == 0)
asm_bpf_version = BPF_V1;
else if (strcmp (option, "v2") == 0)
asm_bpf_version = BPF_V2;
else if (strcmp (option, "v3") == 0)
asm_bpf_version = BPF_V3;
else if (strcmp (option, "v4") == 0)
asm_bpf_version = BPF_V4;
else if (strcmp (option, "xbpf") == 0)
asm_bpf_version = BPF_XBPF;
else if (strcmp (option, "hex") == 0)
asm_obase = 16;
else if (strcmp (option, "oct") == 0)
asm_obase = 8;
else if (strcmp (option, "dec") == 0)
asm_obase = 10;
else
(*info->fprintf_func) (info->stream, "0x%lx", value);
/* xgettext:c-format */
opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
}
/* Default address handler. */
static void
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
bfd_vma value,
unsigned int attrs,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
parse_bpf_dis_options (const char *opts_in)
{
disassemble_info *info = (disassemble_info *) dis_info;
char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
(*info->fprintf_func) (info->stream, "%ld", (long) value);
else
(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
for ( ; opt_end != NULL; opt = opt_end + 1)
{
if ((opt_end = strchr (opt, ',')) != NULL)
*opt_end = 0;
parse_bpf_dis_option (opt);
}
free (opts);
}
/* Keyword print handler. */
/* Auxiliary function used in print_insn_bpf below. */
static void
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void *dis_info,
CGEN_KEYWORD *keyword_table,
long value,
unsigned int attrs ATTRIBUTE_UNUSED)
print_register (disassemble_info *info,
const char *tag, uint8_t regno)
{
disassemble_info *info = (disassemble_info *) dis_info;
const CGEN_KEYWORD_ENTRY *ke;
const char *fmt
= (asm_dialect == BPF_DIALECT_NORMAL
? "%%r%d"
: ((*(tag + 2) == 'w')
? "w%d"
: "r%d"));
ke = cgen_keyword_lookup_value (keyword_table, value);
if (ke != NULL)
(*info->fprintf_func) (info->stream, "%s", ke->name);
else
(*info->fprintf_func) (info->stream, "???");
}
/* Default insn printer.
DIS_INFO is defined as `void *' so the disassembler needn't know anything
about disassemble_info. */
static void
print_insn_normal (CGEN_CPU_DESC cd,
void *dis_info,
const CGEN_INSN *insn,
CGEN_FIELDS *fields,
bfd_vma pc,
int length)
{
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
disassemble_info *info = (disassemble_info *) dis_info;
const CGEN_SYNTAX_CHAR_TYPE *syn;
CGEN_INIT_PRINT (cd);
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
{
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
{
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
continue;
}
if (CGEN_SYNTAX_CHAR_P (*syn))
{
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
continue;
}
/* We have an operand. */
bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
fields, CGEN_INSN_ATTRS (insn), pc, length);
}
}
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
the extract info.
Returns 0 if all is well, non-zero otherwise. */
static int
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
bfd_vma pc,
disassemble_info *info,
bfd_byte *buf,
int buflen,
CGEN_EXTRACT_INFO *ex_info,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
ex_info->dis_info = info;
ex_info->valid = (1 << buflen) - 1;
ex_info->insn_bytes = buf;
*insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
return 0;
}
/* Utility to print an insn.
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
The result is the size of the insn in bytes or zero for an unknown insn
or -1 if an error occurs fetching data (memory_error_func will have
been called). */
static int
print_insn (CGEN_CPU_DESC cd,
bfd_vma pc,
disassemble_info *info,
bfd_byte *buf,
unsigned int buflen)
{
CGEN_INSN_INT insn_value;
const CGEN_INSN_LIST *insn_list;
CGEN_EXTRACT_INFO ex_info;
int basesize;
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call
read_insn, since the incoming buffer is already read (and possibly
modified a la m32r). */
ex_info.valid = (1 << buflen) - 1;
ex_info.dis_info = info;
ex_info.insn_bytes = buf;
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
while (insn_list != NULL)
{
const CGEN_INSN *insn = insn_list->insn;
CGEN_FIELDS fields;
int length;
unsigned long insn_value_cropped;
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! bpf_cgen_insn_supported (cd, insn))
{
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
continue;
}
#endif
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the extract
handler. */
/* Base size may exceed this instruction's size. Extract the
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
== CGEN_INSN_BASE_VALUE (insn))
{
/* Printing is handled in two passes. The first pass parses the
machine insn and extracts the fields. The second pass prints
them. */
/* Make sure the entire insn is loaded into insn_value, if it
can fit. */
if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
{
unsigned long full_insn_value;
int rc = read_insn (cd, pc, info, buf,
CGEN_INSN_BITSIZE (insn) / 8,
& ex_info, & full_insn_value);
if (rc != 0)
return rc;
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, full_insn_value, &fields, pc);
}
else
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
}
return 0;
}
/* Default value for CGEN_PRINT_INSN.
The result is the size of the insn in bytes or zero for an unknown insn
or -1 if an error occured fetching bytes. */
#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif
static int
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
bfd_byte buf[CGEN_MAX_INSN_SIZE];
int buflen;
int status;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
/* Try again with the minimum part, if min < base. */
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
{
buflen = cd->min_insn_bitsize / 8;
status = (*info->read_memory_func) (pc, buf, buflen, info);
}
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
return print_insn (cd, pc, info, buf, buflen);
(*info->fprintf_styled_func) (info->stream, dis_style_register, fmt, regno);
}
/* Main entry point.
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
CGEN_BITSET *isa;
int mach;
int endian;
int insn_endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
int
print_insn_bpf (bfd_vma pc, disassemble_info *info)
{
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
static CGEN_BITSET *prev_isa;
static int prev_mach;
static int prev_endian;
static int prev_insn_endian;
int length;
CGEN_BITSET *isa;
int mach;
int endian = (info->endian == BFD_ENDIAN_BIG
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE);
int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE);
enum bfd_architecture arch;
int insn_size = 8, status;
bfd_byte insn_bytes[16];
bpf_insn_word word = 0;
const struct bpf_opcode *insn = NULL;
enum bpf_endian endian = (info->endian == BFD_ENDIAN_LITTLE
? BPF_ENDIAN_LITTLE : BPF_ENDIAN_BIG);
/* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_bpf
#endif
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
mach = CGEN_COMPUTE_MACH (info);
#else
mach = info->mach;
#endif
#ifdef CGEN_COMPUTE_ISA
{
static CGEN_BITSET *permanent_isa;
if (!permanent_isa)
permanent_isa = cgen_bitset_create (MAX_ISAS);
isa = permanent_isa;
cgen_bitset_clear (isa);
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
&& (cgen_bitset_compare (isa, prev_isa) != 0
|| mach != prev_mach
|| endian != prev_endian))
/* Handle bpf-specific command-line options. */
if (info->disassembler_options != NULL)
{
cd = 0;
for (cl = cd_list; cl; cl = cl->next)
{
if (cgen_bitset_compare (cl->isa, isa) == 0 &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
prev_isa = cd->isas;
break;
}
}
parse_bpf_dis_options (info->disassembler_options);
/* Avoid repeteadly parsing the options. */
info->disassembler_options = NULL;
}
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
/* Print eight bytes per line. */
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
/* Read an instruction word. */
status = (*info->read_memory_func) (pc, insn_bytes, 8, info);
if (status != 0)
{
const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
const char *mach_name;
if (!arch_type)
abort ();
mach_name = arch_type->printable_name;
prev_isa = cgen_bitset_copy (isa);
prev_mach = mach;
prev_endian = endian;
prev_insn_endian = insn_endian;
cd = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, prev_endian,
CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = prev_isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
cd_list = cl;
bpf_cgen_init_dis (cd);
(*info->memory_error_func) (status, pc, info);
return -1;
}
word = (bpf_insn_word) bfd_getb64 (insn_bytes);
/* We try to have as much common code as possible.
But at this point some targets need to take over. */
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
but if not possible try to move this hook elsewhere rather than
have two hooks. */
length = CGEN_PRINT_INSN (cd, pc, info);
if (length > 0)
return length;
if (length < 0)
return -1;
/* Try to match an instruction with it. */
insn = bpf_match_insn (word, endian, asm_bpf_version);
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
return cd->default_insn_bitsize / 8;
/* Print it out. */
if (insn)
{
const char *insn_tmpl
= asm_dialect == BPF_DIALECT_NORMAL ? insn->normal : insn->pseudoc;
const char *p = insn_tmpl;
/* Print the template contents completed with the instruction
operands. */
for (p = insn_tmpl; *p != '\0';)
{
switch (*p)
{
case ' ':
/* Single space prints to nothing. */
p += 1;
break;
case '%':
if (*(p + 1) == '%')
{
(*info->fprintf_styled_func) (info->stream, dis_style_text, "%%");
p += 2;
}
else if (*(p + 1) == 'w' || *(p + 1) == 'W')
{
/* %W prints to a single space. */
(*info->fprintf_styled_func) (info->stream, dis_style_text, " ");
p += 2;
}
else if (strncmp (p, "%dr", 3) == 0)
{
print_register (info, p, bpf_extract_dst (word, endian));
p += 3;
}
else if (strncmp (p, "%sr", 3) == 0)
{
print_register (info, p, bpf_extract_src (word, endian));
p += 3;
}
else if (strncmp (p, "%dw", 3) == 0)
{
print_register (info, p, bpf_extract_dst (word, endian));
p += 3;
}
else if (strncmp (p, "%sw", 3) == 0)
{
print_register (info, p, bpf_extract_src (word, endian));
p += 3;
}
else if (strncmp (p, "%i32", 4) == 0
|| strncmp (p, "%d32", 4) == 0
|| strncmp (p, "%I32", 4) == 0)
{
int32_t imm32 = bpf_extract_imm32 (word, endian);
if (p[1] == 'I')
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
"%s",
asm_obase != 10 || imm32 > 0 ? "+" : "");
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
asm_obase == 10 ? "%" PRIi32
: asm_obase == 8 ? "%" PRIo32
: "0x%" PRIx32,
imm32);
p += 4;
}
else if (strncmp (p, "%o16", 4) == 0
|| strncmp (p, "%d16", 4) == 0)
{
int16_t offset16 = bpf_extract_offset16 (word, endian);
if (p[1] == 'o')
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
"%s",
asm_obase != 10 || offset16 > 0 ? "+" : "");
if (asm_obase == 16 || asm_obase == 8)
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
asm_obase == 8 ? "0%" PRIo16 : "0x%" PRIx16,
(uint16_t) offset16);
else
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
"%" PRIi16, offset16);
p += 4;
}
else if (strncmp (p, "%i64", 4) == 0)
{
bpf_insn_word word2 = 0;
status = (*info->read_memory_func) (pc + 8, insn_bytes + 8,
8, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc + 8, info);
return -1;
}
word2 = (bpf_insn_word) bfd_getb64 (insn_bytes + 8);
(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
asm_obase == 10 ? "%" PRIi64
: asm_obase == 8 ? "0%" PRIo64
: "0x%" PRIx64,
bpf_extract_imm64 (word, word2, endian));
insn_size = 16;
p += 4;
}
else
{
/* xgettext:c-format */
opcodes_error_handler (_("# internal error, unknown tag in opcode template (%s)"),
insn_tmpl);
return -1;
}
break;
default:
/* Any other character is printed literally. */
(*info->fprintf_styled_func) (info->stream, dis_style_text, "%c", *p);
p += 1;
}
}
}
else
(*info->fprintf_styled_func) (info->stream, dis_style_text, "<unknown>");
return insn_size;
}

961
opcodes/bpf-ibld.c
View File

@ -1,961 +0,0 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Instruction building/extraction support for bpf. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "bpf-desc.h"
#include "bpf-opc.h"
#include "cgen/basic-modes.h"
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
#define FLD(f) (fields->f)
static const char * insert_normal
(CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
static const char * insert_insn_normal
(CGEN_CPU_DESC, const CGEN_INSN *,
CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
static int extract_normal
(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, bfd_vma, long *);
static int extract_insn_normal
(CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
#if CGEN_INT_INSN_P
static void put_insn_int_value
(CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
#endif
#if ! CGEN_INT_INSN_P
static CGEN_INLINE void insert_1
(CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
static CGEN_INLINE int fill_cache
(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
static CGEN_INLINE long extract_1
(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
#endif
/* Operand insertion. */
#if ! CGEN_INT_INSN_P
/* Subroutine of insert_normal. */
static CGEN_INLINE void
insert_1 (CGEN_CPU_DESC cd,
unsigned long value,
int start,
int length,
int word_length,
unsigned char *bufp)
{
unsigned long x, mask;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
/* Written this way to avoid undefined behaviour. */
mask = (1UL << (length - 1) << 1) - 1;
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian);
}
#endif /* ! CGEN_INT_INSN_P */
/* Default insertion routine.
ATTRS is a mask of the boolean attributes.
WORD_OFFSET is the offset in bits from the start of the insn of the value.
WORD_LENGTH is the length of the word in bits in which the value resides.
START is the starting bit number in the word, architecture origin.
LENGTH is the length of VALUE in bits.
TOTAL_LENGTH is the total length of the insn in bits.
The result is an error message or NULL if success. */
/* ??? This duplicates functionality with bfd's howto table and
bfd_install_relocation. */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static const char *
insert_normal (CGEN_CPU_DESC cd,
long value,
unsigned int attrs,
unsigned int word_offset,
unsigned int start,
unsigned int length,
unsigned int word_length,
unsigned int total_length,
CGEN_INSN_BYTES_PTR buffer)
{
static char errbuf[100];
unsigned long mask;
/* If LENGTH is zero, this operand doesn't contribute to the value. */
if (length == 0)
return NULL;
/* Written this way to avoid undefined behaviour. */
mask = (1UL << (length - 1) << 1) - 1;
if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
word_length may be too big. */
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
{
if (word_offset == 0
&& word_length > total_length)
word_length = total_length;
}
/* Ensure VALUE will fit. */
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
{
long minval = - (1UL << (length - 1));
unsigned long maxval = mask;
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
/* xgettext:c-format */
sprintf (errbuf,
_("operand out of range (%ld not between %ld and %lu)"),
value, minval, maxval);
return errbuf;
}
}
else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
{
unsigned long maxval = mask;
unsigned long val = (unsigned long) value;
/* For hosts with a word size > 32 check to see if value has been sign
extended beyond 32 bits. If so then ignore these higher sign bits
as the user is attempting to store a 32-bit signed value into an
unsigned 32-bit field which is allowed. */
if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
val &= 0xFFFFFFFF;
if (val > maxval)
{
/* xgettext:c-format */
sprintf (errbuf,
_("operand out of range (0x%lx not between 0 and 0x%lx)"),
val, maxval);
return errbuf;
}
}
else
{
if (! cgen_signed_overflow_ok_p (cd))
{
long minval = - (1UL << (length - 1));
long maxval = (1UL << (length - 1)) - 1;
if (value < minval || value > maxval)
{
sprintf
/* xgettext:c-format */
(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
value, minval, maxval);
return errbuf;
}
}
}
#if CGEN_INT_INSN_P
{
int shift_within_word, shift_to_word, shift;
/* How to shift the value to BIT0 of the word. */
shift_to_word = total_length - (word_offset + word_length);
/* How to shift the value to the field within the word. */
if (CGEN_INSN_LSB0_P)
shift_within_word = start + 1 - length;
else
shift_within_word = word_length - start - length;
/* The total SHIFT, then mask in the value. */
shift = shift_to_word + shift_within_word;
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
#else /* ! CGEN_INT_INSN_P */
{
unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
insert_1 (cd, value, start, length, word_length, bufp);
}
#endif /* ! CGEN_INT_INSN_P */
return NULL;
}
/* Default insn builder (insert handler).
The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
recorded in host byte order, otherwise BUFFER is an array of bytes
and the value is recorded in target byte order).
The result is an error message or NULL if success. */
static const char *
insert_insn_normal (CGEN_CPU_DESC cd,
const CGEN_INSN * insn,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc)
{
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
unsigned long value;
const CGEN_SYNTAX_CHAR_TYPE * syn;
CGEN_INIT_INSERT (cd);
value = CGEN_INSN_BASE_VALUE (insn);
/* If we're recording insns as numbers (rather than a string of bytes),
target byte order handling is deferred until later. */
#if CGEN_INT_INSN_P
put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
CGEN_FIELDS_BITSIZE (fields), value);
#else
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
value, cd->insn_endian);
#endif /* ! CGEN_INT_INSN_P */
/* ??? It would be better to scan the format's fields.
Still need to be able to insert a value based on the operand though;
e.g. storing a branch displacement that got resolved later.
Needs more thought first. */
for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
{
const char *errmsg;
if (CGEN_SYNTAX_CHAR_P (* syn))
continue;
errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
fields, buffer, pc);
if (errmsg)
return errmsg;
}
return NULL;
}
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
CGEN_INSN_BYTES_PTR buf,
int length,
int insn_length,
CGEN_INSN_INT value)
{
/* For architectures with insns smaller than the base-insn-bitsize,
length may be too big. */
if (length > insn_length)
*buf = value;
else
{
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = length == 0 ? 0 : (1UL << (length - 1) << 1) - 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
#endif
/* Operand extraction. */
#if ! CGEN_INT_INSN_P
/* Subroutine of extract_normal.
Ensure sufficient bytes are cached in EX_INFO.
OFFSET is the offset in bytes from the start of the insn of the value.
BYTES is the length of the needed value.
Returns 1 for success, 0 for failure. */
static CGEN_INLINE int
fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
CGEN_EXTRACT_INFO *ex_info,
int offset,
int bytes,
bfd_vma pc)
{
/* It's doubtful that the middle part has already been fetched so
we don't optimize that case. kiss. */
unsigned int mask;
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
/* First do a quick check. */
mask = (1 << bytes) - 1;
if (((ex_info->valid >> offset) & mask) == mask)
return 1;
/* Search for the first byte we need to read. */
for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
if (! (mask & ex_info->valid))
break;
if (bytes)
{
int status;
pc += offset;
status = (*info->read_memory_func)
(pc, ex_info->insn_bytes + offset, bytes, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return 0;
}
ex_info->valid |= ((1 << bytes) - 1) << offset;
}
return 1;
}
/* Subroutine of extract_normal. */
static CGEN_INLINE long
extract_1 (CGEN_CPU_DESC cd,
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
int start,
int length,
int word_length,
unsigned char *bufp,
bfd_vma pc ATTRIBUTE_UNUSED)
{
unsigned long x;
int shift;
x = cgen_get_insn_value (cd, bufp, word_length, cd->endian);
if (CGEN_INSN_LSB0_P)
shift = (start + 1) - length;
else
shift = (word_length - (start + length));
return x >> shift;
}
#endif /* ! CGEN_INT_INSN_P */
/* Default extraction routine.
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
or sometimes less for cases like the m32r where the base insn size is 32
but some insns are 16 bits.
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
but for generality we take a bitmask of all of them.
WORD_OFFSET is the offset in bits from the start of the insn of the value.
WORD_LENGTH is the length of the word in bits in which the value resides.
START is the starting bit number in the word, architecture origin.
LENGTH is the length of VALUE in bits.
TOTAL_LENGTH is the total length of the insn in bits.
Returns 1 for success, 0 for failure. */
/* ??? The return code isn't properly used. wip. */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static int
extract_normal (CGEN_CPU_DESC cd,
#if ! CGEN_INT_INSN_P
CGEN_EXTRACT_INFO *ex_info,
#else
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
#endif
CGEN_INSN_INT insn_value,
unsigned int attrs,
unsigned int word_offset,
unsigned int start,
unsigned int length,
unsigned int word_length,
unsigned int total_length,
#if ! CGEN_INT_INSN_P
bfd_vma pc,
#else
bfd_vma pc ATTRIBUTE_UNUSED,
#endif
long *valuep)
{
long value, mask;
/* If LENGTH is zero, this operand doesn't contribute to the value
so give it a standard value of zero. */
if (length == 0)
{
*valuep = 0;
return 1;
}
if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
word_length may be too big. */
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
{
if (word_offset + word_length > total_length)
word_length = total_length - word_offset;
}
/* Does the value reside in INSN_VALUE, and at the right alignment? */
if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
{
if (CGEN_INSN_LSB0_P)
value = insn_value >> ((word_offset + start + 1) - length);
else
value = insn_value >> (total_length - ( word_offset + start + length));
}
#if ! CGEN_INT_INSN_P
else
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
if (word_length > 8 * sizeof (CGEN_INSN_INT))
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
{
*valuep = 0;
return 0;
}
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
}
#endif /* ! CGEN_INT_INSN_P */
/* Written this way to avoid undefined behaviour. */
mask = (1UL << (length - 1) << 1) - 1;
value &= mask;
/* sign extend? */
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
&& (value & (1UL << (length - 1))))
value |= ~mask;
*valuep = value;
return 1;
}
/* Default insn extractor.
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
The extracted fields are stored in FIELDS.
EX_INFO is used to handle reading variable length insns.
Return the length of the insn in bits, or 0 if no match,
or -1 if an error occurs fetching data (memory_error_func will have
been called). */
static int
extract_insn_normal (CGEN_CPU_DESC cd,
const CGEN_INSN *insn,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS *fields,
bfd_vma pc)
{
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
const CGEN_SYNTAX_CHAR_TYPE *syn;
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
CGEN_INIT_EXTRACT (cd);
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
{
int length;
if (CGEN_SYNTAX_CHAR_P (*syn))
continue;
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
ex_info, insn_value, fields, pc);
if (length <= 0)
return length;
}
/* We recognized and successfully extracted this insn. */
return CGEN_INSN_BITSIZE (insn);
}
/* Machine generated code added here. */
const char * bpf_cgen_insert_operand
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
This function is basically just a big switch statement. Earlier versions
used tables to look up the function to use, but
- if the table contains both assembler and disassembler functions then
the disassembler contains much of the assembler and vice-versa,
- there's a lot of inlining possibilities as things grow,
- using a switch statement avoids the function call overhead.
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
the handlers. It's also needed by GAS to insert operands that couldn't be
resolved during parsing. */
const char *
bpf_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
switch (opindex)
{
case BPF_OPERAND_DISP16 :
errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
break;
case BPF_OPERAND_DISP32 :
errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
break;
case BPF_OPERAND_DSTBE :
errmsg = insert_normal (cd, fields->f_dstbe, 0, 8, 7, 4, 8, total_length, buffer);
break;
case BPF_OPERAND_DSTLE :
errmsg = insert_normal (cd, fields->f_dstle, 0, 8, 3, 4, 8, total_length, buffer);
break;
case BPF_OPERAND_ENDSIZE :
errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
break;
case BPF_OPERAND_IMM32 :
errmsg = insert_normal (cd, fields->f_imm32, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, buffer);
break;
case BPF_OPERAND_IMM64 :
{
{
FLD (f_imm64_b) = 0;
FLD (f_imm64_c) = ((UDI) (FLD (f_imm64)) >> (32));
FLD (f_imm64_a) = ((FLD (f_imm64)) & (MAKEDI (0, 0xffffffff)));
}
errmsg = insert_normal (cd, fields->f_imm64_a, 0, 32, 31, 32, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_imm64_b, 0, 64, 31, 32, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_imm64_c, 0, 96, 31, 32, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case BPF_OPERAND_OFFSET16 :
errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, buffer);
break;
case BPF_OPERAND_SRCBE :
errmsg = insert_normal (cd, fields->f_srcbe, 0, 8, 3, 4, 8, total_length, buffer);
break;
case BPF_OPERAND_SRCLE :
errmsg = insert_normal (cd, fields->f_srcle, 0, 8, 7, 4, 8, total_length, buffer);
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while building insn"),
opindex);
abort ();
}
return errmsg;
}
int bpf_cgen_extract_operand
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
??? Actual values aren't well defined right now.
This function is basically just a big switch statement. Earlier versions
used tables to look up the function to use, but
- if the table contains both assembler and disassembler functions then
the disassembler contains much of the assembler and vice-versa,
- there's a lot of inlining possibilities as things grow,
- using a switch statement avoids the function call overhead.
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
the handlers. */
int
bpf_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
switch (opindex)
{
case BPF_OPERAND_DISP16 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
break;
case BPF_OPERAND_DISP32 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
break;
case BPF_OPERAND_DSTBE :
length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_dstbe);
break;
case BPF_OPERAND_DSTLE :
length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_dstle);
break;
case BPF_OPERAND_ENDSIZE :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
break;
case BPF_OPERAND_IMM32 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 32, 31, 32, 32, total_length, pc, & fields->f_imm32);
break;
case BPF_OPERAND_IMM64 :
{
length = extract_normal (cd, ex_info, insn_value, 0, 32, 31, 32, 32, total_length, pc, & fields->f_imm64_a);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 64, 31, 32, 32, total_length, pc, & fields->f_imm64_b);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 96, 31, 32, 32, total_length, pc, & fields->f_imm64_c);
if (length <= 0) break;
{
FLD (f_imm64) = ((((((UDI) (UINT) (FLD (f_imm64_c)))) << (32))) | (((UDI) (UINT) (FLD (f_imm64_a)))));
}
}
break;
case BPF_OPERAND_OFFSET16 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 16, 15, 16, 16, total_length, pc, & fields->f_offset16);
break;
case BPF_OPERAND_SRCBE :
length = extract_normal (cd, ex_info, insn_value, 0, 8, 3, 4, 8, total_length, pc, & fields->f_srcbe);
break;
case BPF_OPERAND_SRCLE :
length = extract_normal (cd, ex_info, insn_value, 0, 8, 7, 4, 8, total_length, pc, & fields->f_srcle);
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while decoding insn"),
opindex);
abort ();
}
return length;
}
cgen_insert_fn * const bpf_cgen_insert_handlers[] =
{
insert_insn_normal,
};
cgen_extract_fn * const bpf_cgen_extract_handlers[] =
{
extract_insn_normal,
};
int bpf_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma bpf_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
TODO: floating point, inlining support, remove cases where result type
not appropriate. */
int
bpf_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
switch (opindex)
{
case BPF_OPERAND_DISP16 :
value = fields->f_offset16;
break;
case BPF_OPERAND_DISP32 :
value = fields->f_imm32;
break;
case BPF_OPERAND_DSTBE :
value = fields->f_dstbe;
break;
case BPF_OPERAND_DSTLE :
value = fields->f_dstle;
break;
case BPF_OPERAND_ENDSIZE :
value = fields->f_imm32;
break;
case BPF_OPERAND_IMM32 :
value = fields->f_imm32;
break;
case BPF_OPERAND_IMM64 :
value = fields->f_imm64;
break;
case BPF_OPERAND_OFFSET16 :
value = fields->f_offset16;
break;
case BPF_OPERAND_SRCBE :
value = fields->f_srcbe;
break;
case BPF_OPERAND_SRCLE :
value = fields->f_srcle;
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while getting int operand"),
opindex);
abort ();
}
return value;
}
bfd_vma
bpf_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
switch (opindex)
{
case BPF_OPERAND_DISP16 :
value = fields->f_offset16;
break;
case BPF_OPERAND_DISP32 :
value = fields->f_imm32;
break;
case BPF_OPERAND_DSTBE :
value = fields->f_dstbe;
break;
case BPF_OPERAND_DSTLE :
value = fields->f_dstle;
break;
case BPF_OPERAND_ENDSIZE :
value = fields->f_imm32;
break;
case BPF_OPERAND_IMM32 :
value = fields->f_imm32;
break;
case BPF_OPERAND_IMM64 :
value = fields->f_imm64;
break;
case BPF_OPERAND_OFFSET16 :
value = fields->f_offset16;
break;
case BPF_OPERAND_SRCBE :
value = fields->f_srcbe;
break;
case BPF_OPERAND_SRCLE :
value = fields->f_srcle;
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while getting vma operand"),
opindex);
abort ();
}
return value;
}
void bpf_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void bpf_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
TODO: floating point, inlining support, remove cases where argument type
not appropriate. */
void
bpf_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
case BPF_OPERAND_DISP16 :
fields->f_offset16 = value;
break;
case BPF_OPERAND_DISP32 :
fields->f_imm32 = value;
break;
case BPF_OPERAND_DSTBE :
fields->f_dstbe = value;
break;
case BPF_OPERAND_DSTLE :
fields->f_dstle = value;
break;
case BPF_OPERAND_ENDSIZE :
fields->f_imm32 = value;
break;
case BPF_OPERAND_IMM32 :
fields->f_imm32 = value;
break;
case BPF_OPERAND_IMM64 :
fields->f_imm64 = value;
break;
case BPF_OPERAND_OFFSET16 :
fields->f_offset16 = value;
break;
case BPF_OPERAND_SRCBE :
fields->f_srcbe = value;
break;
case BPF_OPERAND_SRCLE :
fields->f_srcle = value;
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while setting int operand"),
opindex);
abort ();
}
}
void
bpf_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
case BPF_OPERAND_DISP16 :
fields->f_offset16 = value;
break;
case BPF_OPERAND_DISP32 :
fields->f_imm32 = value;
break;
case BPF_OPERAND_DSTBE :
fields->f_dstbe = value;
break;
case BPF_OPERAND_DSTLE :
fields->f_dstle = value;
break;
case BPF_OPERAND_ENDSIZE :
fields->f_imm32 = value;
break;
case BPF_OPERAND_IMM32 :
fields->f_imm32 = value;
break;
case BPF_OPERAND_IMM64 :
fields->f_imm64 = value;
break;
case BPF_OPERAND_OFFSET16 :
fields->f_offset16 = value;
break;
case BPF_OPERAND_SRCBE :
fields->f_srcbe = value;
break;
case BPF_OPERAND_SRCLE :
fields->f_srcle = value;
break;
default :
/* xgettext:c-format */
opcodes_error_handler
(_("internal error: unrecognized field %d while setting vma operand"),
opindex);
abort ();
}
}
/* Function to call before using the instruction builder tables. */
void
bpf_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & bpf_cgen_insert_handlers[0];
cd->extract_handlers = & bpf_cgen_extract_handlers[0];
cd->insert_operand = bpf_cgen_insert_operand;
cd->extract_operand = bpf_cgen_extract_operand;
cd->get_int_operand = bpf_cgen_get_int_operand;
cd->set_int_operand = bpf_cgen_set_int_operand;
cd->get_vma_operand = bpf_cgen_get_vma_operand;
cd->set_vma_operand = bpf_cgen_set_vma_operand;
}

2309
opcodes/bpf-opc.c
View File

File diff suppressed because it is too large Load Diff

166
opcodes/bpf-opc.h
View File

@ -1,166 +0,0 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Instruction opcode header for bpf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef BPF_OPC_H
#define BPF_OPC_H
#ifdef __cplusplus
extern "C" {
#endif
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 1
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) 0
/* Allows reason codes to be output when assembler errors occur. */
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- opc.c */
/* Enum declaration for bpf instruction types. */
typedef enum cgen_insn_type {
BPF_INSN_INVALID, BPF_INSN_ADDILE, BPF_INSN_ADDRLE, BPF_INSN_ADD32ILE
, BPF_INSN_ADD32RLE, BPF_INSN_SUBILE, BPF_INSN_SUBRLE, BPF_INSN_SUB32ILE
, BPF_INSN_SUB32RLE, BPF_INSN_MULILE, BPF_INSN_MULRLE, BPF_INSN_MUL32ILE
, BPF_INSN_MUL32RLE, BPF_INSN_DIVILE, BPF_INSN_DIVRLE, BPF_INSN_DIV32ILE
, BPF_INSN_DIV32RLE, BPF_INSN_ORILE, BPF_INSN_ORRLE, BPF_INSN_OR32ILE
, BPF_INSN_OR32RLE, BPF_INSN_ANDILE, BPF_INSN_ANDRLE, BPF_INSN_AND32ILE
, BPF_INSN_AND32RLE, BPF_INSN_LSHILE, BPF_INSN_LSHRLE, BPF_INSN_LSH32ILE
, BPF_INSN_LSH32RLE, BPF_INSN_RSHILE, BPF_INSN_RSHRLE, BPF_INSN_RSH32ILE
, BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
, BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
, BPF_INSN_XOR32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
, BPF_INSN_ARSH32RLE, BPF_INSN_SDIVILE, BPF_INSN_SDIVRLE, BPF_INSN_SDIV32ILE
, BPF_INSN_SDIV32RLE, BPF_INSN_SMODILE, BPF_INSN_SMODRLE, BPF_INSN_SMOD32ILE
, BPF_INSN_SMOD32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
, BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE, BPF_INSN_MOV32RLE, BPF_INSN_ADDIBE
, BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
, BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
, BPF_INSN_MULRBE, BPF_INSN_MUL32IBE, BPF_INSN_MUL32RBE, BPF_INSN_DIVIBE
, BPF_INSN_DIVRBE, BPF_INSN_DIV32IBE, BPF_INSN_DIV32RBE, BPF_INSN_ORIBE
, BPF_INSN_ORRBE, BPF_INSN_OR32IBE, BPF_INSN_OR32RBE, BPF_INSN_ANDIBE
, BPF_INSN_ANDRBE, BPF_INSN_AND32IBE, BPF_INSN_AND32RBE, BPF_INSN_LSHIBE
, BPF_INSN_LSHRBE, BPF_INSN_LSH32IBE, BPF_INSN_LSH32RBE, BPF_INSN_RSHIBE
, BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
, BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
, BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_ARSHIBE
, BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_SDIVIBE
, BPF_INSN_SDIVRBE, BPF_INSN_SDIV32IBE, BPF_INSN_SDIV32RBE, BPF_INSN_SMODIBE
, BPF_INSN_SMODRBE, BPF_INSN_SMOD32IBE, BPF_INSN_SMOD32RBE, BPF_INSN_NEGBE
, BPF_INSN_NEG32BE, BPF_INSN_MOVIBE, BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE
, BPF_INSN_MOV32RBE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
, BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW
, BPF_INSN_LDABSH, BPF_INSN_LDABSB, BPF_INSN_LDABSDW, BPF_INSN_LDINDWLE
, BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDINDWBE
, BPF_INSN_LDINDHBE, BPF_INSN_LDINDBBE, BPF_INSN_LDINDDWBE, BPF_INSN_LDXWLE
, BPF_INSN_LDXHLE, BPF_INSN_LDXBLE, BPF_INSN_LDXDWLE, BPF_INSN_STXWLE
, BPF_INSN_STXHLE, BPF_INSN_STXBLE, BPF_INSN_STXDWLE, BPF_INSN_LDXWBE
, BPF_INSN_LDXHBE, BPF_INSN_LDXBBE, BPF_INSN_LDXDWBE, BPF_INSN_STXWBE
, BPF_INSN_STXHBE, BPF_INSN_STXBBE, BPF_INSN_STXDWBE, BPF_INSN_STBLE
, BPF_INSN_STHLE, BPF_INSN_STWLE, BPF_INSN_STDWLE, BPF_INSN_STBBE
, BPF_INSN_STHBE, BPF_INSN_STWBE, BPF_INSN_STDWBE, BPF_INSN_JEQILE
, BPF_INSN_JEQRLE, BPF_INSN_JEQ32ILE, BPF_INSN_JEQ32RLE, BPF_INSN_JGTILE
, BPF_INSN_JGTRLE, BPF_INSN_JGT32ILE, BPF_INSN_JGT32RLE, BPF_INSN_JGEILE
, BPF_INSN_JGERLE, BPF_INSN_JGE32ILE, BPF_INSN_JGE32RLE, BPF_INSN_JLTILE
, BPF_INSN_JLTRLE, BPF_INSN_JLT32ILE, BPF_INSN_JLT32RLE, BPF_INSN_JLEILE
, BPF_INSN_JLERLE, BPF_INSN_JLE32ILE, BPF_INSN_JLE32RLE, BPF_INSN_JSETILE
, BPF_INSN_JSETRLE, BPF_INSN_JSET32ILE, BPF_INSN_JSET32RLE, BPF_INSN_JNEILE
, BPF_INSN_JNERLE, BPF_INSN_JNE32ILE, BPF_INSN_JNE32RLE, BPF_INSN_JSGTILE
, BPF_INSN_JSGTRLE, BPF_INSN_JSGT32ILE, BPF_INSN_JSGT32RLE, BPF_INSN_JSGEILE
, BPF_INSN_JSGERLE, BPF_INSN_JSGE32ILE, BPF_INSN_JSGE32RLE, BPF_INSN_JSLTILE
, BPF_INSN_JSLTRLE, BPF_INSN_JSLT32ILE, BPF_INSN_JSLT32RLE, BPF_INSN_JSLEILE
, BPF_INSN_JSLERLE, BPF_INSN_JSLE32ILE, BPF_INSN_JSLE32RLE, BPF_INSN_JEQIBE
, BPF_INSN_JEQRBE, BPF_INSN_JEQ32IBE, BPF_INSN_JEQ32RBE, BPF_INSN_JGTIBE
, BPF_INSN_JGTRBE, BPF_INSN_JGT32IBE, BPF_INSN_JGT32RBE, BPF_INSN_JGEIBE
, BPF_INSN_JGERBE, BPF_INSN_JGE32IBE, BPF_INSN_JGE32RBE, BPF_INSN_JLTIBE
, BPF_INSN_JLTRBE, BPF_INSN_JLT32IBE, BPF_INSN_JLT32RBE, BPF_INSN_JLEIBE
, BPF_INSN_JLERBE, BPF_INSN_JLE32IBE, BPF_INSN_JLE32RBE, BPF_INSN_JSETIBE
, BPF_INSN_JSETRBE, BPF_INSN_JSET32IBE, BPF_INSN_JSET32RBE, BPF_INSN_JNEIBE
, BPF_INSN_JNERBE, BPF_INSN_JNE32IBE, BPF_INSN_JNE32RBE, BPF_INSN_JSGTIBE
, BPF_INSN_JSGTRBE, BPF_INSN_JSGT32IBE, BPF_INSN_JSGT32RBE, BPF_INSN_JSGEIBE
, BPF_INSN_JSGERBE, BPF_INSN_JSGE32IBE, BPF_INSN_JSGE32RBE, BPF_INSN_JSLTIBE
, BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE
, BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_CALLLE
, BPF_INSN_CALLBE, BPF_INSN_CALLRLE, BPF_INSN_CALLRBE, BPF_INSN_JA
, BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE
, BPF_INSN_XADDWBE, BPF_INSN_BRKPT
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID BPF_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) BPF_INSN_BRKPT + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
{
int length;
long f_nil;
long f_anyof;
long f_op_code;
long f_op_src;
long f_op_class;
long f_op_mode;
long f_op_size;
long f_dstle;
long f_srcle;
long f_dstbe;
long f_srcbe;
long f_regs;
long f_offset16;
long f_imm32;
long f_imm64_a;
long f_imm64_b;
long f_imm64_c;
int64_t f_imm64;
};
#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}
#ifdef __cplusplus
}
#endif
#endif /* BPF_OPC_H */

2
opcodes/configure vendored
View File

@ -12597,7 +12597,7 @@ if test x${all_targets} = xfalse ; then
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
bfd_bpf_arch) ta="$ta bpf-dis.lo bpf-opc.lo" ;;
bfd_loongarch_arch) ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
"") ;;

2
opcodes/configure.ac
View File

@ -345,7 +345,7 @@ if test x${all_targets} = xfalse ; then
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
bfd_bpf_arch) ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
bfd_bpf_arch) ta="$ta bpf-dis.lo bpf-opc.lo" ;;
bfd_loongarch_arch) ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
"") ;;

Some files were not shown because too many files have changed in this diff Show More