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X86: Reuse opcode 0x80 decoder for opcode 0x82

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Since opcode 0x82 is an alias of opcode 0x80, we can reuse opcode 0x80
decoder.

	* i386-dis.c (REG_82): Removed.
	(X86_64_82_REG_0): Likewise.
	(X86_64_82_REG_1): Likewise.
	(X86_64_82_REG_2): Likewise.
	(X86_64_82_REG_3): Likewise.
	(X86_64_82_REG_4): Likewise.
	(X86_64_82_REG_5): Likewise.
	(X86_64_82_REG_6): Likewise.
	(X86_64_82_REG_7): Likewise.
	(X86_64_82): New.
	(dis386): Use X86_64_82 instead of REG_82.
	(reg_table): Remove REG_82.
	(x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
	X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
	X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
	X86_64_82_REG_7.
This commit is contained in:
H.J. Lu 2016-11-03 09:55:01 -07:00
parent 8b89fe14b5
commit d039fef395
2 changed files with 24 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
opcodes/ChangeLog
View File

@ -1,3 +1,22 @@
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (REG_82): Removed.
(X86_64_82_REG_0): Likewise.
(X86_64_82_REG_1): Likewise.
(X86_64_82_REG_2): Likewise.
(X86_64_82_REG_3): Likewise.
(X86_64_82_REG_4): Likewise.
(X86_64_82_REG_5): Likewise.
(X86_64_82_REG_6): Likewise.
(X86_64_82_REG_7): Likewise.
(X86_64_82): New.
(dis386): Use X86_64_82 instead of REG_82.
(reg_table): Remove REG_82.
(x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
X86_64_82_REG_7.
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20754

63
opcodes/i386-dis.c
View File

@ -706,7 +706,6 @@ enum
{
REG_80 = 0,
REG_81,
REG_82,
REG_83,
REG_8F,
REG_C0,
@ -1695,14 +1694,7 @@ enum
X86_64_63,
X86_64_6D,
X86_64_6F,
X86_64_82_REG_0,
X86_64_82_REG_1,
X86_64_82_REG_2,
X86_64_82_REG_3,
X86_64_82_REG_4,
X86_64_82_REG_5,
X86_64_82_REG_6,
X86_64_82_REG_7,
X86_64_82,
X86_64_9A,
X86_64_C4,
X86_64_C5,
@ -2671,7 +2663,7 @@ static const struct dis386 dis386[] = {
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
{ REG_TABLE (REG_82) },
{ X86_64_TABLE (X86_64_82) },
{ REG_TABLE (REG_83) },
{ "testB", { Eb, Gb }, 0 },
{ "testS", { Ev, Gv }, 0 },
@ -3409,17 +3401,6 @@ static const struct dis386 reg_table[][8] = {
{ "xorQ", { Evh1, Iv }, 0 },
{ "cmpQ", { Ev, Iv }, 0 },
},
/* REG_82 */
{
{ X86_64_TABLE (X86_64_82_REG_0) },
{ X86_64_TABLE (X86_64_82_REG_1) },
{ X86_64_TABLE (X86_64_82_REG_2) },
{ X86_64_TABLE (X86_64_82_REG_3) },
{ X86_64_TABLE (X86_64_82_REG_4) },
{ X86_64_TABLE (X86_64_82_REG_5) },
{ X86_64_TABLE (X86_64_82_REG_6) },
{ X86_64_TABLE (X86_64_82_REG_7) },
},
/* REG_83 */
{
{ "addQ", { Evh1, sIb }, 0 },
@ -6907,44 +6888,10 @@ static const struct dis386 x86_64_table[][2] = {
{ "outs{G|}", { indirDXr, Xz }, 0 },
},
/* X86_64_82_REG_0 */
/* X86_64_82 */
{
{ "addA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_1 */
{
{ "orA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_2 */
{
{ "adcA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_3 */
{
{ "sbbA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_4 */
{
{ "andA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_5 */
{
{ "subA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_6 */
{
{ "xorA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_7 */
{
{ "cmpA", { Eb, Ib }, 0 },
/* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
{ REG_TABLE (REG_80) },
},
/* X86_64_9A */