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gdb/
* xtensa-config.c (rmap): Remove entries for ar32 through ar63. Add threadptr, scompare1, mmid, epc5, epc6, epc7, eps5, eps6, eps7, excsave5, excsave6, excsave7, cpenable, and vecbase registers. (xtensa_submask0, xtensa_submask1, xtensa_submask2) (xtensa_submask3, xtensa_submask4, xtensa_submask5, xtensa_submask6) (xtensa_submask7, xtensa_submask8, xtensa_submask9, xtensa_submask10) (xtensa_submask11, xtensa_submask12, xtensa_submask13, xtensa_submask14) (xtensa_submask15): Adjust register numbers. * xtensa-xtregs.c (XTENSA_ELF_XTREG_SIZE): Change to 4. (xtensa_regmap_table): Add entry for scompare1. * regformats/reg-xtensa.dat: Remove ar32 through ar63. Add threadptr and scompare1. gdb/gdbserver/ * xtensa-xtregs.c (XTENSA_ELF_XTREG_SIZE): Change to 4. (xtensa_regmap_table): Add entry for scompare1.
This commit is contained in:
Bob Wilson
parent
33430bd0ae
commit
d0107bb6ae
@ -1,3 +1,18 @@
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2008-11-19 Bob Wilson <bob.wilson@acm.org>
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* xtensa-config.c (rmap): Remove entries for ar32 through ar63. Add
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threadptr, scompare1, mmid, epc5, epc6, epc7, eps5, eps6, eps7,
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excsave5, excsave6, excsave7, cpenable, and vecbase registers.
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(xtensa_submask0, xtensa_submask1, xtensa_submask2)
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(xtensa_submask3, xtensa_submask4, xtensa_submask5, xtensa_submask6)
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(xtensa_submask7, xtensa_submask8, xtensa_submask9, xtensa_submask10)
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(xtensa_submask11, xtensa_submask12, xtensa_submask13, xtensa_submask14)
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(xtensa_submask15): Adjust register numbers.
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* xtensa-xtregs.c (XTENSA_ELF_XTREG_SIZE): Change to 4.
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(xtensa_regmap_table): Add entry for scompare1.
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* regformats/reg-xtensa.dat: Remove ar32 through ar63. Add threadptr
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and scompare1.
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2008-11-19 Pedro Alves <pedro@codesourcery.com>
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* remote.c (escape_buffer): New.
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@ -1,3 +1,8 @@
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2008-11-19 Bob Wilson <bob.wilson@acm.org>
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* xtensa-xtregs.c (XTENSA_ELF_XTREG_SIZE): Change to 4.
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(xtensa_regmap_table): Add entry for scompare1.
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2008-11-18 Thiago Jung Bauermann <bauerman@br.ibm.com>
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* Makefile.in (powerpc-isa205-32l.o, powerpc-isa205-32l.c,
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@ -28,10 +28,11 @@ typedef struct {
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char* name
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;} xtensa_regtable_t;
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#define XTENSA_ELF_XTREG_SIZE 0
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#define XTENSA_ELF_XTREG_SIZE 4
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const xtensa_regtable_t xtensa_regmap_table[] = {
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/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
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{ 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
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{ 0 }
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};
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@ -33,38 +33,6 @@ expedite:pc,windowbase,windowstart
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32:ar29
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32:ar30
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32:ar31
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32:ar32
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32:ar33
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32:ar34
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32:ar35
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32:ar36
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32:ar37
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32:ar38
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32:ar39
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32:ar40
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32:ar41
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32:ar42
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32:ar43
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32:ar44
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32:ar45
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32:ar46
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32:ar47
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32:ar48
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32:ar49
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32:ar50
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32:ar51
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32:ar52
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32:ar53
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32:ar54
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32:ar55
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32:ar56
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32:ar57
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32:ar58
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32:ar59
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32:ar60
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32:ar61
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32:ar62
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32:ar63
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32:lbeg
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32:lend
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32:lcount
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@ -75,3 +43,5 @@ expedite:pc,windowbase,windowstart
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32:sr176
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32:sr208
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32:ps
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32:threadptr
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32:scompare1
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@ -25,37 +25,37 @@
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/* Masked registers. */
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xtensa_reg_mask_t xtensa_submask0[] = { { 74, 0, 4 } };
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xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
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const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
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xtensa_reg_mask_t xtensa_submask1[] = { { 74, 5, 1 } };
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xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
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const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
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xtensa_reg_mask_t xtensa_submask2[] = { { 74, 18, 1 } };
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xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
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const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
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xtensa_reg_mask_t xtensa_submask3[] = { { 74, 6, 2 } };
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xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
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const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
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xtensa_reg_mask_t xtensa_submask4[] = { { 74, 4, 1 } };
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xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
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const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
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xtensa_reg_mask_t xtensa_submask5[] = { { 74, 16, 2 } };
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xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
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const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
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xtensa_reg_mask_t xtensa_submask6[] = { { 74, 8, 4 } };
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xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
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const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
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xtensa_reg_mask_t xtensa_submask7[] = { { 69, 12, 20 } };
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xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
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const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
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xtensa_reg_mask_t xtensa_submask8[] = { { 69, 0, 1 } };
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xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
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const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
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xtensa_reg_mask_t xtensa_submask9[] = { { 104, 8, 4 } };
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xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
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const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
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xtensa_reg_mask_t xtensa_submask10[] = { { 76, 24, 8 } };
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xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
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const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
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xtensa_reg_mask_t xtensa_submask11[] = { { 76, 16, 8 } };
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xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
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const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
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xtensa_reg_mask_t xtensa_submask12[] = { { 76, 8, 8 } };
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xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
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const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
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xtensa_reg_mask_t xtensa_submask13[] = { { 77, 16, 2 } };
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xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
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const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
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xtensa_reg_mask_t xtensa_submask14[] = { { 78, 16, 2 } };
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xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
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const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
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xtensa_reg_mask_t xtensa_submask15[] = { { 75, 22, 10 } };
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xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
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const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
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@ -96,135 +96,117 @@ xtensa_register_t rmap[] =
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XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
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XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
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XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
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XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32, 0,0,0,0,0,0)
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XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33, 0,0,0,0,0,0)
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XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34, 0,0,0,0,0,0)
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XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35, 0,0,0,0,0,0)
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XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36, 0,0,0,0,0,0)
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XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37, 0,0,0,0,0,0)
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XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38, 0,0,0,0,0,0)
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XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39, 0,0,0,0,0,0)
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XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40, 0,0,0,0,0,0)
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XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41, 0,0,0,0,0,0)
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XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42, 0,0,0,0,0,0)
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XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43, 0,0,0,0,0,0)
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XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44, 0,0,0,0,0,0)
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XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45, 0,0,0,0,0,0)
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XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46, 0,0,0,0,0,0)
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XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47, 0,0,0,0,0,0)
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XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48, 0,0,0,0,0,0)
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XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49, 0,0,0,0,0,0)
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XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50, 0,0,0,0,0,0)
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XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51, 0,0,0,0,0,0)
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XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52, 0,0,0,0,0,0)
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XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53, 0,0,0,0,0,0)
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XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54, 0,0,0,0,0,0)
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XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55, 0,0,0,0,0,0)
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XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56, 0,0,0,0,0,0)
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XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57, 0,0,0,0,0,0)
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XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58, 0,0,0,0,0,0)
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XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59, 0,0,0,0,0,0)
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XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60, 0,0,0,0,0,0)
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XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61, 0,0,0,0,0,0)
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XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62, 0,0,0,0,0,0)
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XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63, 0,0,0,0,0,0)
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XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
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XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
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XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
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XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
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XTREG( 69,276,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
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XTREG( 70,280, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
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XTREG( 71,284,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
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XTREG( 72,288,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
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XTREG( 73,292,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
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XTREG( 74,296,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
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XTREG( 75,300,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
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XTREG( 76,304,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
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XTREG( 77,308,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
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XTREG( 78,312,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
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XTREG( 79,316, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
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XTREG( 80,320,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
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XTREG( 81,324,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
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XTREG( 82,328,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
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XTREG( 83,332,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
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XTREG( 84,336,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
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XTREG( 85,340,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
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XTREG( 86,344,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
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XTREG( 87,348,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
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XTREG( 88,352,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
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XTREG( 89,356,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
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XTREG( 90,360,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
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XTREG( 91,364,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
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XTREG( 92,368,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
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XTREG( 93,372,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
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XTREG( 94,376,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
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XTREG( 95,380,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
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XTREG( 96,384,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
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XTREG( 97,388,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
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XTREG( 98,392,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
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XTREG( 99,396,17, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
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XTREG(100,400,17, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
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XTREG(101,404,17, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
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XTREG(102,408,17, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
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XTREG(103,412, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
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XTREG(104,416,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
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XTREG(105,420,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
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XTREG(106,424,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
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XTREG(107,428,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
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XTREG(108,432, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
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XTREG(109,436,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(110,440,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(111,444,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(112,448,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(113,452,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(114,456,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(115,460,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG(116,464,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG(117,468,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(118,472,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(119,476,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(120,480,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(121,484,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(122,488,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(123,492,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(124,496,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(125,500,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(126,504,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(127,508,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(128,512,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(129,516,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(130,520,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(131,524, 4, 4, 4,0x2004,0x0006,-2, 6,0x1010,psintlevel,
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 50,200, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 57,228,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 58,232,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 68,272,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 69,276,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 70,280,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG( 77,308,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG( 78,312,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG( 79,316, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG( 80,320,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG( 81,324,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG( 82,328,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG( 83,332,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG( 84,336,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG( 85,340, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG( 86,344,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG( 87,348,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG( 88,352,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG( 89,356,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG( 90,360, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG( 91,364,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG( 93,372,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG( 94,376,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG( 96,384,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG( 98,392,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG( 99,396,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(100,400,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(101,404,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(102,408,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(103,412,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(104,416,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(105,420,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(106,424,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(107,428,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(108,432,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(109,436,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(110,440,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(111,444,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(112,448,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(113,452, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(132,528, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,psum,
|
||||
XTREG(114,456, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(133,532, 1, 4, 4,0x2006,0x0006,-2, 6,0x1010,pswoe,
|
||||
XTREG(115,460, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(134,536, 2, 4, 4,0x2007,0x0006,-2, 6,0x1010,psring,
|
||||
XTREG(116,464, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(135,540, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,psexcm,
|
||||
XTREG(117,468, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(136,544, 2, 4, 4,0x2009,0x0006,-2, 6,0x1010,pscallinc,
|
||||
XTREG(118,472, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(137,548, 4, 4, 4,0x200a,0x0006,-2, 6,0x1010,psowb,
|
||||
XTREG(119,476, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(138,552,20, 4, 4,0x200b,0x0006,-2, 6,0x1010,litbaddr,
|
||||
XTREG(120,480,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(139,556, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,litben,
|
||||
XTREG(121,484, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(140,560, 4, 4, 4,0x2011,0x0006,-2, 6,0x1010,dbnum,
|
||||
XTREG(122,488, 4, 4, 4,0x2015,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(141,564, 8, 4, 4,0x2012,0x0006,-2, 6,0x1010,asid3,
|
||||
XTREG(123,492, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(142,568, 8, 4, 4,0x2013,0x0006,-2, 6,0x1010,asid2,
|
||||
XTREG(124,496, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(143,572, 8, 4, 4,0x2014,0x0006,-2, 6,0x1010,asid1,
|
||||
XTREG(125,500, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(144,576, 2, 4, 4,0x2015,0x0006,-2, 6,0x1010,instpgszid4,
|
||||
XTREG(126,504, 2, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid4,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(145,580, 2, 4, 4,0x2016,0x0006,-2, 6,0x1010,datapgszid4,
|
||||
XTREG(127,508, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,datapgszid4,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(146,584,10, 4, 4,0x2017,0x0006,-2, 6,0x1010,ptbase,
|
||||
XTREG(128,512,10, 4, 4,0x201b,0x0006,-2, 6,0x1010,ptbase,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG_END
|
||||
};
|
||||
|
||||
@ -28,10 +28,11 @@ typedef struct {
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 0
|
||||
#define XTENSA_ELF_XTREG_SIZE 4
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 0, 0, 4, -1, 0x020c, "scompare1" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user