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aarch64: Add new data cache maintenance operations

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This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in
conjunction with DC instruction. This change is part of RME (Realm Management
Extension).

gas/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* testsuite/gas/aarch64/rme.d: Update test.
	* testsuite/gas/aarch64/rme.s: Update test.

opcodes/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
	DC instruction.
This commit is contained in:
Przemyslaw Wirkus 2021-04-19 14:54:46 +01:00
parent fe1640ff8e
commit cd6608e49d
5 changed files with 18 additions and 0 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme.d: Update test.
* testsuite/gas/aarch64/rme.s: Update test.
2021-04-19 Jan Beulich <jbeulich@suse.com>
* as.h (sprint_value): Delete.

2
gas/testsuite/gas/aarch64/rme.d
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@ -12,3 +12,5 @@ Disassembly of section \.text:
8: d53e2180 mrs x0, gptbr_el3
c: d51e21c0 msr gpccr_el3, x0
10: d51e2180 msr gptbr_el3, x0
14: d50e7e20 dc cipapa, x0
18: d50e7ea0 dc cigdpapa, x0

4
gas/testsuite/gas/aarch64/rme.s
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@ -8,3 +8,7 @@ mrs x0, gptbr_el3
/* Write to RME system registers. */
msr gpccr_el3, x0
msr gptbr_el3, x0
/* RME data cache maintenance operations. */
dc cipapa, x0
dc cigdpapa, x0

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
DC instruction.
2021-04-19 Jan Beulich <jbeulich@suse.com>
* aarch64-asm.c (encode_asimd_fcvt): Add initializer for

2
opcodes/aarch64-opc.c
View File

@ -4763,6 +4763,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
{ "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
{ "cipapa", CPENS (6, C7, C14, 1), F_HASXT },
{ "cigdpapa", CPENS (6, C7, C14, 5), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
};