mirrors/binutils-gdb
1
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2024-11-24 02:24:46 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

2007-06-26 Paul Brook <paul@codesourcery.com>

Browse Source 
gas/
	* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
	for OP_RVC.
	(reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1.

	gas/testsuite/
	* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.
	* gas/arm/vfp1xD.s: Ditto.
	* gas/arm/vfp1xD_t2.d: Ditto.
	* gas/arm/vfp1xD_t2.s: Ditto.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1.
This commit is contained in:
Paul Brook 2007-06-26 21:36:37 +00:00
parent 86f78eb20c
commit cd2cf30b7d
9 changed files with 90 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2007-06-26 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
for OP_RVC.
(reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1.
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Replace regKludge

12
gas/config/tc-arm.c
View File

@ -5612,7 +5612,13 @@ parse_operands (char *str, const unsigned char *pattern)
case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
case OP_oRND:
case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
case OP_RVC:
po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
break;
/* Also accept generic coprocessor regs for unknown registers. */
coproc_reg:
po_reg_or_fail (REG_TYPE_CN);
break;
case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
@ -14506,6 +14512,10 @@ static const struct reg_entry reg_names[] =
/* VFP control registers. */
REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
/* Maverick DSP coprocessor registers. */
REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2007-06-26 Paul Brook <paul@codesourcery.com>
* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.
* gas/arm/vfp1xD.s: Ditto.
* gas/arm/vfp1xD_t2.d: Ditto.
* gas/arm/vfp1xD_t2.s: Ditto.
2007-06-24 Nick Clifton <nickc@redhat.com>
* gas/arm/backslash-at.d: Fix for non-ELF arm targets.

12
gas/testsuite/gas/arm/vfp1xD.d
View File

@ -239,3 +239,15 @@ Disassembly of section .text:
0+394 <[^>]*> 0ef09a10 fmrxeq r9, fpsid
0+398 <[^>]*> 0e019a90 fmsreq s3, r9
0+39c <[^>]*> 0ee08a10 fmxreq fpsid, r8
0+3a0 <[^>]*> eef90a10 fmrx r0, fpinst @ Impl def
0+3a4 <[^>]*> eefa0a10 fmrx r0, fpinst2 @ Impl def
0+3a8 <[^>]*> eef70a10 fmrx r0, mvfr0
0+3ac <[^>]*> eef60a10 fmrx r0, mvfr1
0+3b0 <[^>]*> eefc0a10 fmrx r0, <impl def 0xc>
0+3b4 <[^>]*> eee90a10 fmxr fpinst, r0 @ Impl def
0+3b8 <[^>]*> eeea0a10 fmxr fpinst2, r0 @ Impl def
0+3bc <[^>]*> eee70a10 fmxr mvfr0, r0
0+3c0 <[^>]*> eee60a10 fmxr mvfr1, r0
0+3c4 <[^>]*> eeec0a10 fmxr <impl def 0xc>, r0
0+3c8 <[^>]*> e1a00000 nop \(mov r0,r0\)
0+3cc <[^>]*> e1a00000 nop \(mov r0,r0\)

14
gas/testsuite/gas/arm/vfp1xD.s
View File

@ -337,3 +337,17 @@ F:
fmsreq s3, r9
fmxreq fpsid, r8
@ Implementation specific system registers
fmrx r0, fpinst
fmrx r0, fpinst2
fmrx r0, mvfr0
fmrx r0, mvfr1
fmrx r0, c12
fmxr fpinst, r0
fmxr fpinst2, r0
fmxr mvfr0, r0
fmxr mvfr1, r0
fmxr c12, r0
nop
nop

18
gas/testsuite/gas/arm/vfp1xD_t2.d
View File

@ -253,5 +253,19 @@ Disassembly of section .text:
0+3b2 <[^>]*> bf04 itt eq
0+3b4 <[^>]*> ee01 9a90 fmsreq s3, r9
0+3b8 <[^>]*> eee0 8a10 fmxreq fpsid, r8
0+3bc <[^>]*> bf00 nop
0+3be <[^>]*> bf00 nop
0+3bc <[^>]*> eef9 0a10 fmrx r0, fpinst @ Impl def
0+3c0 <[^>]*> eefa 0a10 fmrx r0, fpinst2 @ Impl def
0+3c4 <[^>]*> eef7 0a10 fmrx r0, mvfr0
0+3c8 <[^>]*> eef6 0a10 fmrx r0, mvfr1
0+3cc <[^>]*> eefc 0a10 fmrx r0, <impl def 0xc>
0+3d0 <[^>]*> eee9 0a10 fmxr fpinst, r0 @ Impl def
0+3d4 <[^>]*> eeea 0a10 fmxr fpinst2, r0 @ Impl def
0+3d8 <[^>]*> eee7 0a10 fmxr mvfr0, r0
0+3dc <[^>]*> eee6 0a10 fmxr mvfr1, r0
0+3e0 <[^>]*> eeec 0a10 fmxr <impl def 0xc>, r0
0+3e4 <[^>]*> bf00 nop
0+3e6 <[^>]*> bf00 nop
0+3e8 <[^>]*> bf00 nop
0+3ea <[^>]*> bf00 nop
0+3ec <[^>]*> bf00 nop
0+3ee <[^>]*> bf00 nop

17
gas/testsuite/gas/arm/vfp1xD_t2.s
View File

@ -354,6 +354,21 @@ F:
fmsreq s3, r9
fmxreq fpsid, r8
@ 2 nops to pad to 16-byte boundary
@ Implementation specific system registers
fmrx r0, fpinst
fmrx r0, fpinst2
fmrx r0, mvfr0
fmrx r0, mvfr1
fmrx r0, c12
fmxr fpinst, r0
fmxr fpinst2, r0
fmxr mvfr0, r0
fmxr mvfr1, r0
fmxr c12, r0
nop
nop
nop
nop
nop
nop

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2007-06-26 Paul Brook <paul@codesourcery.com>
* arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1.
2007-06-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (regKludge): Renamed to ...

4
opcodes/arm-dis.c
View File

@ -268,11 +268,15 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
{FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
{FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
{FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
{FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"},
{FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"},
{FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
{FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
{FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},