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opcodes/

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2007-10-04  David Daney  <ddaney@avtrex.com>

	* mips-opc.c (mips_builtin_opcodes): Mark lwxc1 as working on FP_S
	registers.

gas/testsuite/
2007-10-04  David Daney  <ddaney@avtrex.com>

	* gas/mips/odd-float.d, gas/mips/odd-float.s: New test.
	* gas/mips/mips.exp: Run it.
This commit is contained in:
David Daney 2007-10-04 21:53:06 +00:00
parent df26e7af07
commit c8ab98e0eb
6 changed files with 28 additions and 1 deletions
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5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2007-10-04 David Daney <ddaney@avtrex.com>
* gas/mips/odd-float.d, gas/mips/odd-float.s: New test.
* gas/mips/mips.exp: Run it.
2007-10-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5109

1
gas/testsuite/gas/mips/mips.exp
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@ -775,4 +775,5 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "noreorder"
run_dump_test "align"
run_dump_test "odd-float"
}

10
gas/testsuite/gas/mips/odd-float.d Normal file
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@ -0,0 +1,10 @@
#objdump: -dr --prefix-addresses
#name: MIPS odd float
#as: -32 -march=sb1 -EL --fatal-warnings
.*: +file format .*mips.*
Disassembly of section .text:
0+00 <[^>]*> lwxc1 \$f1,a0\(a1\)
0+04 <[^>]*> swxc1 \$f3,a0\(a1\)
...

6
gas/testsuite/gas/mips/odd-float.s Normal file
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@ -0,0 +1,6 @@
# Source file used to test operations on odd numbered floating point
# registers.
text_label:
lwxc1 $f1,$4($5)
swxc1 $f3,$4($5)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2007-10-04 David Daney <ddaney@avtrex.com>
* mips-opc.c (mips_builtin_opcodes): Mark lwxc1 as working on FP_S
registers.
2007-10-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOD_0F12_PREFIX_0): Use "movlps" and "movhlps"

2
opcodes/mips-opc.c
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@ -744,7 +744,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, 0, I4|I33 },
{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },