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[AArch64][PATCH 1/2] Add support for RAS instruction ESB.

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The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: New.
	* gas/aarch64/system-2.s: New.
	* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_RAS): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_feature_ras): New.
	(RAS): New.
	(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
This commit is contained in:
Matthew Wahab 2015-12-10 14:05:01 +00:00
parent af117b3cf1
commit c8a6db6fa0
10 changed files with 68 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run ospke and x86-64-ospke.

10
gas/testsuite/gas/aarch64/system-2.d Normal file
View File

@ -0,0 +1,10 @@
#as: -march=armv8.2-a
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: d503221f esb
4: d503221f esb

6
gas/testsuite/gas/aarch64/system-2.s Normal file
View File

@ -0,0 +1,6 @@
/* ARMv8.1 System instructions. */
.text
/* RAS Extension. */
esb
hint #0x10

2
gas/testsuite/gas/aarch64/system.d
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@ -28,7 +28,7 @@ Disassembly of section \.text:
50: d50321bf hint #0xd
54: d50321df hint #0xe
58: d50321ff hint #0xf
5c: d503221f hint #0x10
5c: d503221f (hint #0x10|esb)
60: d503223f hint #0x11
64: d503225f hint #0x12
68: d503227f hint #0x13

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): Fix clash with

2
include/opcode/aarch64.h
View File

@ -49,6 +49,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@ -66,6 +67,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_V8_2 \
| AARCH64_FEATURE_F16 \
| AARCH64_FEATURE_RAS \
| AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD \
| AARCH64_FEATURE_CRC \

8
opcodes/ChangeLog
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@ -1,3 +1,11 @@
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".
2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOD_0F01_REG_5): New.

13
opcodes/aarch64-asm-2.c
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@ -422,6 +422,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1004: /* movz */
value = 1004; /* --> movz. */
break;
case 1017: /* esb */
case 1016: /* sevl */
case 1015: /* sev */
case 1014: /* wfi */
@ -431,12 +432,12 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1010: /* hint */
value = 1010; /* --> hint. */
break;
case 1025: /* tlbi */
case 1024: /* ic */
case 1023: /* dc */
case 1022: /* at */
case 1021: /* sys */
value = 1021; /* --> sys. */
case 1026: /* tlbi */
case 1025: /* ic */
case 1024: /* dc */
case 1023: /* at */
case 1022: /* sys */
value = 1022; /* --> sys. */
break;
default: return NULL;
}

37
opcodes/aarch64-dis-2.c
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@ -3319,7 +3319,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxx1xx1x10x01x
sysl. */
return 1027;
return 1028;
}
}
}
@ -3342,7 +3342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx0110x1xx
tbz. */
return 1029;
return 1030;
}
}
else
@ -3361,7 +3361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxxxxxxxxxxxxxxxxxxxxxx1110x1xx
tbnz. */
return 1030;
return 1031;
}
}
}
@ -8857,15 +8857,15 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 794: value = 798; break; /* ldnp --> ldp. */
case 798: return NULL; /* ldp --> NULL. */
case 1009: value = 1010; break; /* msr --> hint. */
case 1010: value = 1017; break; /* hint --> clrex. */
case 1017: value = 1018; break; /* clrex --> dsb. */
case 1018: value = 1019; break; /* dsb --> dmb. */
case 1019: value = 1020; break; /* dmb --> isb. */
case 1020: value = 1021; break; /* isb --> sys. */
case 1021: value = 1026; break; /* sys --> msr. */
case 1026: return NULL; /* msr --> NULL. */
case 1027: value = 1028; break; /* sysl --> mrs. */
case 1028: return NULL; /* mrs --> NULL. */
case 1010: value = 1018; break; /* hint --> clrex. */
case 1018: value = 1019; break; /* clrex --> dsb. */
case 1019: value = 1020; break; /* dsb --> dmb. */
case 1020: value = 1021; break; /* dmb --> isb. */
case 1021: value = 1022; break; /* isb --> sys. */
case 1022: value = 1027; break; /* sys --> msr. */
case 1027: return NULL; /* msr --> NULL. */
case 1028: value = 1029; break; /* sysl --> mrs. */
case 1029: return NULL; /* mrs --> NULL. */
case 361: value = 362; break; /* st4 --> st1. */
case 362: value = 363; break; /* st1 --> st2. */
case 363: value = 364; break; /* st2 --> st3. */
@ -9145,8 +9145,8 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode)
case 952: value = 1001; break; /* lduminl --> stuminl. */
case 1002: value = 1003; break; /* movn --> mov. */
case 1004: value = 1005; break; /* movz --> mov. */
case 1010: value = 1016; break; /* hint --> sevl. */
case 1021: value = 1025; break; /* sys --> tlbi. */
case 1010: value = 1017; break; /* hint --> esb. */
case 1022: value = 1026; break; /* sys --> tlbi. */
default: return NULL;
}
@ -9271,16 +9271,17 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
case 1001: value = 952; break; /* stuminl --> lduminl. */
case 1003: value = 1002; break; /* mov --> movn. */
case 1005: value = 1004; break; /* mov --> movz. */
case 1017: value = 1016; break; /* esb --> sevl. */
case 1016: value = 1015; break; /* sevl --> sev. */
case 1015: value = 1014; break; /* sev --> wfi. */
case 1014: value = 1013; break; /* wfi --> wfe. */
case 1013: value = 1012; break; /* wfe --> yield. */
case 1012: value = 1011; break; /* yield --> nop. */
case 1011: value = 1010; break; /* nop --> hint. */
case 1025: value = 1024; break; /* tlbi --> ic. */
case 1024: value = 1023; break; /* ic --> dc. */
case 1023: value = 1022; break; /* dc --> at. */
case 1022: value = 1021; break; /* at --> sys. */
case 1026: value = 1025; break; /* tlbi --> ic. */
case 1025: value = 1024; break; /* ic --> dc. */
case 1024: value = 1023; break; /* dc --> at. */
case 1023: value = 1022; break; /* at --> sys. */
default: return NULL;
}

4
opcodes/aarch64-tbl.h
View File

@ -1297,6 +1297,8 @@ static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
static const aarch64_feature_set aarch64_feature_rdma =
AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
static const aarch64_feature_set aarch64_feature_ras =
AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
static const aarch64_feature_set aarch64_feature_fp_f16 =
@ -1311,6 +1313,7 @@ static const aarch64_feature_set aarch64_feature_fp_f16 =
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
#define RAS &aarch64_feature_ras
#define ARMV8_2 &aarch64_feature_v8_2
struct aarch64_opcode aarch64_opcode_table[] =
@ -2456,6 +2459,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
{"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
{"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
{"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},