mirror of
https://sourceware.org/git/binutils-gdb.git
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* gas/config/tc-arm.c (el_type_type_check): Add handling for 16-bit
floating point types. (do_neon_cvttb_2): New function. (do_neon_cvttb_1): Likewise. (do_neon_cvtb): Refactor to use do_neon_cvttb_1. (do_neon_cvtt): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * gas/testsuite/gas/arm/half-prec-vfpv3.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add support for HP/DP conversions.
This commit is contained in:
Matthew Gretton-Dann
parent
30bdf75259
commit
c70a898785
@ -1,3 +1,12 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (el_type_type_check): Add handling for 16-bit
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floating point types.
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(do_neon_cvttb_2): New function.
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(do_neon_cvttb_1): Likewise.
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(do_neon_cvtb): Refactor to use do_neon_cvttb_1.
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(do_neon_cvtt): Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
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@ -12832,7 +12832,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
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if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
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*size = 8;
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else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
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else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
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*size = 16;
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else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
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*size = 32;
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@ -12851,7 +12851,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
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*type = NT_untyped;
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else if ((mask & (N_P8 | N_P16)) != 0)
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*type = NT_poly;
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else if ((mask & (N_F32 | N_F64)) != 0)
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else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
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*type = NT_float;
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else
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return FAIL;
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@ -14887,32 +14887,64 @@ do_neon_cvtm (void)
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do_neon_cvt_1 (neon_cvt_mode_m);
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}
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static void
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do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
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{
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if (is_double)
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mark_feature_used (&fpu_vfp_ext_armv8);
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encode_arm_vfp_reg (inst.operands[0].reg,
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(is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
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encode_arm_vfp_reg (inst.operands[1].reg,
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(is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
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inst.instruction |= to ? 0x10000 : 0;
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inst.instruction |= t ? 0x80 : 0;
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inst.instruction |= is_double ? 0x100 : 0;
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do_vfp_cond_or_thumb ();
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}
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static void
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do_neon_cvttb_1 (bfd_boolean t)
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{
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enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
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if (rs == NS_NULL)
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return;
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else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
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{
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inst.error = NULL;
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do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
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}
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else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
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{
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inst.error = NULL;
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do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
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}
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else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
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{
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inst.error = NULL;
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do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
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}
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else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
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{
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inst.error = NULL;
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do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
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}
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else
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return;
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}
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static void
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do_neon_cvtb (void)
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{
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inst.instruction = 0xeb20a40;
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/* The sizes are attached to the mnemonic. */
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if (inst.vectype.el[0].type != NT_invtype
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&& inst.vectype.el[0].size == 16)
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inst.instruction |= 0x00010000;
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/* Programmer's syntax: the sizes are attached to the operands. */
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else if (inst.operands[0].vectype.type != NT_invtype
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&& inst.operands[0].vectype.size == 16)
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inst.instruction |= 0x00010000;
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encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
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encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
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do_vfp_cond_or_thumb ();
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do_neon_cvttb_1 (FALSE);
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}
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static void
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do_neon_cvtt (void)
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{
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do_neon_cvtb ();
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inst.instruction |= 0x80;
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do_neon_cvttb_1 (TRUE);
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}
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static void
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@ -18958,8 +18990,8 @@ static const struct asm_opcode insns[] =
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nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
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nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
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nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
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nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
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NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
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NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
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/* NOTE: All VMOV encoding is special-cased! */
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@ -1,3 +1,9 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a+fp.d: Update testcase.
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* gas/arm/armv8-a+fp.s: Likewise.
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* gas/arm/half-prec-vfpv3.s: Likewise.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv8-a+fpv5.d: Update testcase.
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@ -50,6 +50,14 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64.f64 d1, d1
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0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64.f64 d30, d30
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0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64.f64 d31, d31
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0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
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0[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16
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0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15
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0[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31
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0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
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0[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1
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0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30
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0[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31
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0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
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0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
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0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
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@ -96,3 +104,11 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64.f64 d1, d1
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0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64.f64 d30, d30
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0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64.f64 d31, d31
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0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0
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0[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16
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0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15
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0[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31
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0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0
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0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1
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0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
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0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31
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@ -50,6 +50,14 @@
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vrintn.f64.f64 d1, d1
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vrintp.f64.f64 d30, d30
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vrintm.f64.f64 d31, d31
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vcvtt.f16.f64 s0, d0
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vcvtb.f16.f64 s1, d16
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vcvtt.f16.f64 s30, d15
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vcvtb.f16.f64 s31, d31
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vcvtt.f64.f16 d0, s0
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vcvtb.f64.f16 d16, s1
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vcvtt.f64.f16 d15, s30
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vcvtb.f64.f16 d31, s31
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.thumb
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vseleq.f32 s0, s0, s0
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@ -98,3 +106,11 @@
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vrintn.f64.f64 d1, d1
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vrintp.f64.f64 d30, d30
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vrintm.f64.f64 d31, d31
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vcvtt.f16.f64 s0, d0
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vcvtb.f16.f64 s1, d16
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vcvtt.f16.f64 s30, d15
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vcvtb.f16.f64 s31, d31
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vcvtt.f64.f16 d0, s0
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vcvtb.f64.f16 d16, s1
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vcvtt.f64.f16 d15, s30
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vcvtb.f64.f16 d31, s31
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@ -1,20 +1,20 @@
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.text
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vcvtt.f32.f32 s0, s1
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vcvtteq.f32.f32 s2, s3
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vcvttne.f32.f32 s2, s3
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vcvttcs.f32.f32 s2, s3
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vcvttcc.f32.f32 s2, s3
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vcvttmi.f32.f32 s2, s3
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vcvttpl.f32.f32 s2, s3
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vcvttvs.f32.f32 s2, s3
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vcvttvc.f32.f32 s2, s3
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vcvtthi.f32.f32 s2, s3
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vcvttls.f32.f32 s2, s3
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vcvttge.f32.f32 s2, s3
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vcvttlt.f32.f32 s2, s3
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vcvttgt.f32.f32 s2, s3
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vcvttle.f32.f32 s2, s3
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vcvttal.f32.f32 s2, s3
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vcvtt.f32.f16 s0, s1
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vcvtteq.f32.f16 s2, s3
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vcvttne.f32.f16 s2, s3
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vcvttcs.f32.f16 s2, s3
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vcvttcc.f32.f16 s2, s3
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vcvttmi.f32.f16 s2, s3
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vcvttpl.f32.f16 s2, s3
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vcvttvs.f32.f16 s2, s3
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vcvttvc.f32.f16 s2, s3
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vcvtthi.f32.f16 s2, s3
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vcvttls.f32.f16 s2, s3
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vcvttge.f32.f16 s2, s3
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vcvttlt.f32.f16 s2, s3
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vcvttgt.f32.f16 s2, s3
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vcvttle.f32.f16 s2, s3
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vcvttal.f32.f16 s2, s3
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vcvtt.f16.f32 s0, s1
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vcvtteq.f16.f32 s2, s3
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@ -33,22 +33,22 @@
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vcvttle.f16.f32 s2, s3
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vcvttal.f16.f32 s2, s3
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vcvtb.f32.f32 s0, s1
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vcvtbeq.f32.f32 s2, s3
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vcvtbne.f32.f32 s2, s3
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vcvtbcs.f32.f32 s2, s3
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vcvtbcc.f32.f32 s2, s3
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vcvtbmi.f32.f32 s2, s3
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vcvtbpl.f32.f32 s2, s3
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vcvtbvs.f32.f32 s2, s3
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vcvtbvc.f32.f32 s2, s3
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vcvtbhi.f32.f32 s2, s3
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vcvtbls.f32.f32 s2, s3
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vcvtbge.f32.f32 s2, s3
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vcvtblt.f32.f32 s2, s3
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vcvtbgt.f32.f32 s2, s3
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vcvtble.f32.f32 s2, s3
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vcvtbal.f32.f32 s2, s3
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vcvtb.f32.f16 s0, s1
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vcvtbeq.f32.f16 s2, s3
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vcvtbne.f32.f16 s2, s3
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vcvtbcs.f32.f16 s2, s3
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vcvtbcc.f32.f16 s2, s3
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vcvtbmi.f32.f16 s2, s3
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vcvtbpl.f32.f16 s2, s3
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vcvtbvs.f32.f16 s2, s3
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vcvtbvc.f32.f16 s2, s3
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vcvtbhi.f32.f16 s2, s3
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vcvtbls.f32.f16 s2, s3
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vcvtbge.f32.f16 s2, s3
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vcvtblt.f32.f16 s2, s3
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vcvtbgt.f32.f16 s2, s3
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vcvtble.f32.f16 s2, s3
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vcvtbal.f32.f16 s2, s3
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vcvtb.f16.f32 s0, s1
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vcvtbeq.f16.f32 s2, s3
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@ -1,3 +1,8 @@
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add support for HP/DP
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conversions.
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2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add VRINT.
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@ -319,6 +319,8 @@ static const struct opcode32 coprocessor_opcodes[] =
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{FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
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{FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
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/* Half-precision conversion instructions. */
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{FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
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{FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
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{FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
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{FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
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