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x86-64: don't accept supposedly disabled MOVQ forms
While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
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Jan Beulich
parent
574d27ede4
commit
c3344b626d
@ -1,3 +1,9 @@
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2021-03-26 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/x86-64-nosse2.s,
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testsuite/gas/i386/x86-64-nosse2.l: New.
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* testsuite/gas/i386/i386.exp: Run new test.
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2021-03-25 Abid Qadeer <abidh@codesourcery.com>
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* testsuite/gas/nios2/brn.d: New.
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@ -826,6 +826,7 @@ if [gas_64_check] then {
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run_list_test "noreg-intel64" "-I${srcdir}/$subdir -mintel64"
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run_list_test "movx64" "-al"
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run_list_test "cvtsi2sX"
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run_list_test "x86-64-nosse2" "-al"
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run_dump_test "x86-64-sse4_1"
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run_dump_test "x86-64-sse4_1-intel"
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run_dump_test "x86-64-sse4_2"
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15
gas/testsuite/gas/i386/x86-64-nosse2.l
Normal file
15
gas/testsuite/gas/i386/x86-64-nosse2.l
Normal file
@ -0,0 +1,15 @@
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.*: Assembler messages:
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.*:6: Error: .*paddb.*
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.*:7: Error: .*movq.*
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.*:8: Error: .*movq.*
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GAS LISTING .*
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#...
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[ ]*1[ ]+\# Test \.arch \.nosse2
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[ ]*2[ ]+\.text
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[ ]*3[ ]+\.arch generic64
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[ ]*4[ ]+\.arch \.nosse2
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[ ]*5[ ]+\?\?\?\? 0F58C0 addps %xmm0, %xmm0
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[ ]*6[ ]+paddb %xmm0, %xmm0
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[ ]*7[ ]+movq %xmm0, %rax
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[ ]*8[ ]+movq %rax, %xmm0
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#pass
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9
gas/testsuite/gas/i386/x86-64-nosse2.s
Normal file
9
gas/testsuite/gas/i386/x86-64-nosse2.s
Normal file
@ -0,0 +1,9 @@
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# Test .arch .nosse2
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.text
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.arch generic64
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.arch .nosse2
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addps %xmm0, %xmm0
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paddb %xmm0, %xmm0
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movq %xmm0, %rax
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movq %rax, %xmm0
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.p2align 4
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@ -1,3 +1,9 @@
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2021-03-26 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
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MMX form.
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* i386-tbl.h: Re-generate.
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2021-03-25 Abid Qadeer <abidh@codesourcery.com>
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* nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
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@ -972,9 +972,9 @@ movq, 0x66d6, None, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf|N
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movq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
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movq, 0x0f7e, None, CpuSSE2, Prefix_0XF3|Load|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
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movq, 0x0fd6, None, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
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movq, 0x0f6e, None, Cpu64, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
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movq, 0x0f6e, None, CpuSSE2|Cpu64, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
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movq, 0xf6f, None, CpuMMX, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
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movq, 0xf6e, None, Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
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movq, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
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// The segment register moves accept Reg64 so that a segment register
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// can be copied to a 64 bit register, and vice versa.
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movq, 0x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 }
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@ -9847,7 +9847,7 @@ const insn_template i386_optab[] =
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{ 1, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -9877,7 +9877,7 @@ const insn_template i386_optab[] =
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{ 1, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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