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sim: Fix some -Werror=shadow=compatible-local issues in aarch64/simulator.c
With GCC 14 -Werror=shadow=compatible-local flags the reuse of single
capital letters used in aarch64/cpustate.h enums
88 | expand_logical_immediate (uint32_t S, uint32_t R, uint32_t N)
| ~~~~~~~~~^
In file included from ../../binutils-gdb/sim/aarch64/aarch64-sim.h:27,
from ../../binutils-gdb/sim/aarch64/simulator.c:33:
217 | N = 1 << N_IDX
| ^
sim/aarch64/simulator.c: In function ‘expand_logical_immediate’:
sim/aarch64/simulator.c:88:60: error: declaration of ‘N’ shadows a previous local [-Werror=shadow=compatible-local]
sim/aarch64/cpustate.h:217:3: note: shadowed declaration is here
This commit is contained in:
Mark Wielaard
parent
865e469c60
commit
c2625a463f
@ -85,7 +85,7 @@
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while (0)
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static uint64_t
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expand_logical_immediate (uint32_t S, uint32_t R, uint32_t N)
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expand_logical_immediate (uint32_t s, uint32_t r, uint32_t n)
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{
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uint64_t mask;
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uint64_t imm;
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@ -93,38 +93,38 @@ expand_logical_immediate (uint32_t S, uint32_t R, uint32_t N)
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/* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
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(in other words, right rotated by R), then replicated. */
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if (N != 0)
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if (n != 0)
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{
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simd_size = 64;
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mask = 0xffffffffffffffffull;
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}
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else
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{
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switch (S)
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switch (s)
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{
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case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break;
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case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
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case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
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case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
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case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
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case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; s &= 0xf; break;
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case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; s &= 0x7; break;
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case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; s &= 0x3; break;
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case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; s &= 0x1; break;
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default: return 0;
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}
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mask = (1ull << simd_size) - 1;
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/* Top bits are IGNORED. */
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R &= simd_size - 1;
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r &= simd_size - 1;
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}
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/* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
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if (S == simd_size - 1)
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if (s == simd_size - 1)
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return 0;
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/* S+1 consecutive bits to 1. */
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/* NOTE: S can't be 63 due to detection above. */
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imm = (1ull << (S + 1)) - 1;
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imm = (1ull << (s + 1)) - 1;
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/* Rotate to the left by simd_size - R. */
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if (R != 0)
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imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
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if (r != 0)
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imm = ((imm << (simd_size - r)) & mask) | (imm >> r);
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/* Replicate the value according to SIMD size. */
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switch (simd_size)
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@ -153,11 +153,11 @@ aarch64_init_LIT_table (void)
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for (index = 0; index < LI_TABLE_SIZE; index++)
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{
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uint32_t N = uimm (index, 12, 12);
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uint32_t n = uimm (index, 12, 12);
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uint32_t immr = uimm (index, 11, 6);
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uint32_t imms = uimm (index, 5, 0);
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LITable [index] = expand_logical_immediate (imms, immr, N);
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LITable [index] = expand_logical_immediate (imms, immr, n);
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}
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}
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@ -9925,14 +9925,14 @@ dexLogicalImmediate (sim_cpu *cpu)
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/* 32 bit operations must have N = 0 or else we have an UNALLOC. */
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uint32_t size = INSTR (31, 31);
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uint32_t N = INSTR (22, 22);
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uint32_t n = INSTR (22, 22);
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/* uint32_t immr = INSTR (21, 16);. */
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/* uint32_t imms = INSTR (15, 10);. */
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uint32_t index = INSTR (22, 10);
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uint64_t bimm64 = LITable [index];
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uint32_t dispatch = INSTR (30, 29);
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if (~size & N)
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if (~size & n)
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HALT_UNALLOC;
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if (!bimm64)
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@ -10338,12 +10338,12 @@ dexBitfieldImmediate (sim_cpu *cpu)
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uint32_t dispatch;
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uint32_t imms;
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uint32_t size = INSTR (31, 31);
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uint32_t N = INSTR (22, 22);
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uint32_t n = INSTR (22, 22);
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/* 32 bit operations must have immr[5] = 0 and imms[5] = 0. */
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/* or else we have an UNALLOC. */
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uint32_t immr = INSTR (21, 16);
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if (~size & N)
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if (~size & n)
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HALT_UNALLOC;
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if (!size && uimm (immr, 5, 5))
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@ -10429,12 +10429,12 @@ dexExtractImmediate (sim_cpu *cpu)
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/* 64 bit operations must have N = 1 or else we have an UNALLOC. */
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uint32_t dispatch;
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uint32_t size = INSTR (31, 31);
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uint32_t N = INSTR (22, 22);
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uint32_t n = INSTR (22, 22);
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/* 32 bit operations must have imms[5] = 0
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or else we have an UNALLOC. */
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uint32_t imms = INSTR (15, 10);
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if (size ^ N)
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if (size ^ n)
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HALT_UNALLOC;
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if (!size && uimm (imms, 5, 5))
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@ -10509,11 +10509,11 @@ dexLoadUnscaledImmediate (sim_cpu *cpu)
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instr[20,12] = simm9
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instr[9,5] = rn may be SP. */
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/* unsigned rt = INSTR (4, 0); */
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uint32_t V = INSTR (26, 26);
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uint32_t v = INSTR (26, 26);
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uint32_t dispatch = ((INSTR (31, 30) << 2) | INSTR (23, 22));
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int32_t imm = simm32 (aarch64_get_instr (cpu), 20, 12);
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if (!V)
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if (!v)
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{
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/* GReg operations. */
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switch (dispatch)
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@ -10879,12 +10879,12 @@ dexLoadImmediatePrePost (sim_cpu *cpu)
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instr[9,5] = Rn may be SP.
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instr[4,0] = Rt */
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uint32_t V = INSTR (26, 26);
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uint32_t v = INSTR (26, 26);
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uint32_t dispatch = ((INSTR (31, 30) << 2) | INSTR (23, 22));
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int32_t imm = simm32 (aarch64_get_instr (cpu), 20, 12);
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WriteBack wb = INSTR (11, 11);
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if (!V)
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if (!v)
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{
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/* GReg operations. */
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switch (dispatch)
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@ -10956,7 +10956,7 @@ dexLoadRegisterOffset (sim_cpu *cpu)
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instr[9,5] = rn
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instr[4,0] = rt. */
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uint32_t V = INSTR (26, 26);
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uint32_t v = INSTR (26, 26);
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uint32_t dispatch = ((INSTR (31, 30) << 2) | INSTR (23, 22));
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Scaling scale = INSTR (12, 12);
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Extension extensionType = INSTR (15, 13);
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@ -10968,7 +10968,7 @@ dexLoadRegisterOffset (sim_cpu *cpu)
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if (extensionType == UXTX || extensionType == SXTX)
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extensionType = NoExtension;
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if (!V)
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if (!v)
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{
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/* GReg operations. */
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switch (dispatch)
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@ -11034,11 +11034,11 @@ dexLoadUnsignedImmediate (sim_cpu *cpu)
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instr[9,5] = rn may be SP.
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instr[4,0] = rt. */
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uint32_t V = INSTR (26,26);
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uint32_t v = INSTR (26,26);
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uint32_t dispatch = ((INSTR (31, 30) << 2) | INSTR (23, 22));
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uint32_t imm = INSTR (21, 10);
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if (!V)
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if (!v)
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{
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/* GReg operations. */
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switch (dispatch)
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@ -11526,13 +11526,13 @@ vec_reg (unsigned v, unsigned o)
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/* Load multiple N-element structures to M consecutive registers. */
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static void
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vec_load (sim_cpu *cpu, uint64_t address, unsigned N, unsigned M)
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vec_load (sim_cpu *cpu, uint64_t address, unsigned n, unsigned m)
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{
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int all = INSTR (30, 30);
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unsigned size = INSTR (11, 10);
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unsigned vd = INSTR (4, 0);
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unsigned rpt = (N == M) ? 1 : M;
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unsigned selem = N;
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unsigned rpt = (n == m) ? 1 : m;
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unsigned selem = n;
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unsigned i, j, k;
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switch (size)
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@ -11634,13 +11634,13 @@ LD1_4 (sim_cpu *cpu, uint64_t address)
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/* Store multiple N-element structures from M consecutive registers. */
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static void
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vec_store (sim_cpu *cpu, uint64_t address, unsigned N, unsigned M)
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vec_store (sim_cpu *cpu, uint64_t address, unsigned n, unsigned m)
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{
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int all = INSTR (30, 30);
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unsigned size = INSTR (11, 10);
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unsigned vd = INSTR (4, 0);
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unsigned rpt = (N == M) ? 1 : M;
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unsigned selem = N;
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unsigned rpt = (n == m) ? 1 : m;
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unsigned selem = n;
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unsigned i, j, k;
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switch (size)
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