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RISC-V: Add macro-only operands to validate_riscv_insn

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Although they are not (and should not be) reachable, following macro-only
operands are parsed in the `validate_riscv_insn' function and ignored.
That function also notes that they are macro-only.

-   "A"
-   "B"
-   "I"

Following this convention, this commit adds three remaining macro-only
operands to this function.  By doing this, we could instead choose to reject
those operands from appearing in regular instructions later.

-   "c"   (used by call, tail and jump macros)
-   "VM"  (used by vmsge.vx and vmsgeu.vx macros)
-   "VT"  (likewise)

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT"
	macro-only operand types.
This commit is contained in:
Tsukasa OI 2022-08-07 14:57:00 +09:00
parent 90eca71113
commit c1ecdee7e0
1 changed files with 3 additions and 0 deletions
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3
gas/config/tc-riscv.c
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@ -1203,6 +1203,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'j':
case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
case 'M': break; /* Macro operand, must be a mask register. */
case 'T': break; /* Macro operand, must be a vector register. */
default:
goto unknown_validate_operand;
}
@ -1214,6 +1216,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break; /* Macro operand, must be symbol. */
case 'B': break; /* Macro operand, must be symbol or constant. */
case 'c': break; /* Macro operand, must be symbol or constant. */
case 'I': break; /* Macro operand, must be constant. */
case 'D': /* RD, floating point. */
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;