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MIPS/LD/testsuite: Correct relocation addends in VxWorks tests
Fix commit171191bac5
("Add support for STT_IFUNC"), <https://sourceware.org/ml/binutils/2008-12/msg00052.html>, commite04d7088af
("PR ld/14088: Always display addend as signed hex number"), <https://sourceware.org/ml/binutils/2012-05/msg00123.html> and commit343dbc36ff
("Print addend as signed in objdump"), <https://sourceware.org/ml/binutils/2012-05/msg00163.html> regressions: FAIL: VxWorks executable test 1 (dynamic) FAIL: ld-mips-elf/vxworks-forced-local-1 seen with `mips-vxworks' and `mipsel-vxworks' targets and adjust dump patterns according to changes made to the presentation of relocation addends in `readelf -r' and `objdump -r' output. ld/ * testsuite/ld-mips-elf/vxworks-forced-local-1.d: Correct the presentation of relocation addends. * testsuite/ld-mips-elf/vxworks1-lib.rd: Likewise. * testsuite/ld-mips-elf/vxworks1.dd: Likewise. * testsuite/ld-mips-elf/vxworks1.rd: Likewise.
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@ -1,3 +1,11 @@
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2017-02-01 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/ld-mips-elf/vxworks-forced-local-1.d: Correct the
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presentation of relocation addends.
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* testsuite/ld-mips-elf/vxworks1-lib.rd: Likewise.
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* testsuite/ld-mips-elf/vxworks1.dd: Likewise.
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* testsuite/ld-mips-elf/vxworks1.rd: Likewise.
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2017-02-01 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/ld-mips-elf/tls-multi-got-1-1.s: Place `tlsvar_ld'
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@ -5,8 +5,8 @@
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Relocation section '\.rela\.dyn' .*
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.*
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0008140c 00000002 R_MIPS_32 *00080810
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00081410 00000002 R_MIPS_32 *00080814
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00081414 00000002 R_MIPS_32 *00080818
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0008140c 00000002 R_MIPS_32 *80810
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00081410 00000002 R_MIPS_32 *80814
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00081414 00000002 R_MIPS_32 *80818
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00081418 00000302 R_MIPS_32 *00000000 *bar \+ 0
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#pass
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@ -4,9 +4,9 @@ Relocation section '\.rela\.dyn' at offset .* contains .* entries:
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00080c0c .*05 R_MIPS_HI16 00000000 __GOTT_BASE__ \+ 0
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00080c10 .*06 R_MIPS_LO16 00000000 __GOTT_BASE__ \+ 0
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00080c14 .*01 R_MIPS_16 00000000 __GOTT_INDEX__ \+ 0
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0008141c 00000002 R_MIPS_32 00080c5c
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00081800 00000002 R_MIPS_32 00080c5c
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00081804 00000002 R_MIPS_32 00081800
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0008141c 00000002 R_MIPS_32 80c5c
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00081800 00000002 R_MIPS_32 80c5c
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00081804 00000002 R_MIPS_32 81800
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00081808 .*02 R_MIPS_32 00081808 dglobal \+ 0
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0008180c .*02 R_MIPS_32 00000000 dexternal \+ 0
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00081420 .*02 R_MIPS_32 00081c00 x \+ 0
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@ -15,9 +15,9 @@ Disassembly of section \.plt:
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80818: 1000fff9 b 80800 <_PROCEDURE_LINKAGE_TABLE_>
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8081c: 24180000 li t8,0
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80820: 3c190008 lui t9,0x8
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80820: R_MIPS_HI16 _GLOBAL_OFFSET_TABLE_\+0xfffffff0
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80820: R_MIPS_HI16 _GLOBAL_OFFSET_TABLE_-0x10
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80824: 27391400 addiu t9,t9,5120
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80824: R_MIPS_LO16 _GLOBAL_OFFSET_TABLE_\+0xfffffff0
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80824: R_MIPS_LO16 _GLOBAL_OFFSET_TABLE_-0x10
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80828: 8f390000 lw t9,0\(t9\)
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8082c: 00000000 nop
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80830: 03200008 jr t9
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@ -25,9 +25,9 @@ Disassembly of section \.plt:
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80838: 1000fff1 b 80800 <_PROCEDURE_LINKAGE_TABLE_>
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8083c: 24180001 li t8,1
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80840: 3c190008 lui t9,0x8
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80840: R_MIPS_HI16 _GLOBAL_OFFSET_TABLE_\+0xfffffff4
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80840: R_MIPS_HI16 _GLOBAL_OFFSET_TABLE_-0xc
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80844: 27391404 addiu t9,t9,5124
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80844: R_MIPS_LO16 _GLOBAL_OFFSET_TABLE_\+0xfffffff4
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80844: R_MIPS_LO16 _GLOBAL_OFFSET_TABLE_-0xc
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80848: 8f390000 lw t9,0\(t9\)
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8084c: 00000000 nop
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80850: 03200008 jr t9
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@ -25,8 +25,8 @@ Relocation section '\.rela\.plt\.unloaded' at offset .* contains 8 entries:
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00080800 .*05 R_MIPS_HI16 00081410 _GLOBAL_OFFSET_TABLE_ \+ 0
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00080804 .*06 R_MIPS_LO16 00081410 _GLOBAL_OFFSET_TABLE_ \+ 0
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00081400 .*02 R_MIPS_32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 18
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00080820 .*05 R_MIPS_HI16 00081410 _GLOBAL_OFFSET_TABLE_ \+ fffffff0
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00080824 .*06 R_MIPS_LO16 00081410 _GLOBAL_OFFSET_TABLE_ \+ fffffff0
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00080820 .*05 R_MIPS_HI16 00081410 _GLOBAL_OFFSET_TABLE_ - 10
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00080824 .*06 R_MIPS_LO16 00081410 _GLOBAL_OFFSET_TABLE_ - 10
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00081404 .*02 R_MIPS_32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 38
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00080840 .*05 R_MIPS_HI16 00081410 _GLOBAL_OFFSET_TABLE_ \+ fffffff4
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00080844 .*06 R_MIPS_LO16 00081410 _GLOBAL_OFFSET_TABLE_ \+ fffffff4
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00080840 .*05 R_MIPS_HI16 00081410 _GLOBAL_OFFSET_TABLE_ - c
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00080844 .*06 R_MIPS_LO16 00081410 _GLOBAL_OFFSET_TABLE_ - c
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