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Clean up F-unit assembly and tests.
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@ -1,3 +1,9 @@
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2000-04-22 Timothy Wall <twall@cygnus.com>
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* config/tc-ia64.c (pseudo_func[]): Add new "nat" entry equivalent
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to "natval".
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(operand_match): Conditionally insert default bit values for IMMU9.
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2000-04-14 Matthew Green <mrg@cygnus.com>
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* configure.in: Add NetBSD/sparc ELF and NetBSD/sparc64 support.
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@ -448,7 +448,7 @@ pseudo_func[] =
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{ "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
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/* fclass constants: */
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{ "natval", PSEUDO_FUNC_CONST, { 0x100 } },
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{ "nat", PSEUDO_FUNC_CONST, { 0x100 } },
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{ "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
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{ "snan", PSEUDO_FUNC_CONST, { 0x040 } },
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{ "pos", PSEUDO_FUNC_CONST, { 0x001 } },
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@ -457,6 +457,8 @@ pseudo_func[] =
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{ "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
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{ "norm", PSEUDO_FUNC_CONST, { 0x010 } },
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{ "inf", PSEUDO_FUNC_CONST, { 0x020 } },
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{ "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
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};
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/* 41-bit nop opcodes (one per unit): */
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@ -3815,7 +3817,6 @@ operand_match (idesc, index, e)
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case IA64_OPND_IMMU2:
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case IA64_OPND_IMMU7a:
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case IA64_OPND_IMMU7b:
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case IA64_OPND_IMMU9:
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case IA64_OPND_IMMU21:
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case IA64_OPND_IMMU24:
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case IA64_OPND_MBTYPE4:
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@ -3827,6 +3828,18 @@ operand_match (idesc, index, e)
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return 1;
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break;
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case IA64_OPND_IMMU9:
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bits = operand_width (idesc->operands[index]);
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if (e->X_op == O_constant
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&& (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
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{
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int lobits = e->X_add_number & 0x3;
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if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
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e->X_add_number |= (bfd_vma)0x3;
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return 1;
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}
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break;
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case IA64_OPND_IMM44:
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/* least 16 bits must be zero */
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if ((e->X_add_number & 0xffff) != 0)
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@ -1,3 +1,8 @@
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2000-04-22 Timothy Wall <twall@cygnus.com>
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* gas/ia64/opc-f.d: Disassemble zeroes to verify break.f.
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* gas/ia64/opc-f.s: Add an explicit stop to make IAS output match.
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Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
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David Mosberger <davidm@hpl.hp.com>
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Timothy Wall <twall@cygnus.com>
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@ -1,4 +1,4 @@
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# objdump: -d
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# objdump: -d --disassemble-zeroes
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# name: ia64 opc-f
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.*: +file format .*
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@ -469,16 +469,16 @@ Disassembly of section \.text:
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996: 40 38 14 0c 76 00 xma\.hu f4=f5,f6,f7
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99c: 00 00 04 00 nop\.i 0x0
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9a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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9a6: 40 00 14 0c 74 00 xma\.l f4=f5,f6,f0
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9a6: 40 00 14 0c 74 00 xmpy\.l f4=f5,f6
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9ac: 00 00 04 00 nop\.i 0x0
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9b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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9b6: 40 00 14 0c 74 00 xma\.l f4=f5,f6,f0
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9b6: 40 00 14 0c 74 00 xmpy\.l f4=f5,f6
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9bc: 00 00 04 00 nop\.i 0x0
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9c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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9c6: 40 00 14 0c 77 00 xma\.h f4=f5,f6,f0
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9c6: 40 00 14 0c 77 00 xmpy\.h f4=f5,f6
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9cc: 00 00 04 00 nop\.i 0x0
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9d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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9d6: 40 00 14 0c 76 00 xma\.hu f4=f5,f6,f0
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9d6: 40 00 14 0c 76 00 xmpy\.hu f4=f5,f6
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9dc: 00 00 04 00 nop\.i 0x0
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9e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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9e6: 40 38 14 0c 70 00 fselect f4=f5,f6,f7
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@ -1210,8 +1210,8 @@ Disassembly of section \.text:
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1906: 00 e7 ff 10 07 00 fchkf\.s3 0 <_start>
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190c: 00 00 04 00 nop\.i 0x0
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1910: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
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\.\.\.
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191e: 04 00 0c 00 nop\.i 0x0
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1922: 00 00 01 00 00 00 \[MFI\] nop\.m 0x0
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1928: 00 02 00 00 00 00 nop\.f 0x0
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192e: 04 00 00 00 nop\.i 0x0
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1916: 00 00 00 00 00 00 break\.f 0x0
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191c: 00 00 04 00 nop\.i 0x0
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1920: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
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1926: 00 00 00 02 00 00 nop\.f 0x0
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192c: 00 00 04 00 nop\.i 0x0;;
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@ -477,5 +477,5 @@ _start:
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fchkf.s3 _start
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break.f 0
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nop.f 0
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nop.f 0;;
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